diff --git a/src/V3SenExprBuilder.h b/src/V3SenExprBuilder.h
index 6b70e7d23..86b09d03f 100644
--- a/src/V3SenExprBuilder.h
+++ b/src/V3SenExprBuilder.h
@@ -94,24 +94,21 @@ class SenExprBuilder final {
const auto rdCurr = [=]() { return getCurr(exprp); };
AstNode* scopeExprp = exprp;
- if (AstVarRef* const refp = VN_CAST(exprp, VarRef)) {
- scopeExprp = refp->varScopep()->varp();
- }
+ if (AstVarRef* const refp = VN_CAST(exprp, VarRef)) scopeExprp = refp->varScopep();
// Create the 'previous value' variable
auto it = m_prev.find(*scopeExprp);
if (it == m_prev.end()) {
- // For readability, use the scoped signal name if the trigger is a simple AstVarRef
- string name;
- if (AstVarRef* const refp = VN_CAST(exprp, VarRef)) {
- AstVarScope* vscp = refp->varScopep();
- name = "__Vtrigrprev__" + vscp->scopep()->nameDotless() + "__"
- + vscp->varp()->name();
- } else {
- name = m_prevNames.get(exprp);
- }
-
AstVarScope* prevp;
if (m_scopep->isTop()) {
+ // For readability, use the scoped signal name if the trigger is a simple AstVarRef
+ string name;
+ if (AstVarRef* const refp = VN_CAST(exprp, VarRef)) {
+ AstVarScope* const vscp = refp->varScopep();
+ name = "__" + vscp->scopep()->nameDotless() + "__" + vscp->varp()->name();
+ name = m_prevNames.get(name);
+ } else {
+ name = m_prevNames.get(exprp);
+ }
prevp = m_scopep->createTemp(name, exprp->dtypep());
} else {
AstVar* const varp = new AstVar{flp, VVarType::BLOCKTEMP, m_prevNames.get(exprp),
diff --git a/test_regress/t/t_event_control_scope_var.pl b/test_regress/t/t_event_control_scope_var.pl
new file mode 100755
index 000000000..d78b3ff03
--- /dev/null
+++ b/test_regress/t/t_event_control_scope_var.pl
@@ -0,0 +1,22 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+ verilator_flags2 => ['-fno-inline', '-Wno-WIDTHTRUNC'],
+ );
+
+execute(
+ check_finished => 1,
+ );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_event_control_scope_var.v b/test_regress/t/t_event_control_scope_var.v
new file mode 100644
index 000000000..e976b1c60
--- /dev/null
+++ b/test_regress/t/t_event_control_scope_var.v
@@ -0,0 +1,61 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module test_mod(input reg clk, input reg reset, output integer result);
+ always @(reset) begin
+ result <= 1;
+ end
+endmodule
+
+module Dut(input clk);
+ integer num;
+ integer result1;
+ integer result2;
+ reg reset1;
+ reg reset2;
+ initial begin
+ reset1 = $random;
+ reset2 = $random;
+ end
+ always @(posedge clk) begin
+ num <= num + 1;
+ if (num == 5) begin
+ reset1 <= 1'b1;
+ end
+ if (num == 10) begin
+ // display to prevent optimalization
+ $display("result1: %d", result1);
+ $display("result2: %d", result2);
+ $write("*-* All Finished *-*\n");
+ $finish;
+ end
+ end
+ always @(reset1) begin
+ reset2 <= t.reset;
+ end
+
+ test_mod t (
+ .clk(clk),
+ .reset(reset1),
+ .result(result1)
+ );
+ test_mod t2 (
+ .clk(clk),
+ .reset(reset2),
+ .result(result2));
+ endmodule
+
+module Dut_wrapper(input clk);
+
+ Dut d(.clk(clk));
+ Dut d2(.clk(clk));
+endmodule
+
+module t (/*AUTOARG*/
+ clk);
+ input clk;
+ Dut_wrapper d_w(.clk(clk));
+endmodule
diff --git a/test_regress/t/t_protect_ids_key.out b/test_regress/t/t_protect_ids_key.out
index 5f362ac43..117c4a728 100644
--- a/test_regress/t/t_protect_ids_key.out
+++ b/test_regress/t/t_protect_ids_key.out
@@ -28,7 +28,7 @@
-
+
diff --git a/test_regress/t/t_xml_debugcheck.out b/test_regress/t/t_xml_debugcheck.out
index ff409ca14..e99f614c6 100644
--- a/test_regress/t/t_xml_debugcheck.out
+++ b/test_regress/t/t_xml_debugcheck.out
@@ -22,7 +22,7 @@
-
+
@@ -49,7 +49,7 @@
-
+
@@ -607,7 +607,7 @@
-
+
@@ -618,7 +618,7 @@
-
+
@@ -1688,7 +1688,7 @@
-
+