diff --git a/Changes b/Changes
index 01527e68f..03be43810 100644
--- a/Changes
+++ b/Changes
@@ -7,6 +7,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ***  Add $feof, $fgetc, $fgets, $fflush, $fscanf, $sscanf. [Holger Waechtler]
 
+***  Add $stime. [Holger Waechtler]
+
 ***  Add $random.
 
 **** Fix verilator_includer not being installed properly.  [Holger Waechtler]
diff --git a/bin/verilator b/bin/verilator
index edd6485a5..848dfa07c 100755
--- a/bin/verilator
+++ b/bin/verilator
@@ -1535,8 +1535,8 @@ Verilator does not perform warning checking on uwires, it treats the uwire
 keyword as if it were the normal wire keyword.
 
 =item $bits, $countones, $error, $fatal, $finish, $info, $isunknown,
-$onehot, $onehot0, $readmemb, $readmemh, $signed, $stop, $time, $unsigned,
-$warning.
+$onehot, $onehot0, $readmemb, $readmemh, $signed, $stime, $stop, $time,
+$unsigned, $warning.
 
 Generally supported.
 
diff --git a/src/verilog.l b/src/verilog.l
index f198556c4..12a600a99 100644
--- a/src/verilog.l
+++ b/src/verilog.l
@@ -155,6 +155,7 @@ escid	\\[^ \t\f\r\n]+
   "$setuphold"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
   "$skew"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
   "$sscanf"		{yylval.fileline = CRELINE(); return yD_SSCANF;}
+  "$stime"		{yylval.fileline = CRELINE(); return yD_STIME;}
   "$stop"		{yylval.fileline = CRELINE(); return yD_STOP;}
   "$time"		{yylval.fileline = CRELINE(); return yD_TIME;}
   "$timeskew"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
diff --git a/src/verilog.y b/src/verilog.y
index 829af5900..4ebbbac02 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -243,6 +243,7 @@ class AstSenTree;
 %token<fileline>	yD_READMEMH	"$readmemh"
 %token<fileline>	yD_SIGNED	"$signed"
 %token<fileline>	yD_SSCANF	"$sscanf"
+%token<fileline>	yD_STIME	"$stime"
 %token<fileline>	yD_STOP		"$stop"
 %token<fileline>	yD_TIME		"$time"
 %token<fileline>	yD_UNSIGNED	"$unsigned"
@@ -1099,6 +1100,7 @@ exprNoStr:	expr yP_OROR expr			{ $$ = new AstLogOr	($2,$1,$3); }
 	|	yD_RANDOM '(' ')'			{ $$ = new AstRand($1); }
 	|	yD_RANDOM				{ $$ = new AstRand($1); }
 	|	yD_SIGNED '(' expr ')'			{ $$ = new AstSigned($1,$3); }
+	|	yD_STIME				{ $$ = new AstSel($1,new AstTime($1),0,32); }
 	|	yD_TIME					{ $$ = new AstTime($1); }
 	|	yD_UNSIGNED '(' expr ')'		{ $$ = new AstUnsigned($1,$3); }
 
diff --git a/test_regress/t/t_sys_time.pl b/test_regress/t/t_sys_time.pl
new file mode 100755
index 000000000..e2a0c97fa
--- /dev/null
+++ b/test_regress/t/t_sys_time.pl
@@ -0,0 +1,17 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_sys_time.v b/test_regress/t/t_sys_time.v
new file mode 100644
index 000000000..19f280074
--- /dev/null
+++ b/test_regress/t/t_sys_time.v
@@ -0,0 +1,34 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2008 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer 	cyc=0;
+
+   reg [63:0]	time64;
+
+
+   // Test loop
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      if (cyc==0) begin
+      end
+      else if (cyc<10) begin
+      end
+      else if (cyc<90) begin
+	 time64 = $time;
+	 if ($stime != time64[31:0]) $stop;
+      end
+      else if (cyc==99) begin
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+
+endmodule