diff --git a/Changes b/Changes index de6958566..b9bd5e3df 100644 --- a/Changes +++ b/Changes @@ -32,6 +32,7 @@ Verilator 5.045 devel * Fix WIDTHEXTEND suppression on add/sub with single-bit signal. [Dan Katz] * Fix segfault in V3Slice (#6899). [Pawel Kojma, Antmicro Ltd.] * Fix signedness of packed array (#6901) (#6902). [Yutetsu TAKATSUKASA] +* Fix assignment of queue from unpacked array (#6906). Verilator 5.044 2026-01-01 diff --git a/include/verilated_types.h b/include/verilated_types.h index b7463e835..7a0c40bc7 100644 --- a/include/verilated_types.h +++ b/include/verilated_types.h @@ -38,6 +38,10 @@ #include #include +class VlProcess; +template +class VlUnpacked; + //========================================================================= // Debug functions @@ -104,8 +108,6 @@ constexpr IData VL_CLOG2_CE_Q(QData lhs) VL_PURE { } // Metadata of processes -class VlProcess; - using VlProcessRef = std::shared_ptr; class VlProcess final { @@ -531,6 +533,10 @@ public: m_deque.resize(size, atDefault()); } } + // Unpacked array new[]() becomes a renew_copy() + template + void renew_copy(size_t size, const VlUnpacked& rhs); + void resize(size_t size) { m_deque.resize(size, atDefault()); } // function void q.push_front(value) @@ -1615,6 +1621,16 @@ std::string VL_TO_STRING(const VlUnpacked& obj) { template struct VlContainsCustomStruct> : VlContainsCustomStruct {}; +template +template +void VlQueue::renew_copy( + size_t size, const VlUnpacked& rhs) { + clear(); + if (size == 0) return; + m_deque.resize(size, atDefault()); + for (size_t i = 0; i < std::min(size, N_UnpackedDepth); ++i) { m_deque[i] = rhs.m_storage[i]; } +} + //=================================================================== // Helper to apply the given indices to a target expression diff --git a/test_regress/t/t_queue_init.v b/test_regress/t/t_queue_init.v index 3efd86bcf..9d94c0407 100644 --- a/test_regress/t/t_queue_init.v +++ b/test_regress/t/t_queue_init.v @@ -4,33 +4,49 @@ // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop -`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - int a1[$] = '{12, 13}; - int a2[$] = {14, 15}; - int a3[$] = '{16}; - int a4[$] = {17}; + int a1[$] = '{12, 13}; + int a2[$] = {14, 15}; + int a3[$] = '{16}; + int a4[$] = {17}; - initial begin - `checkh(a1.size, 2); - `checkh(a1[0], 12); - `checkh(a1[1], 13); + int src[3], dest1[], dest2[]; - `checkh(a2.size, 2); - `checkh(a2[0], 14); - `checkh(a2[1], 15); + initial begin + `checkd(a1.size, 2); + `checkd(a1[0], 12); + `checkd(a1[1], 13); - `checkh(a3.size, 1); - `checkh(a3[0], 16); + `checkd(a2.size, 2); + `checkd(a2[0], 14); + `checkd(a2[1], 15); - `checkh(a4.size, 1); - `checkh(a4[0], 17); + `checkd(a3.size, 1); + `checkd(a3[0], 16); - $write("*-* All Finished *-*\n"); - $finish; - end + `checkd(a4.size, 1); + `checkd(a4[0], 17); + + src = '{2, 3, 4}; + dest1 = new[2] (src); + `checkd(dest1.size, 2); // {2, 3} + `checkd(dest1[0], 2); + `checkd(dest1[1], 3); + dest2 = new[4] (src); + `checkd(dest2.size, 4); // {2, 3, 4, 0}. + `checkd(dest2[0], 2); + `checkd(dest2[1], 3); + `checkd(dest2[2], 4); + `checkd(dest2[3], 0); + + $write("*-* All Finished *-*\n"); + $finish; + end endmodule