diff --git a/Changes b/Changes
index dbccd7377..6445c228c 100644
--- a/Changes
+++ b/Changes
@@ -11,6 +11,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
*** Support $readmem/$writemem with assoc arrarys. Closes #2100. [agrobman]
+**** Add parameter values in XML. #2110. [Pieter Kapsenberg]
+
**** Add error on misused define. [Topa Tota]
diff --git a/src/V3Dead.cpp b/src/V3Dead.cpp
index 265738e2a..cc16421c3 100644
--- a/src/V3Dead.cpp
+++ b/src/V3Dead.cpp
@@ -299,7 +299,7 @@ private:
return (!nodep->isSigPublic() // Can't elim publics!
&& !nodep->isIO()
&& ((nodep->isTemp() && !nodep->isTrace())
- || (nodep->isParam() && !nodep->isTrace())
+ || (nodep->isParam() && !nodep->isTrace() && !v3Global.opt.xmlOnly())
|| m_elimUserVars)); // Post-Trace can kill most anything
}
diff --git a/src/V3EmitXml.cpp b/src/V3EmitXml.cpp
index 86985506a..c1f09316c 100644
--- a/src/V3EmitXml.cpp
+++ b/src/V3EmitXml.cpp
@@ -140,6 +140,8 @@ class EmitXmlFileVisitor : public AstNVisitor {
if (nodep->isSigPublic()) puts(" public=\"true\"");
if (nodep->isSigUserRdPublic()) puts(" public_flat_rd=\"true\"");
if (nodep->isSigUserRWPublic()) puts(" public_flat_rw=\"true\"");
+ if (nodep->isGParam()) puts(" param=\"true\"");
+ else if (nodep->isParam()) puts(" localparam=\"true\"");
if (nodep->attrScBv()) puts(" sc_bv=\"true\"");
if (nodep->attrScClocked()) puts(" sc_clock=\"true\"");
if (nodep->attrSFormat()) puts(" sformat=\"true\"");
diff --git a/test_regress/t/t_xml_first.out b/test_regress/t/t_xml_first.out
index 064080960..d40bc7c59 100644
--- a/test_regress/t/t_xml_first.out
+++ b/test_regress/t/t_xml_first.out
@@ -12,7 +12,7 @@
- |
+ |
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@@ -22,57 +22,64 @@
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diff --git a/test_regress/t/t_xml_first.v b/test_regress/t/t_xml_first.v
index cf58091f8..8c87572c5 100644
--- a/test_regress/t/t_xml_first.v
+++ b/test_regress/t/t_xml_first.v
@@ -13,29 +13,30 @@ module t (/*AUTOARG*/
input [3:0] d;
output wire [3:0] q;
- logic [3:0] between;
+ logic [3:0] between;
- mod1 cell1 (.q(between),
- /*AUTOINST*/
- // Inputs
- .clk (clk),
- .d (d[3:0]));
+ mod1 #(.WIDTH(4))
+ cell1 (.q(between),
+ .clk (clk),
+ .d (d[3:0]));
- mod2 cell2 (.d(between),
- /*AUTOINST*/
- // Outputs
- .q (q[3:0]),
- // Inputs
- .clk (clk));
+ mod2
+ cell2 (.d(between),
+ .q (q[3:0]),
+ .clk (clk));
endmodule
module mod1
- (
- input clk,
- input [3:0] d,
- output logic [3:0] q
+ #(parameter WIDTH = 32)
+ (
+ input clk,
+ input [WIDTH-1:0] d,
+ output logic [WIDTH-1:0] q
);
+
+ localparam IGNORED = 1;
+
always @(posedge clk)
q <= d;