From 81915540de60f9a39c26cc82ef70e9a6007a8089 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Thu, 5 Nov 2009 19:26:44 -0500
Subject: [PATCH] Support "reg x [3][2]".

---
 Changes                | 2 ++
 src/verilog.y          | 2 +-
 test_regress/t/t_mem.v | 3 ++-
 3 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/Changes b/Changes
index c93aa5136..5c402f84d 100644
--- a/Changes
+++ b/Changes
@@ -12,6 +12,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ***  Support "reg [1:0][1:0][1:0]", bug176.  [Byron Bradley]
 
+***  Support "reg x [3][2]".
+
 ***  Support "program".
 
 * Verilator 3.720 2009/10/26
diff --git a/src/verilog.y b/src/verilog.y
index 0872f2ebb..5bc7d56f7 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -995,7 +995,7 @@ variable_dimension<rangep>:	// ==IEEE: variable_dimension
 	//UNSUP	'[' ']'					{ UNSUP }
 	//			// IEEE: unpacked_dimension
 		anyrange				{ $$ = $1; }
-	|	'[' constExpr ']'			{ $$ = new AstRange($1,$2,$2->cloneTree(true)); }
+	|	'[' constExpr ']'			{ $$ = new AstRange($1,new AstSub($1,$2, new AstConst($1,1)), new AstConst($1,0)); }
 	//			// IEEE: associative_dimension
 	//UNSUP	'[' data_type ']'			{ UNSUP }
 	//UNSUP	yP_BRASTAR ']'				{ UNSUP }
diff --git a/test_regress/t/t_mem.v b/test_regress/t/t_mem.v
index 341a8b703..128263f23 100644
--- a/test_regress/t/t_mem.v
+++ b/test_regress/t/t_mem.v
@@ -11,7 +11,8 @@ module t (/*AUTOARG*/
    input clk;
    integer cyc; initial cyc=1;
 
-   reg [7:0] memory8_16 [15:0];
+   // [16] is SV syntax for [15:0]
+   reg [7:0] memory8_16 [16];
 
    reg 	      m_we;
    reg [3:1]  m_addr;