From 80f5738544964ed03a780239c32e70d472cb652d Mon Sep 17 00:00:00 2001 From: Peter Monsson Date: Thu, 3 Sep 2020 14:09:47 +0200 Subject: [PATCH] Tests: Move t_rose t_fell and t_stable to a single test (#2530) --- test_regress/t/t_fell.v | 81 ------------------ test_regress/t/{t_fell.pl => t_past_funcs.pl} | 0 test_regress/t/{t_rose.v => t_past_funcs.v} | 24 ++++++ test_regress/t/t_rose.pl | 21 ----- test_regress/t/t_stable.pl | 21 ----- test_regress/t/t_stable.v | 85 ------------------- 6 files changed, 24 insertions(+), 208 deletions(-) delete mode 100644 test_regress/t/t_fell.v rename test_regress/t/{t_fell.pl => t_past_funcs.pl} (100%) rename test_regress/t/{t_rose.v => t_past_funcs.v} (71%) delete mode 100755 test_regress/t/t_rose.pl delete mode 100755 test_regress/t/t_stable.pl delete mode 100644 test_regress/t/t_stable.v diff --git a/test_regress/t/t_fell.v b/test_regress/t/t_fell.v deleted file mode 100644 index eff06f114..000000000 --- a/test_regress/t/t_fell.v +++ /dev/null @@ -1,81 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Peter Monsson. - -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; - integer cyc; initial cyc=2; - wire [31:0] in = cyc; - - Test test (/*AUTOINST*/ - // Inputs - .clk (clk), - .in (in[31:0])); - - Test2 test2 (/*AUTOINST*/ - // Inputs - .clk (clk), - .in (in[31:0])); - - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - end - -endmodule - -module Test (/*AUTOARG*/ - // Inputs - clk, in - ); - - input clk; - input [31:0] in; - - reg [31:0] dly0 = 1; - - // If called in an assertion, sequence, or property, the appropriate clocking event. - // Otherwise, if called in a disable condition or a clock expression in an assertion, sequence, or prop, explicit. - // Otherwise, if called in an action block of an assertion, the leading clock of the assertion is used. - // Otherwise, if called in a procedure, the inferred clock - // Otherwise, default clocking - - always @(posedge clk) begin - dly0 <= in; - // In clock expression - $write("in=%0d, dly0=%0d, fell=%0d, past=%0d\n", in, dly0, $fell(dly0), $past(dly0)); - if ($fell(dly0[4])) $stop; - end - - assert property (@(posedge clk) $fell(dly0) || dly0%2==1); -endmodule - - -module Test2 (/*AUTOARG*/ - // Inputs - clk, in - ); - - input clk; - input [31:0] in; - - reg [31:0] dly0 = 1; - - always @(posedge clk) begin - dly0 <= in; - if ($fell(dly0[31:4])) $stop; - end - - default clocking @(posedge clk); endclocking - assert property ($fell(dly0[0]) || dly0%2==1); -endmodule diff --git a/test_regress/t/t_fell.pl b/test_regress/t/t_past_funcs.pl similarity index 100% rename from test_regress/t/t_fell.pl rename to test_regress/t/t_past_funcs.pl diff --git a/test_regress/t/t_rose.v b/test_regress/t/t_past_funcs.v similarity index 71% rename from test_regress/t/t_rose.v rename to test_regress/t/t_past_funcs.v index 1eadaa61d..2ee24f4a5 100644 --- a/test_regress/t/t_rose.v +++ b/test_regress/t/t_past_funcs.v @@ -43,6 +43,8 @@ module Test (/*AUTOARG*/ input [31:0] in; reg [31:0] dly0 = 0; + reg [31:0] dly1 = 1; + reg [31:0] dly2 = -1; // If called in an assertion, sequence, or property, the appropriate clocking event. // Otherwise, if called in a disable condition or a clock expression in an assertion, sequence, or prop, explicit. @@ -52,12 +54,20 @@ module Test (/*AUTOARG*/ always @(posedge clk) begin dly0 <= in; + dly1 <= in; + dly2 <= in; // In clock expression $write("in=%0d, dly0=%0d, rose=%0d, past=%0d\n", in, dly0, $rose(dly0), $past(dly0)); if ($rose(dly0[4])) $stop; + if ($fell(dly1[4])) $stop; + if ($stable(dly2)) $stop; + if (!$changed(dly2)) $stop; end assert property (@(posedge clk) $rose(dly0) || dly0%2==0); + assert property (@(posedge clk) $fell(dly1) || dly1%2==1); + assert property (@(posedge clk) !$stable(dly2)); + assert property (@(posedge clk) $changed(dly2)); endmodule @@ -70,12 +80,26 @@ module Test2 (/*AUTOARG*/ input [31:0] in; reg [31:0] dly0; + reg [31:0] dly1 = 1; + reg [31:0] dly2; always @(posedge clk) begin dly0 <= in; + dly1 <= in; + dly2 <= in; if ($rose(dly0[31:4])) $stop; + if ($fell(dly1[31:4])) $stop; + if (!$stable(dly2[31:4])) $stop; + if ($changed(dly2[31:4])) $stop; end default clocking @(posedge clk); endclocking assert property ($rose(dly0[0]) || dly0%2==0); + + default clocking @(posedge clk); endclocking + assert property ($fell(dly1[0]) || dly1%2==1); + + default clocking @(posedge clk); endclocking + assert property ($stable(dly2[31:4])); + assert property (!$changed(dly2[31:4])); endmodule diff --git a/test_regress/t/t_rose.pl b/test_regress/t/t_rose.pl deleted file mode 100755 index c1a6773e9..000000000 --- a/test_regress/t/t_rose.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_stable.pl b/test_regress/t/t_stable.pl deleted file mode 100755 index c1a6773e9..000000000 --- a/test_regress/t/t_stable.pl +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/perl -if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } -# DESCRIPTION: Verilator: Verilog Test driver/expect definition -# -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. - -scenarios(simulator => 1); - -compile( - verilator_flags2 => ['--assert'], - ); - -execute( - check_finished => 1, - ); - -ok(1); -1; diff --git a/test_regress/t/t_stable.v b/test_regress/t/t_stable.v deleted file mode 100644 index 114a10f89..000000000 --- a/test_regress/t/t_stable.v +++ /dev/null @@ -1,85 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Peter Monsson. - -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; - integer cyc; initial cyc=1; - wire [31:0] in = cyc; - - Test test (/*AUTOINST*/ - // Inputs - .clk (clk), - .in (in[31:0])); - - Test2 test2 (/*AUTOINST*/ - // Inputs - .clk (clk), - .in (in[31:0])); - - - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - end - -endmodule - -module Test (/*AUTOARG*/ - // Inputs - clk, in - ); - - input clk; - input [31:0] in; - - reg [31:0] dly0 = -1; - - // If called in an assertion, sequence, or property, the appropriate clocking event. - // Otherwise, if called in a disable condition or a clock expression in an assertion, sequence, or prop, explicit. - // Otherwise, if called in an action block of an assertion, the leading clock of the assertion is used. - // Otherwise, if called in a procedure, the inferred clock - // Otherwise, default clocking - - always @(posedge clk) begin - dly0 <= in; - // In clock expression - $write("dly0=%0d, in=%0d, stable=%0d, past=%0d\n", dly0, in, $stable(dly0), $past(dly0)); - if ($stable(dly0)) $stop; - if (!$changed(dly0)) $stop; - end - - assert property (@(posedge clk) !$stable(dly0)); - assert property (@(posedge clk) $changed(dly0)); -endmodule - -module Test2 (/*AUTOARG*/ - // Inputs - clk, in - ); - - input clk; - input [31:0] in; - - reg [31:0] dly0; - - always @(posedge clk) begin - dly0 <= in; - if (!$stable(dly0[31:4])) $stop; - if ($changed(dly0[31:4])) $stop; - end - - default clocking @(posedge clk); endclocking - assert property ($stable(dly0[31:4])); - assert property (!$changed(dly0[31:4])); -endmodule