diff --git a/src/V3AssertNfa.cpp b/src/V3AssertNfa.cpp
index f71606ea4..106e634c2 100644
--- a/src/V3AssertNfa.cpp
+++ b/src/V3AssertNfa.cpp
@@ -2014,9 +2014,7 @@ class AssertNfaVisitor final : public VNVisitor {
         VL_DO_DANGLING(pushDeletep(innerPropp), innerPropp);
     }
 
-    // Hoist a leading clocking event (IEEE 1800-2023 16.7:
-    // sequence_expr ::= clocking_event sequence_expr) from the sequence body onto
-    // the enclosing assertion clock. Returns true if E_UNSUPPORTED was emitted.
+    // Hoist a leading clocking event (IEEE 1800-2023 16.7):
     bool hoistClockedSeq(AstPropSpec* specp) {
         while (AstSClocked* const clockedp = VN_CAST(specp->propp(), SClocked)) {
             if (specp->sensesp()) {
diff --git a/src/V3AstNodeExpr.h b/src/V3AstNodeExpr.h
index 47e290711..f6e0d98f5 100644
--- a/src/V3AstNodeExpr.h
+++ b/src/V3AstNodeExpr.h
@@ -2240,7 +2240,7 @@ public:
     ASTGEN_MEMBERS_AstSClocked;
     string emitVerilog() override { V3ERROR_NA_RETURN(""); }
     string emitC() override { V3ERROR_NA_RETURN(""); }
-    bool cleanOut() const override { V3ERROR_NA_RETURN(""); }
+    bool cleanOut() const override { V3ERROR_NA_RETURN(false); }
 };
 class AstSConsRep final : public AstNodeExpr {
     // Consecutive repetition [*N], [*N:M], [+], [*] (IEEE 1800-2023 16.9.2)
diff --git a/src/V3EmitV.cpp b/src/V3EmitV.cpp
index 4201a0ad5..db0798e38 100644
--- a/src/V3EmitV.cpp
+++ b/src/V3EmitV.cpp
@@ -1142,6 +1142,13 @@ class EmitVBaseVisitorConst VL_NOT_FINAL : public VNVisitorConst {
         puts(") ");
         iterateConst(nodep->propp());
     }
+    void visit(AstSClocked* nodep) override {
+        puts("@(");
+        iterateConst(nodep->sensesp());
+        puts(") ");
+        iterateConst(nodep->exprp());
+        puts("\n");
+    }
     void visit(AstPropAlways* nodep) override {
         puts(nodep->isStrong() ? "s_always" : "always");
         if (!VN_IS(nodep->loBoundp(), Unbounded) || !VN_IS(nodep->hiBoundp(), Unbounded)) {
diff --git a/test_regress/t/t_assert_seq_clocking.v b/test_regress/t/t_assert_seq_clocking.v
index db1bdaf24..b835acb85 100644
--- a/test_regress/t/t_assert_seq_clocking.v
+++ b/test_regress/t/t_assert_seq_clocking.v
@@ -4,6 +4,11 @@
 // SPDX-FileCopyrightText: 2026 PlanV GmbH
 // SPDX-License-Identifier: CC0-1.0
 
+// verilog_format: off
+`define stop $stop
+`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
+// verilog_format: on
+
 module t (
   input clk
 );
@@ -39,15 +44,10 @@ module t (
   end
 
   // Counts read in final (Postponed) to avoid same-timestep races.
-  // Concrete Verilator counts; cross-checked equal in Questa 2022.3
-  // on the self-clocked equivalent (same CRC stimulus).
-  // Questa: fails_single=17 fails_multi=17
+  // Concrete Verilator counts; Questa: fails_single=17 fails_multi=17
   final begin
-    if (fails_single == 17 && fails_multi == 17) begin
-      $write("*-* All Finished *-*\n");
-    end else begin
-      $write("FAILED fails_single=%0d fails_multi=%0d\n", fails_single, fails_multi);
-      $stop;
-    end
+    `checkd(fails_single, 17);
+    `checkd(fails_multi, 17);
+    $write("*-* All Finished *-*\n");
   end
 endmodule
diff --git a/test_regress/t/t_debug_emitv.out b/test_regress/t/t_debug_emitv.out
index b65ab991e..11c0c85e3 100644
--- a/test_regress/t/t_debug_emitv.out
+++ b/test_regress/t/t_debug_emitv.out
@@ -364,6 +364,16 @@ module Vt_debug_emitv_t;
             release sum;
         end
     end
+    sequence s_clocked;
+    @(posedge clk) in
+    endsequence
+    begin : assert_seq_clocked
+        assert property ( s_clocked()
+        ) begin
+        end
+        else begin
+        end
+    end
     property p;
     @(posedge clk) ##1 sum[0]
     endproperty
diff --git a/test_regress/t/t_debug_emitv.v b/test_regress/t/t_debug_emitv.v
index edc1ec87b..5cc9c5153 100644
--- a/test_regress/t/t_debug_emitv.v
+++ b/test_regress/t/t_debug_emitv.v
@@ -286,6 +286,14 @@ module t (/*AUTOARG*/
     release sum;
   end
 
+  // verilog_format: off  // verible does not support clocking events inside sequence declarations
+  sequence s_clocked;
+    @(posedge clk) in
+  endsequence
+  // verilog_format: on
+
+  assert_seq_clocked: assert property (s_clocked);
+
   property p;
     @(posedge clk) ##1 sum[0]
   endproperty