diff --git a/src/V3AstAttr.h b/src/V3AstAttr.h
index 6a81c993c..5105fe73a 100644
--- a/src/V3AstAttr.h
+++ b/src/V3AstAttr.h
@@ -1139,6 +1139,16 @@ public:
     bool isWritable() const VL_MT_SAFE { return m_e == OUTPUT || m_e == INOUT || m_e == REF; }
     bool isRef() const VL_MT_SAFE { return m_e == REF; }
     bool isConstRef() const VL_MT_SAFE { return m_e == CONSTREF; }
+    string traceSigDirection() const {
+        if (isInout()) {
+            return "VerilatedTraceSigDirection::INOUT";
+        } else if (isWritable()) {
+            return "VerilatedTraceSigDirection::OUTPUT";
+        } else if (isNonOutput()) {
+            return "VerilatedTraceSigDirection::INPUT";
+        }
+        return "VerilatedTraceSigDirection::NONE";
+    }
 };
 constexpr bool operator==(const VDirection& lhs, const VDirection& rhs) VL_MT_SAFE {
     return lhs.m_e == rhs.m_e;
@@ -1798,6 +1808,10 @@ public:
         static const char* const names[] = {"CONSTANT", "FULL", "CHANGE"};
         return names[m_e];
     }
+    const char* func_prefix() const {
+        static const char* const names[] = {"trace_const", "trace_full", "trace_chg"};
+        return names[m_e];
+    }
 };
 constexpr bool operator==(const VTraceType& lhs, const VTraceType& rhs) {
     return lhs.m_e == rhs.m_e;
diff --git a/src/V3AstNodeExpr.h b/src/V3AstNodeExpr.h
index 886fa4d7a..c821a179d 100644
--- a/src/V3AstNodeExpr.h
+++ b/src/V3AstNodeExpr.h
@@ -4679,6 +4679,7 @@ public:
     string selfPointerProtect(bool useSelfForThis) const {
         return selfPointer().protect(useSelfForThis, protect());
     }
+    bool maybePointedTo() const override VL_MT_SAFE { return true; }
 };
 class AstCMethodCall final : public AstNodeCCall {
     // C++ method call
diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h
index 4ca004b11..1972577f0 100644
--- a/src/V3AstNodeOther.h
+++ b/src/V3AstNodeOther.h
@@ -2089,6 +2089,12 @@ public:
     }
     VDirection direction() const VL_MT_SAFE { return m_direction; }
     bool isIO() const VL_MT_SAFE { return m_direction != VDirection::NONE; }
+    bool isVLIO() const {
+        const AstBasicDType* const bdtypep = basicp();
+        return isPrimaryIO() && bdtypep && !bdtypep->isOpaque()
+               && !dtypep()->skipRefp()->isCompound()
+               && !VN_IS(dtypep()->skipRefp(), UnpackArrayDType);
+    }
     void declDirection(const VDirection& flag) { m_declDirection = flag; }
     VDirection declDirection() const { return m_declDirection; }
     void varType(VVarType type) { m_varType = type; }
@@ -2107,7 +2113,7 @@ public:
     string dpiTmpVarType(const string& varName) const;
     // Return Verilator internal type for argument: CData, SData, IData, WData
     string vlArgType(bool named, bool forReturn, bool forFunc, const string& namespc = "",
-                     bool asRef = false) const;
+                     bool asRef = false, bool constRef = false) const;
     string vlEnumType() const;  // Return VerilatorVarType: VLVT_UINT32, etc
     string vlEnumDir() const;  // Return VerilatorVarDir: VLVD_INOUT, etc
     string vlPropDecl(const string& propName) const;  // Return VerilatorVarProps declaration
diff --git a/src/V3AstNodeStmt.h b/src/V3AstNodeStmt.h
index 05a419f5f..b81cebb3c 100644
--- a/src/V3AstNodeStmt.h
+++ b/src/V3AstNodeStmt.h
@@ -1267,6 +1267,9 @@ class AstTraceDecl final : public AstNodeStmt {
     // Parents:  {statement list}
     // Expression being traced - Moved to AstTraceInc by V3Trace
     // @astgen op1 := valuep : Optional[AstNodeExpr]
+    //
+    // @astgen ptr := m_dtypeCallp: Optional[AstCCall] // Type init function call
+    // @astgen ptr := m_dtypeDeclp: Optional[AstTraceDecl] // CCall TraceDecl which replaces this
     uint32_t m_code{std::numeric_limits<uint32_t>::max()};  // Trace identifier code
     uint32_t m_fidx{0};  // Trace function index
     const string m_showname;  // Name of variable
@@ -1274,18 +1277,23 @@ class AstTraceDecl final : public AstNodeStmt {
     const VNumRange m_arrayRange;  // Property of var the trace details
     const VVarType m_varType;  // Type of variable (for localparam vs. param)
     const VDirection m_declDirection;  // Declared direction input/output etc
+    const bool m_inDtypeFunc;  // Trace decl inside type init function
+    int m_codeInc{0};  // Code increment for type
 public:
     AstTraceDecl(FileLine* fl, const string& showname,
                  AstVar* varp,  // For input/output state etc
-                 AstNodeExpr* valuep, const VNumRange& bitRange, const VNumRange& arrayRange)
+                 AstNodeExpr* valuep, const VNumRange& bitRange, const VNumRange& arrayRange,
+                 AstCCall* const dtypeCallp, const bool inDtypeFunc)
         : ASTGEN_SUPER_TraceDecl(fl)
         , m_showname{showname}
         , m_bitRange{bitRange}
         , m_arrayRange{arrayRange}
         , m_varType{varp->varType()}
-        , m_declDirection{varp->declDirection()} {
+        , m_declDirection{varp->declDirection()}
+        , m_inDtypeFunc{inDtypeFunc} {
         dtypeFrom(valuep);
         this->valuep(valuep);
+        this->dtypeCallp(dtypeCallp);
     }
     void dump(std::ostream& str) const override;
     void dumpJson(std::ostream& str) const override;
@@ -1294,7 +1302,7 @@ public:
     string name() const override VL_MT_STABLE { return m_showname; }
     bool maybePointedTo() const override VL_MT_SAFE { return true; }
     bool hasDType() const override VL_MT_SAFE { return true; }
-    bool sameNode(const AstNode* samep) const override { return false; }
+    bool sameNode(const AstNode* samep) const override { return true; }
     string showname() const { return m_showname; }  // * = Var name
     // Details on what we're tracing
     uint32_t code() const { return m_code; }
@@ -1302,7 +1310,9 @@ public:
     bool codeAssigned() const { return m_code != std::numeric_limits<uint32_t>::max(); }
     uint32_t fidx() const { return m_fidx; }
     void fidx(uint32_t fidx) { m_fidx = fidx; }
+    void codeInc(uint32_t codeInc) { m_codeInc = codeInc; }
     uint32_t codeInc() const {
+        if (m_codeInc) { return m_codeInc; }
         return (m_arrayRange.ranged() ? m_arrayRange.elements() : 1)
                * valuep()->dtypep()->widthWords()
                * (VL_EDATASIZE / 32);  // A code is always 32-bits
@@ -1311,6 +1321,11 @@ public:
     const VNumRange& arrayRange() const { return m_arrayRange; }
     VVarType varType() const { return m_varType; }
     VDirection declDirection() const { return m_declDirection; }
+    AstCCall* dtypeCallp() const { return m_dtypeCallp; }
+    void dtypeCallp(AstCCall* const callp) { m_dtypeCallp = callp; }
+    AstTraceDecl* dtypeDeclp() const { return m_dtypeDeclp; }
+    void dtypeDeclp(AstTraceDecl* const declp) { m_dtypeDeclp = declp; }
+    bool inDtypeFunc() const { return m_inDtypeFunc; }
 };
 class AstTraceInc final : public AstNodeStmt {
     // Trace point dump
@@ -1359,20 +1374,23 @@ class AstTracePushPrefix final : public AstNodeStmt {
     const VTracePrefixType m_prefixType;  // Type of prefix being pushed
     const int m_left;  // Array left index, or struct/union member count
     const int m_right;  // Array right index
+    const bool m_quotedPrefix;  // Quote prefix name
 public:
     AstTracePushPrefix(FileLine* fl, const string& prefix, VTracePrefixType prefixType,
-                       int left = 0, int right = 0)
+                       int left = 0, int right = 0, bool quotedPrefix = true)
         : ASTGEN_SUPER_TracePushPrefix(fl)
         , m_prefix{prefix}
         , m_prefixType{prefixType}
         , m_left{left}
-        , m_right{right} {}
+        , m_right{right}
+        , m_quotedPrefix{quotedPrefix} {}
     ASTGEN_MEMBERS_AstTracePushPrefix;
     bool sameNode(const AstNode* samep) const override { return false; }
     string prefix() const { return m_prefix; }
     VTracePrefixType prefixType() const { return m_prefixType; }
     int left() const { return m_left; }
     int right() const { return m_right; }
+    bool quotedPrefix() const { return m_quotedPrefix; }
 };
 class AstWait final : public AstNodeStmt {
     // @astgen op1 := condp : AstNodeExpr
diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp
index 9d93cfd4d..90fd147d3 100644
--- a/src/V3AstNodes.cpp
+++ b/src/V3AstNodes.cpp
@@ -622,7 +622,7 @@ string AstVar::verilogKwd() const {
 }
 
 string AstVar::vlArgType(bool named, bool forReturn, bool forFunc, const string& namespc,
-                         bool asRef) const {
+                         bool asRef, bool constRef) const {
     UASSERT_OBJ(!forReturn, this,
                 "Internal data is never passed as return, but as first argument");
     string ostatic;
@@ -630,7 +630,7 @@ string AstVar::vlArgType(bool named, bool forReturn, bool forFunc, const string&
 
     asRef = asRef || isDpiOpenArray() || (forFunc && (isWritable() || isRef() || isConstRef()));
 
-    if (forFunc && isReadOnly() && asRef) ostatic = ostatic + "const ";
+    if (forFunc && (isReadOnly() || constRef) && asRef) ostatic = ostatic + "const ";
 
     string oname;
     if (named) {
@@ -3317,7 +3317,8 @@ void AstStop::dumpJson(std::ostream& str) const {
 }
 void AstTraceDecl::dump(std::ostream& str) const {
     this->AstNodeStmt::dump(str);
-    if (code()) str << " [code=" << code() << "]";
+    if (codeAssigned()) str << " [code=" << code() << "]";
+    if (dtypeCallp()) str << " [dtypeCallp=" << dtypeCallp() << "]";
 }
 void AstTraceDecl::dumpJson(std::ostream& str) const {
     dumpJsonNumFunc(str, code);
diff --git a/src/V3EmitCBase.cpp b/src/V3EmitCBase.cpp
index 71e92bc16..45dfc13fb 100644
--- a/src/V3EmitCBase.cpp
+++ b/src/V3EmitCBase.cpp
@@ -207,9 +207,7 @@ void EmitCBaseVisitorConst::emitVarDecl(const AstVar* nodep, bool asRef) {
         if (asRef && refNeedParens) puts(")");
         emitDeclArrayBrackets(nodep);
         puts(";\n");
-    } else if (nodep->isPrimaryIO() && basicp && !basicp->isOpaque()
-               && !nodep->dtypep()->skipRefp()->isCompound()
-               && !VN_IS(nodep->dtypep()->skipRefp(), UnpackArrayDType)) {
+    } else if (nodep->isVLIO()) {
         if (nodep->isInout()) {
             putns(nodep, "VL_INOUT");
         } else if (nodep->isWritable()) {
diff --git a/src/V3EmitCImp.cpp b/src/V3EmitCImp.cpp
index 0649fb888..eebca7f66 100644
--- a/src/V3EmitCImp.cpp
+++ b/src/V3EmitCImp.cpp
@@ -627,6 +627,16 @@ class EmitCTrace final : public EmitCFunc {
     }
 
     void emitTraceInitOne(const AstTraceDecl* nodep, int enumNum) {
+        std::string direction;
+        direction = nodep->declDirection().traceSigDirection();
+
+        AstCCall* const callp = nodep->dtypeCallp();
+        if (callp) {
+            callp->argTypes(callp->argTypes() + ", " + cvtToStr(nodep->fidx()) + ", c+"
+                            + cvtToStr(nodep->code()) + ", " + direction);
+            return;
+        }
+
         if (nodep->dtypep()->basicp()->isDouble()) {
             puts("VL_TRACE_DECL_DOUBLE");
         } else if (nodep->isWide()) {
@@ -653,7 +663,11 @@ class EmitCTrace final : public EmitCFunc {
 
         // Function index
         puts(",");
-        puts(cvtToStr(nodep->fidx()));
+        if (nodep->inDtypeFunc()) {
+            puts("fidx");
+        } else {
+            puts(cvtToStr(nodep->fidx()));
+        }
 
         // Name
         puts(",");
@@ -663,14 +677,10 @@ class EmitCTrace final : public EmitCFunc {
         puts("," + cvtToStr(enumNum));
 
         // Direction
-        if (nodep->declDirection().isInout()) {
-            puts(", VerilatedTraceSigDirection::INOUT");
-        } else if (nodep->declDirection().isWritable()) {
-            puts(", VerilatedTraceSigDirection::OUTPUT");
-        } else if (nodep->declDirection().isNonOutput()) {
-            puts(", VerilatedTraceSigDirection::INPUT");
+        if (nodep->inDtypeFunc()) {
+            puts(", direction");
         } else {
-            puts(", VerilatedTraceSigDirection::NONE");
+            puts(", " + direction);
         }
 
         // Kind
@@ -767,16 +777,7 @@ class EmitCTrace final : public EmitCFunc {
                 puts("VL_SC_BV_DATAP(");
             }
             iterateConst(varrefp);  // Put var name out
-            // Tracing only supports 1D arrays
-            if (nodep->declp()->arrayRange().ranged()) {
-                if (arrayindex == -2) {
-                    puts("[i]");
-                } else if (arrayindex == -1) {
-                    puts("[0]");
-                } else {
-                    puts("[" + cvtToStr(arrayindex) + "]");
-                }
-            }
+            emitTraceIndex(nodep, arrayindex);
             if (varp->isSc()) puts(".read()");
             if (emitTraceIsScUint(nodep)) {
                 puts(nodep->isQuad() ? ".to_uint64()" : ".to_uint()");
@@ -789,10 +790,24 @@ class EmitCTrace final : public EmitCFunc {
         } else {
             puts("(");
             iterateConst(nodep->valuep());
+            emitTraceIndex(nodep, arrayindex);
             puts(")");
         }
     }
 
+    void emitTraceIndex(const AstTraceInc* const nodep, int arrayindex) {
+        // Tracing only supports 1D arrays
+        if (nodep->declp()->arrayRange().ranged()) {
+            if (arrayindex == -2) {
+                puts("[i]");
+            } else if (arrayindex == -1) {
+                puts("[0]");
+            } else {
+                puts("[" + cvtToStr(arrayindex) + "]");
+            }
+        }
+    }
+
     // VISITORS
     using EmitCFunc::visit;  // Suppress hidden overloaded virtual function warning
     void visit(AstCFunc* nodep) override {
@@ -812,7 +827,11 @@ class EmitCTrace final : public EmitCFunc {
     }
     void visit(AstTracePushPrefix* nodep) override {
         putns(nodep, "VL_TRACE_PUSH_PREFIX(tracep, ");
-        putsQuoted(VIdProtect::protectWordsIf(nodep->prefix(), nodep->protect()));
+        if (nodep->quotedPrefix()) {
+            putsQuoted(VIdProtect::protectWordsIf(nodep->prefix(), nodep->protect()));
+        } else {
+            puts(nodep->prefix());
+        }
         puts(", VerilatedTracePrefixType::");
         puts(nodep->prefixType().ascii());
         puts(", " + std::to_string(nodep->left()));
diff --git a/src/V3Gate.cpp b/src/V3Gate.cpp
index 6d3c1f9b2..ca15a0bb6 100644
--- a/src/V3Gate.cpp
+++ b/src/V3Gate.cpp
@@ -429,11 +429,11 @@ class GateOkVisitor final : public VNVisitorConst {
 
         // We only allow a LHS ref for the var being set, and a RHS ref for
         // something else being read.
+        AstVarScope* const vscp = nodep->varScopep();
         if (nodep->access().isWriteOnly()) {
             if (m_lhsVarRef) clearSimple(">1 write refs");
             m_lhsVarRef = nodep;
         } else {
-            AstVarScope* const vscp = nodep->varScopep();
             // TODO: possible bug, should it be >= 1 as add is below?
             if (m_readVscps.size() > 1) {
                 if (m_buffersOnly) clearSimple(">1 rhs varRefs");
diff --git a/src/V3Trace.cpp b/src/V3Trace.cpp
index 959b9ef77..b4eb06234 100644
--- a/src/V3Trace.cpp
+++ b/src/V3Trace.cpp
@@ -39,13 +39,16 @@
 
 #include "V3Trace.h"
 
+#include "V3Ast.h"
 #include "V3DupFinder.h"
 #include "V3EmitCBase.h"
 #include "V3Graph.h"
 #include "V3Stats.h"
+#include "V3UniqueNames.h"
 
 #include <limits>
 #include <set>
+#include <unordered_map>
 
 VL_DEFINE_DEBUG_FUNCTIONS;
 
@@ -118,6 +121,8 @@ class TraceTraceVertex final : public V3GraphVertex {
     AstTraceDecl* const m_nodep;  // TRACEINC this represents
     // nullptr, or other vertex with the real code() that duplicates this one
     TraceTraceVertex* m_duplicatep = nullptr;
+    // When aliasing to a dtype parent, offset of the member within the dtype
+    uint32_t m_dtypeAliasOffset = 0;
 
 public:
     TraceTraceVertex(V3Graph* graphp, AstTraceDecl* nodep)
@@ -134,6 +139,9 @@ public:
         UASSERT_OBJ(!duplicatep(), nodep(), "Assigning duplicatep() to already duplicated node");
         m_duplicatep = dupp;
     }
+    void redirectDuplicatep(TraceTraceVertex* dupp) { m_duplicatep = dupp; }
+    uint32_t dtypeAliasOffset() const { return m_dtypeAliasOffset; }
+    void dtypeAliasOffset(uint32_t offset) { m_dtypeAliasOffset = offset; }
 };
 
 class TraceVarVertex final : public V3GraphVertex {
@@ -161,9 +169,12 @@ class TraceVisitor final : public VNVisitor {
     //  Ast*::user4()                   // V3Hasher calculation
     // Cleared entire netlist
     //  AstCFunc::user1()               // V3GraphVertex* for this node
+    //  AstCFunc::user2()               // bool; func contains trace decls (needs splitting)
     //  AstTraceDecl::user1()           // V3GraphVertex* for this node
+    //  AstTraceDecl::user2()           // dtype decl cannot be used for _chg
     //  AstVarScope::user1()            // V3GraphVertex* for this node
     //  AstStmtExpr::user2()            // bool; walked next list for other ccalls
+    //  AstVarRef::user2()              // dtype V3TraceDecl* for this node
     //  Ast*::user3()                   // TraceActivityVertex* for this node
     const VNUser1InUse m_inuser1;
     const VNUser2InUse m_inuser2;
@@ -183,6 +194,15 @@ class TraceVisitor final : public VNVisitor {
     V3Graph m_graph;  // Var/CFunc tracking
     TraceActivityVertex* const m_alwaysVtxp;  // "Always trace" vertex
     bool m_finding = false;  // Pass one of algorithm?
+    struct DtypeFuncs final {
+    public:
+        AstCFunc* fullFuncp = nullptr;
+        AstCFunc* chgFuncp = nullptr;
+    };
+    std::unordered_map<const AstNodeDType*, DtypeFuncs>
+        m_dtypeNonConstFuncs;  // Full / Chg funcs per type
+    std::unordered_map<const AstNodeDType*, AstCFunc*> m_dtypeConstFuncs;  // Const func per type
+    V3UniqueNames m_dtypeNames{""};  // Unique type func names
 
     // Trace parallelism. Only VCD tracing can be parallelized at this time.
     const uint32_t m_parallelism
@@ -203,31 +223,165 @@ class TraceVisitor final : public VNVisitor {
         UINFO(9, "Finding duplicates");
         // Note uses user4
         V3DupFinder dupFinder;  // Duplicate code detection
+
+        // Compute member offsets within dtype instances incrementally.
+        // For each dtype member TraceDecl, stores its code offset within the
+        // dtype parent's code range.
+        std::unordered_map<const AstTraceDecl*, uint32_t> memberOffsets;
+        std::unordered_map<const AstTraceDecl*, uint32_t> runningOffset;
+
+        // For fixup pass: track dups redirected to dtype parents, so we can
+        // fix them if the parent's user2 is later set during the loop.
+        // Maps dup vertex -> original canonical member vertex.
+        std::vector<std::pair<TraceTraceVertex*, TraceTraceVertex*>> dtypeParentRedirects;
+
         // Hash all of the traced values and find if there are any duplicates
         for (V3GraphVertex& vtx : m_graph.vertices()) {
             if (TraceTraceVertex* const vvertexp = vtx.cast<TraceTraceVertex>()) {
-                const AstTraceDecl* const nodep = vvertexp->nodep();
+                AstTraceDecl* const nodep = vvertexp->nodep();
+                if (nodep->dtypeCallp()) continue;
+
+                if (nodep->dtypeDeclp()) {
+                    uint32_t& offset = runningOffset[nodep->dtypeDeclp()];
+                    memberOffsets[nodep] = offset;
+                    offset += nodep->codeInc();
+                }
+
                 UASSERT_OBJ(!vvertexp->duplicatep(), nodep, "Should not be a duplicate");
-                const auto dupit = dupFinder.findDuplicate(nodep->valuep());
+                const auto dupit = dupFinder.findDuplicate(nodep);
                 if (dupit == dupFinder.end()) {
-                    dupFinder.insert(nodep->valuep());
+                    dupFinder.insert(nodep);
                 } else {
-                    const AstTraceDecl* const dupDeclp = VN_AS(dupit->second->backp(), TraceDecl);
+                    AstTraceDecl* const dupDeclp = VN_AS(dupit->second, TraceDecl);
                     UASSERT_OBJ(dupDeclp, nodep, "Trace duplicate of wrong type");
                     TraceTraceVertex* const dupvertexp
                         = dupDeclp->user1u().toGraphVertex()->cast<TraceTraceVertex>();
-                    UINFO(8, "  Orig " << nodep);
-                    UINFO(8, "   dup " << dupDeclp);
-                    // Mark the hashed node as the original and our
-                    // iterating node as duplicated
-                    vvertexp->duplicatep(dupvertexp);
+                    UINFO(8, "  Orig " << dupDeclp << endl);
+                    UINFO(8, "   dup " << nodep << endl);
+
+                    if (dupDeclp->dtypeDeclp() && !dupDeclp->dtypeDeclp()->user2()) {
+                        AstTraceDecl* const dtypeParentp = dupDeclp->dtypeDeclp();
+                        TraceTraceVertex* const dtypeVtxp
+                            = dtypeParentp->user1u().toGraphVertex()->cast<TraceTraceVertex>();
+                        const auto it2 = memberOffsets.find(dupDeclp);
+                        UASSERT_OBJ(it2 != memberOffsets.end(), dupDeclp,
+                                    "Member offset not precomputed");
+                        vvertexp->duplicatep(dtypeVtxp);
+                        vvertexp->dtypeAliasOffset(it2->second);
+                        dtypeParentRedirects.emplace_back(vvertexp, dupvertexp);
+                    } else {
+                        vvertexp->duplicatep(dupvertexp);
+                    }
+                    if (nodep->dtypeDeclp()) nodep->dtypeDeclp()->user2(true);
                 }
             }
         }
+
+        for (const auto& pair : dtypeParentRedirects) {
+            TraceTraceVertex* const dupVtxp = pair.first;
+            TraceTraceVertex* const memberVtxp = pair.second;
+            const AstTraceDecl* const parentDeclp = dupVtxp->duplicatep()->nodep();
+            if (parentDeclp->user2()) {
+                dupVtxp->redirectDuplicatep(memberVtxp);
+                dupVtxp->dtypeAliasOffset(0);
+            }
+        }
+
         if (dumpLevel() || debug() >= 9)
             dupFinder.dumpFile(v3Global.debugFilename("trace") + ".hash", false);
     }
 
+    void graphDtypePrune() {
+        for (V3GraphVertex* const vtxp : m_graph.vertices().unlinkable()) {
+            if (TraceTraceVertex* const vvertexp = vtxp->cast<TraceTraceVertex>()) {
+                AstTraceDecl* const declp = vvertexp->nodep();
+                // This skips the dtype sub-func optimization if a var is affected by multiple
+                // activities.  We really only need to do this for _chg funcs (and not decls,
+                // _const and _full) but it's simpiler to do it all one way or the other.
+                if (declp) {
+                    if (declp->user2() || (declp->dtypeDeclp() && !declp->dtypeDeclp()->user2())) {
+                        AstCCall* const callp = declp->dtypeCallp();
+                        if (callp) {
+                            AstNode* stmtexprp = callp->backp();
+                            VL_DO_DANGLING(pushDeletep(stmtexprp->unlinkFrBack()), stmtexprp);
+                        } else {
+                            bool emptyScope;
+                            do {
+                                emptyScope = false;
+                                AstNode* const declBackp = declp->backp();
+                                AstNode* const declNextp = declp->nextp();
+                                if (VN_IS(declBackp, TracePushPrefix)
+                                    && VN_IS(declNextp, TracePopPrefix)) {
+                                    VL_DO_DANGLING(pushDeletep(declBackp->unlinkFrBack()),
+                                                   declBackp);
+                                    VL_DO_DANGLING(pushDeletep(declNextp->unlinkFrBack()),
+                                                   declNextp);
+                                    emptyScope = true;
+                                }
+                            } while (emptyScope);
+                        }
+                        // Can't purge until we finish this pass
+                        pushDeletep(declp->unlinkFrBack());
+                        vvertexp->rerouteEdges(&m_graph);
+                        vvertexp->unlinkDelete(&m_graph);
+                    }
+                    declp->dtypeDeclp(nullptr);
+                }
+            }
+        }
+    }
+
+    void splitTraceDeclFuncs() {
+        const int splitLimit = v3Global.opt.outputSplitCTrace() ? v3Global.opt.outputSplitCTrace()
+                                                                : std::numeric_limits<int>::max();
+        if (splitLimit == std::numeric_limits<int>::max()) return;
+
+        for (AstNode* nodep = m_topScopep->blocksp(); nodep; nodep = nodep->nextp()) {
+            AstCFunc* const funcp = VN_CAST(nodep, CFunc);
+            if (!funcp || !funcp->user2()) continue;
+
+            const string baseName = funcp->name();
+            uint32_t subNum = 1;
+            int curSize = 0;
+            AstCFunc* curFuncp = funcp;
+            std::vector<AstNodeStmt*> callStmts;
+
+            auto startNewSubFunc = [&]() {
+                FileLine* const flp = funcp->fileline();
+                const string newName = baseName + "_" + cvtToStr(subNum++);
+                AstCFunc* const newFuncp = new AstCFunc{flp, newName, m_topScopep};
+                newFuncp->argTypes(v3Global.opt.traceClassBase() + "* tracep");
+                newFuncp->isTrace(true);
+                newFuncp->isStatic(false);
+                newFuncp->isLoose(true);
+                newFuncp->slow(true);
+                newFuncp->dontCombine(true);
+                m_topScopep->addBlocksp(newFuncp);
+                newFuncp->addStmtsp(new AstCStmt{flp, "const int c = vlSymsp->__Vm_baseCode;"});
+                AstCCall* const callp = new AstCCall{flp, newFuncp};
+                callp->dtypeSetVoid();
+                callp->argTypes("tracep");
+                callStmts.push_back(callp->makeStmt());
+                curFuncp = newFuncp;
+                curSize = 0;
+            };
+
+            for (AstNode *stmtp = funcp->stmtsp(), *nextp; stmtp; stmtp = nextp) {
+                nextp = stmtp->nextp();
+                curSize += stmtp->nodeCount();
+
+                if (curFuncp != funcp) {
+                    stmtp->unlinkFrBack();
+                    curFuncp->addStmtsp(stmtp);
+                }
+
+                if (curSize > splitLimit && nextp) startNewSubFunc();
+            }
+
+            for (AstNodeStmt* const callStmtp : callStmts) { funcp->addStmtsp(callStmtp); }
+        }
+    }
+
     void graphSimplify(bool initial) {
         if (initial) {
             // Remove all variable nodes
@@ -481,24 +635,26 @@ class TraceVisitor final : public VNVisitor {
     }
 
     AstCFunc* newCFunc(VTraceType traceType, AstCFunc* topFuncp, uint32_t funcNum,
-                       uint32_t baseCode = 0) {
+                       uint32_t baseCode = 0, const AstTraceDecl* const declp = nullptr,
+                       bool declSub = false) {
         // Create new function
-        const bool isTopFunc = topFuncp == nullptr;
+        const bool isTopFunc = !declp && topFuncp == nullptr;
         std::string funcName;
-        if (isTopFunc) {
-            if (traceType == VTraceType::CONSTANT) {
-                funcName = "trace_const";
-            } else if (traceType == VTraceType::FULL) {
-                funcName = "trace_full";
-            } else {
-                funcName = "trace_chg";
-            }
+        if (isTopFunc || declp) {
+            funcName = traceType.func_prefix();
         } else {
             funcName = topFuncp->name();
             funcName += "_sub";
         }
-        funcName += "_";
-        funcName += cvtToStr(funcNum);
+        if (declp) {
+            funcName += "_dtype";
+            if (declSub) funcName += "_sub";
+            funcName += "__";
+            funcName = m_dtypeNames.get(funcName);
+        } else {
+            funcName += "_";
+            funcName += cvtToStr(funcNum);
+        }
 
         FileLine* const flp = m_topScopep->fileline();
         AstCFunc* const funcp = new AstCFunc{flp, funcName, m_topScopep};
@@ -511,7 +667,10 @@ class TraceVisitor final : public VNVisitor {
         m_topScopep->addBlocksp(funcp);
         const std::string bufArg
             = v3Global.opt.traceClassBase()
-              + "::" + (v3Global.opt.useTraceOffload() ? "OffloadBuffer" : "Buffer") + "* bufp";
+              + "::" + (v3Global.opt.useTraceOffload() ? "OffloadBuffer" : "Buffer") + "* bufp"
+              + (declp ? (", uint32_t offset, const " + declp->dtypep()->cType("", true, true)
+                          + " __VdtypeVar")
+                       : "");
         if (isTopFunc) {
             // Top functions
             funcp->argTypes("void* voidSelf, " + bufArg);
@@ -546,35 +705,82 @@ class TraceVisitor final : public VNVisitor {
             if (traceType != VTraceType::CHANGE) {
                 // Full dump sub function
                 funcp->addStmtsp(new AstCStmt{flp,  //
-                                              "uint32_t* const oldp VL_ATTR_UNUSED = "
-                                              "bufp->oldp(vlSymsp->__Vm_baseCode);\n"});
+                                              string("uint32_t* const oldp VL_ATTR_UNUSED = "
+                                                     "bufp->oldp(vlSymsp->__Vm_baseCode")
+                                                  + (declp ? " + offset" : "") + ");\n"});
             } else {
                 // Change dump sub function
                 if (v3Global.opt.useTraceOffload()) {
                     funcp->addStmtsp(new AstCStmt{flp,  //
                                                   "const uint32_t base VL_ATTR_UNUSED = "
                                                   "vlSymsp->__Vm_baseCode + "
-                                                      + cvtToStr(baseCode) + ";\n"});
+                                                      + (declp ? " offset" : cvtToStr(baseCode))
+                                                      + ";\n"});
                     funcp->addStmtsp(
                         new AstCStmt{flp, "(void)bufp;  // Prevent unused variable warning\n"});
                 } else {
                     funcp->addStmtsp(new AstCStmt{flp,  //
                                                   "uint32_t* const oldp VL_ATTR_UNUSED = "
                                                   "bufp->oldp(vlSymsp->__Vm_baseCode + "
-                                                      + cvtToStr(baseCode) + ");\n"});
+                                                      + (declp ? " offset" : cvtToStr(baseCode))
+                                                      + ");\n"});
                 }
             }
-            // Add call to top function
-            AstCCall* const callp = new AstCCall{funcp->fileline(), funcp};
-            callp->dtypeSetVoid();
-            callp->argTypes("bufp");
-            topFuncp->addStmtsp(callp->makeStmt());
+            if (!declp) {
+                // Add call to top function
+                AstCCall* const callp = new AstCCall{funcp->fileline(), funcp};
+                callp->dtypeSetVoid();
+                callp->argTypes("bufp");
+                topFuncp->addStmtsp(callp->makeStmt());
+            }
         }
         // Done
         UINFO(5, "  newCFunc " << funcp);
         return funcp;
     }
 
+    AstCFunc* newCDtypeSubFunc(VTraceType traceType, const AstTraceDecl* const declp,
+                               AstCFunc* parentp) {
+        AstCFunc* const funcp = newCFunc(traceType, nullptr, 0, 0, declp, true);
+        FileLine* const flp = m_topScopep->fileline();
+        AstCCall* const callp = new AstCCall{flp, funcp};
+        callp->dtypeSetVoid();
+        callp->argTypes("bufp, offset, __VdtypeVar");
+        parentp->addStmtsp(callp->makeStmt());
+        return funcp;
+    }
+
+    AstCFunc* createConstDtypeTraceFunctions(const AstTraceDecl* declp) {
+        const AstNodeDType* const dtypep = declp->dtypep()->skipRefp();
+        auto pair = m_dtypeConstFuncs.emplace(dtypep, nullptr);
+        if (pair.second) {
+            FileLine* const flp = declp->fileline();
+            AstCFunc* const funcp = newCFunc(VTraceType::CONSTANT, nullptr, 0, 0, declp);
+
+            bool first = true;
+            for (AstNode* callStmtp = declp->dtypeCallp()->funcp()->stmtsp(); callStmtp;
+                 callStmtp = callStmtp->nextp()) {
+                const AstCCall* const callp
+                    = VN_CAST(VN_CAST(callStmtp, StmtExpr)->exprp(), CCall);
+                bool onlyOne = first && !callStmtp->nextp();
+                AstCFunc* const subFuncp
+                    = onlyOne ? funcp : newCDtypeSubFunc(VTraceType::CONSTANT, declp, funcp);
+                for (AstNode* stmtp = callp->funcp()->stmtsp(); stmtp; stmtp = stmtp->nextp()) {
+                    if (AstTraceDecl* const fieldDeclp = VN_CAST(stmtp, TraceDecl)) {
+                        AstTraceInc* const incp
+                            = new AstTraceInc{flp, fieldDeclp, VTraceType::CONSTANT};
+                        subFuncp->addStmtsp(incp);
+                    }
+                }
+                first = false;
+            }
+
+            pair.first->second = funcp;
+        }
+
+        return pair.first->second;
+    }
+
     void createConstTraceFunctions(const TraceVec& traces) {
         const int splitLimit = v3Global.opt.outputSplitCTrace() ? v3Global.opt.outputSplitCTrace()
                                                                 : std::numeric_limits<int>::max();
@@ -583,18 +789,12 @@ class TraceVisitor final : public VNVisitor {
         uint32_t subFuncNum = 0;
         AstCFunc* subFuncp = nullptr;
         int subStmts = 0;
+        std::vector<const TraceTraceVertex*> duplicates;
         for (auto it = traces.cbegin(); it != traces.end(); ++it) {
             const TraceTraceVertex* const vtxp = it->second;
             AstTraceDecl* const declp = vtxp->nodep();
-            if (const TraceTraceVertex* const canonVtxp = vtxp->duplicatep()) {
-                // This is a duplicate trace node. We will assign the signal
-                // number to the canonical node, and emit this as an alias, so
-                // no need to create a TraceInc node.
-                const AstTraceDecl* const canonDeclp = canonVtxp->nodep();
-                UASSERT_OBJ(!canonVtxp->duplicatep(), canonDeclp, "Canonical node is a duplicate");
-                UASSERT_OBJ(canonDeclp->codeAssigned(), canonDeclp,
-                            "Canonical node should have code assigned already");
-                declp->code(canonDeclp->code());
+            if (vtxp->duplicatep()) {
+                duplicates.push_back(vtxp);
                 continue;
             }
 
@@ -616,11 +816,71 @@ class TraceVisitor final : public VNVisitor {
                     ++subFuncNum;
                 }
                 FileLine* const flp = declp->fileline();
-                AstTraceInc* const incp = new AstTraceInc{flp, declp, VTraceType::CONSTANT};
-                subFuncp->addStmtsp(incp);
-                subStmts += incp->nodeCount();
+                if (declp->dtypeCallp()) {
+                    AstCFunc* const funcp = createConstDtypeTraceFunctions(declp);
+                    AstNodeExpr* argsp = nullptr;
+                    argsp = AstNode::addNext(argsp, declp->valuep()->cloneTree(false));
+                    AstCCall* const callp = new AstCCall{flp, funcp, argsp};
+                    callp->dtypeSetVoid();
+                    callp->argTypes(callp->argTypes() + "bufp, " + std::to_string(declp->code()));
+                    subFuncp->addStmtsp(callp->makeStmt());
+
+                    subStmts += 1;
+                } else {
+                    AstTraceInc* const incp = new AstTraceInc{flp, declp, VTraceType::CONSTANT};
+                    subFuncp->addStmtsp(incp);
+                    subStmts += incp->nodeCount();
+                }
             }
         }
+
+        // Assign codes to duplicate nodes from their canonicals
+        for (const TraceTraceVertex* const vtxp : duplicates) {
+            AstTraceDecl* const declp = vtxp->nodep();
+            const TraceTraceVertex* const canonVtxp = vtxp->duplicatep();
+            const AstTraceDecl* const canonDeclp = canonVtxp->nodep();
+            UASSERT_OBJ(!canonVtxp->duplicatep(), canonDeclp, "Canonical node is a duplicate");
+            UASSERT_OBJ(canonDeclp->codeAssigned(), canonDeclp,
+                        "Canonical node should have code assigned already");
+            declp->code(canonDeclp->code() + vtxp->dtypeAliasOffset());
+        }
+    }
+
+    DtypeFuncs createNonConstDtypeTraceFunctions(const AstTraceDecl* declp) {
+        AstNodeDType* dtypep = declp->dtypep()->skipRefp();
+        auto pair = m_dtypeNonConstFuncs.emplace(dtypep, DtypeFuncs{});
+        if (pair.second) {
+            FileLine* const flp = declp->fileline();
+            AstCFunc* const fullFuncp = newCFunc(VTraceType::FULL, nullptr, 0, 0, declp);
+            AstCFunc* const chgFuncp = newCFunc(VTraceType::CHANGE, nullptr, 0, 0, declp);
+
+            bool first = true;
+            for (AstNode* callStmtp = declp->dtypeCallp()->funcp()->stmtsp(); callStmtp;
+                 callStmtp = callStmtp->nextp()) {
+                const AstCCall* const callp
+                    = VN_CAST(VN_CAST(callStmtp, StmtExpr)->exprp(), CCall);
+                bool onlyOne = first && !callStmtp->nextp();
+                AstCFunc* const fullSubFuncp
+                    = onlyOne ? fullFuncp : newCDtypeSubFunc(VTraceType::FULL, declp, fullFuncp);
+                AstCFunc* const chgSubFuncp
+                    = onlyOne ? chgFuncp : newCDtypeSubFunc(VTraceType::CHANGE, declp, chgFuncp);
+                for (AstNode* stmtp = callp->funcp()->stmtsp(); stmtp; stmtp = stmtp->nextp()) {
+                    if (AstTraceDecl* const fieldDeclp = VN_CAST(stmtp, TraceDecl)) {
+                        AstTraceInc* const incFullp
+                            = new AstTraceInc{flp, fieldDeclp, VTraceType::FULL};
+                        fullSubFuncp->addStmtsp(incFullp);
+                        AstTraceInc* const incChgp
+                            = new AstTraceInc{flp, fieldDeclp, VTraceType::CHANGE};
+                        chgSubFuncp->addStmtsp(incChgp);
+                    }
+                }
+                first = false;
+            }
+
+            pair.first->second = {.fullFuncp = fullFuncp, .chgFuncp = chgFuncp};
+        }
+
+        return pair.first->second;
     }
 
     void createNonConstTraceFunctions(const TraceVec& traces, uint32_t nAllCodes,
@@ -698,24 +958,44 @@ class TraceVisitor final : public VNVisitor {
 
                 // Add TraceInc nodes
                 FileLine* const flp = declp->fileline();
-                AstTraceInc* const incFulp = new AstTraceInc{flp, declp, VTraceType::FULL};
-                subFulFuncp->addStmtsp(incFulp);
-                AstTraceInc* const incChgp
-                    = new AstTraceInc{flp, declp, VTraceType::CHANGE, baseCode};
-                ifp->addThensp(incChgp);
+                if (declp->dtypeCallp()) {
+                    DtypeFuncs funcs = createNonConstDtypeTraceFunctions(declp);
+                    AstNodeExpr* argsp = nullptr;
+                    argsp = AstNode::addNext(argsp, declp->valuep()->cloneTree(false));
+                    AstCCall* const callFullp = new AstCCall{flp, funcs.fullFuncp, argsp};
+                    callFullp->dtypeSetVoid();
+                    callFullp->argTypes(callFullp->argTypes() + "bufp, "
+                                        + std::to_string(declp->code()));
+                    subFulFuncp->addStmtsp(callFullp->makeStmt());
+                    argsp = nullptr;
+                    argsp = AstNode::addNext(argsp, declp->valuep()->cloneTree(false));
+                    AstCCall* const callChgp = new AstCCall{flp, funcs.chgFuncp, argsp};
+                    callChgp->dtypeSetVoid();
+                    callChgp->argTypes(callChgp->argTypes() + "bufp, "
+                                       + std::to_string(declp->code()));
+                    ifp->addThensp(callChgp->makeStmt());
 
-                // Set the function index of the decl
-                declp->fidx(topFuncNum);
-
-                // Track splitting due to size
-                UASSERT_OBJ(incFulp->nodeCount() == incChgp->nodeCount(), declp,
-                            "Should have equal cost");
-                const VNumRange range = declp->arrayRange();
-                if (range.ranged()) {
-                    // 2x because each element is a TraceInc and a VarRef
-                    subStmts += range.elements() * 2;
+                    subStmts += 2;
                 } else {
-                    subStmts += incChgp->nodeCount();
+                    AstTraceInc* const incFulp = new AstTraceInc{flp, declp, VTraceType::FULL};
+                    subFulFuncp->addStmtsp(incFulp);
+                    AstTraceInc* const incChgp
+                        = new AstTraceInc{flp, declp, VTraceType::CHANGE, baseCode};
+                    ifp->addThensp(incChgp);
+
+                    // Set the function index of the decl
+                    declp->fidx(topFuncNum);
+
+                    // Track splitting due to size
+                    UASSERT_OBJ(incFulp->nodeCount() == incChgp->nodeCount(), declp,
+                                "Should have equal cost");
+                    const VNumRange range = declp->arrayRange();
+                    if (range.ranged()) {
+                        // 2x because each element is a TraceInc and a VarRef
+                        subStmts += range.elements() * 2;
+                    } else {
+                        subStmts += incChgp->nodeCount();
+                    }
                 }
 
                 // Track partitioning
@@ -761,6 +1041,9 @@ class TraceVisitor final : public VNVisitor {
     void createTraceFunctions() {
         // Detect and remove duplicate values
         detectDuplicates();
+
+        graphDtypePrune();
+        splitTraceDeclFuncs();
         m_graph.removeRedundantEdgesMax(&V3GraphEdge::followAlwaysTrue);
 
         // Simplify & optimize the graph
@@ -885,7 +1168,7 @@ class TraceVisitor final : public VNVisitor {
                 || nodep->isCoroutine()) {
                 // Cannot treat a coroutine as slow, it may be resumed later
                 const bool slow = nodep->slow() && !nodep->isCoroutine();
-                V3GraphVertex* const activityVtxp = getActivityVertexp(nodep, slow);
+                TraceActivityVertex* const activityVtxp = getActivityVertexp(nodep, slow);
                 new V3GraphEdge{&m_graph, activityVtxp, funcVtxp, 1};
             }
         }
@@ -895,21 +1178,23 @@ class TraceVisitor final : public VNVisitor {
     }
     void visit(AstTraceDecl* nodep) override {
         UINFO(8, "   TRACE " << nodep);
-        if (!m_finding) {
+        if (!m_finding && !nodep->inDtypeFunc()) {
             V3GraphVertex* const vertexp = new TraceTraceVertex{&m_graph, nodep};
             nodep->user1p(vertexp);
 
             UASSERT_OBJ(m_cfuncp, nodep, "Trace not under func");
+            m_cfuncp->user2(true);
             VL_RESTORER(m_tracep);
             m_tracep = nodep;
             iterateChildren(nodep);
         }
     }
     void visit(AstVarRef* nodep) override {
+        UASSERT_OBJ(nodep->varScopep(), nodep, "No var scope?");
+        AstVarScope* const varscopep = nodep->varScopep();
+        V3GraphVertex* varVtxp = varscopep->user1u().toGraphVertex();
         if (m_tracep) {
-            UASSERT_OBJ(nodep->varScopep(), nodep, "No var scope?");
             UASSERT_OBJ(nodep->access().isReadOnly(), nodep, "Lvalue in trace?  Should be const.");
-            V3GraphVertex* varVtxp = nodep->varScopep()->user1u().toGraphVertex();
             if (!varVtxp) {
                 varVtxp = new TraceVarVertex{&m_graph, nodep->varScopep()};
                 nodep->varScopep()->user1p(varVtxp);
@@ -920,12 +1205,23 @@ class TraceVisitor final : public VNVisitor {
                 || nodep->varp()->isSigPublic()) {  // Or ones user can change
                 new V3GraphEdge{&m_graph, m_alwaysVtxp, traceVtxp, 1};
             }
+            if (m_tracep->dtypeCallp()) varscopep->user2p(m_tracep);
         } else if (m_cfuncp && m_finding && nodep->access().isWriteOrRW()) {
-            UASSERT_OBJ(nodep->varScopep(), nodep, "No var scope?");
             V3GraphVertex* const funcVtxp = getCFuncVertexp(m_cfuncp);
-            V3GraphVertex* const varVtxp = nodep->varScopep()->user1u().toGraphVertex();
             if (varVtxp) {  // else we're not tracing this signal
                 new V3GraphEdge{&m_graph, funcVtxp, varVtxp, 1};
+                AstTraceDecl* const declp = VN_AS(varscopep->user2p(), TraceDecl);
+                if (declp) {
+                    V3GraphVertex* const cFuncVtxp = getCFuncVertexp(m_cfuncp);
+                    for (const V3GraphEdge& edge : cFuncVtxp->inEdges()) {
+                        V3GraphVertex* const activityp = edge.fromp();
+                        if (!declp->user3p()) {
+                            declp->user3p(activityp);
+                        } else if (declp->user3u().toGraphVertex() != activityp) {
+                            declp->user2(true);
+                        }
+                    }
+                }
             }
         }
     }
@@ -936,7 +1232,15 @@ public:
     // CONSTRUCTORS
     explicit TraceVisitor(AstNetlist* nodep)
         : m_alwaysVtxp{new TraceActivityVertex{&m_graph, TraceActivityVertex::ACTIVITY_ALWAYS}} {
+        nodep->user2ClearTree();  // TraceDecl multiple activities flag
+        nodep->user3ClearTree();  // TraceDecl TraceActivityVertex (assumes we start at nullptr)
         iterate(nodep);
+        nodep->foreach([](AstTraceDecl* const declp) {
+            if (declp->inDtypeFunc()) {
+                declp->valuep()->unlinkFrBack()->deleteTree();
+                declp->valuep(nullptr);
+            }
+        });
     }
     ~TraceVisitor() override {
         V3Stats::addStat("Tracing, Activity setters", m_statSetters);
diff --git a/src/V3TraceDecl.cpp b/src/V3TraceDecl.cpp
index d79ffc540..c0fd99eef 100644
--- a/src/V3TraceDecl.cpp
+++ b/src/V3TraceDecl.cpp
@@ -24,13 +24,21 @@
 
 #include "V3TraceDecl.h"
 
+#include "V3Ast.h"
 #include "V3Control.h"
 #include "V3EmitCBase.h"
+#include "V3Error.h"
+#include "V3File.h"
+#include "V3Global.h"
+#include "V3Number.h"
 #include "V3Stats.h"
+#include "V3UniqueNames.h"
 
+#include <cstdint>
 #include <functional>
 #include <limits>
 #include <tuple>
+#include <unordered_map>
 #include <vector>
 
 VL_DEFINE_DEBUG_FUNCTIONS;
@@ -94,6 +102,10 @@ public:
 // TraceDecl state, as a visitor of each AstNode
 
 class TraceDeclVisitor final : public VNVisitor {
+    // NODE STATE
+    // AstCFunc::user1()                // code offset for current type
+    // AstCFunc::user2()                // VarScope for dtype functions
+
     // STATE
     AstTopScope* const m_topScopep;  // The singleton AstTopScope
     const AstScope* m_currScopep = nullptr;  // Current scope being visited
@@ -101,6 +113,30 @@ class TraceDeclVisitor final : public VNVisitor {
     std::vector<AstCFunc*> m_topFuncps;  // Top level trace initialization functions
     std::vector<AstCFunc*> m_subFuncps;  // Trace sub functions for this scope
     std::set<const AstTraceDecl*> m_declUncalledps;  // Declarations not called
+    // Functions per type and variable kind (wire vs logic etc.)
+    struct DtypeFuncKey final {
+        const AstNodeDType* dtypep;
+        VVarType varType;
+        bool operator==(const DtypeFuncKey& other) const {
+            return dtypep == other.dtypep && varType == other.varType;
+        }
+    };
+    struct DtypeFuncKeyHash final {
+        size_t operator()(const DtypeFuncKey& key) const {
+            return std::hash<const AstNodeDType*>{}(key.dtypep)
+                   ^ (std::hash<uint8_t>{}(key.varType) << 1);
+        }
+    };
+    std::unordered_map<DtypeFuncKey, AstCFunc*, DtypeFuncKeyHash>
+        m_dtypeFuncs;  // Functions per type+kind
+    AstCFunc* m_dtypeFuncp = nullptr;  // Current type func
+    AstCFunc* m_dtypeSubFuncp = nullptr;  // Current type sub func
+    const string m_dtypeArgs{", const char* name, uint32_t fidx, uint32_t c, "
+                             "VerilatedTraceSigDirection direction"};  // Type func args
+    AstTraceDecl* m_dtypeDeclp = nullptr;  // Current type func decl
+    V3UniqueNames m_dtypeNames{""};  // Unique names for dtype funcs
+    bool m_skipDtypeFunc = false;  // Don't create a type func
+    uint32_t m_offset = std::numeric_limits<uint32_t>::max();  // Offset for types
     int m_topFuncSize = 0;  // Size of the top function currently being built
     int m_subFuncSize = 0;  // Size of the sub function currently being built
     const int m_funcSizeLimit  // Maximum size of a function
@@ -255,9 +291,15 @@ class TraceDeclVisitor final : public VNVisitor {
     }
 
     void addToSubFunc(AstNodeStmt* stmtp) {
-        if (m_subFuncSize > m_funcSizeLimit || m_subFuncps.empty()) {
-            m_subFuncSize = 0;
-            //
+        // TODO (maybe) -- sub funcs for dtype components
+        if (m_dtypeSubFuncp) {
+            if (m_subFuncSize > m_funcSizeLimit) newDeclSubFunc();
+            m_dtypeSubFuncp->addStmtsp(stmtp);
+            m_subFuncSize += stmtp->nodeCount();
+            return;
+        }
+        // Defer trace splitting until V3Trace
+        if (m_subFuncps.empty()) {
             FileLine* const flp = m_currScopep->fileline();
             const string n = cvtToStr(m_subFuncps.size());
             const string name{"trace_init_sub__" + m_currScopep->nameDotless() + "__" + n};
@@ -269,20 +311,38 @@ class TraceDeclVisitor final : public VNVisitor {
         m_subFuncSize += stmtp->nodeCount();
     }
 
-    void addTraceDecl(const VNumRange& arrayRange,
-                      int widthOverride) {  // If !=0, is packed struct/array where basicp size
-                                            // misreflects one element
+    AstTraceDecl* addTraceDecl(const VNumRange& arrayRange,
+                               int widthOverride,  // If !=0, is packed struct/array where basicp
+                                                   // size misreflects one element
+                               AstCCall* const dtypeCallp = nullptr) {
         VNumRange bitRange;
         if (widthOverride) {
             bitRange = VNumRange{widthOverride - 1, 0};
         } else if (const AstBasicDType* const bdtypep = m_traValuep->dtypep()->basicp()) {
             bitRange = bdtypep->nrange();
         }
+        FileLine* const flp = m_traVscp->fileline();
+        AstNodeExpr* valuep = m_traValuep->cloneTree(false);
+        const bool validOffset = m_offset != std::numeric_limits<uint32_t>::max();
         AstTraceDecl* const newp
-            = new AstTraceDecl{m_traVscp->fileline(),         m_traName, m_traVscp->varp(),
-                               m_traValuep->cloneTree(false), bitRange,  arrayRange};
+            = new AstTraceDecl{flp,      m_traName,  m_traVscp->varp(), valuep,
+                               bitRange, arrayRange, dtypeCallp,        validOffset};
+        if (validOffset) {
+            newp->code(m_offset);
+            if (!dtypeCallp) { m_offset += newp->codeInc(); }
+            valuep->foreach([&](AstVarRef* const refp) {
+                UASSERT_OBJ(refp->varScopep() == m_traVscp, refp,
+                            "Trace decl expression references unexpected var");
+                refp->replaceWith(new AstCExpr{flp, "__VdtypeVar", m_traVscp->width()});
+                VL_DO_DANGLING(refp->deleteTree(), refp);
+            });
+        } else {
+            newp->dtypeDeclp(m_dtypeDeclp);
+        }
         m_declUncalledps.emplace(newp);
         addToSubFunc(newp);
+
+        return newp;
     }
 
     void addIgnore(const string& why) {
@@ -398,6 +458,166 @@ class TraceDeclVisitor final : public VNVisitor {
         });
     }
 
+    bool isBasicIO() { return m_traVscp->varp()->isVLIO(); }
+    void newDeclSubFunc() {
+        FileLine* const flp = m_dtypeFuncp->fileline();
+        AstCFunc* const subFuncp = newCFunc(flp, m_dtypeNames.get("trace_init_dtype_sub__"));
+        subFuncp->argTypes(subFuncp->argTypes() + m_dtypeArgs);
+        AstCCall* const subCallp = new AstCCall{flp, subFuncp};
+        subCallp->dtypeSetVoid();
+        subCallp->argTypes("tracep, name, fidx, c, direction");
+        m_dtypeFuncp->addStmtsp(subCallp->makeStmt());
+        m_dtypeSubFuncp = subFuncp;
+        m_subFuncSize = 0;
+    }
+    void newDeclFunc(AstNodeDType* nodep) {
+        AstNodeDType* const skipTypep = nodep->skipRefp();
+        // offset and direction args added in EmitCImp
+        std::string callArgs{"tracep, \"" + VIdProtect::protect(m_traName) + "\""};
+        VL_RESTORER(m_traName);
+        FileLine* const flp = skipTypep->fileline();
+
+        const DtypeFuncKey dtypeKey{skipTypep, m_traVscp->varp()->varType()};
+        auto pair = m_dtypeFuncs.emplace(dtypeKey, nullptr);
+        AstCFunc** funcpp = &pair.first->second;
+        if (pair.second) {
+            *funcpp = newCFunc(flp, m_dtypeNames.get("trace_init_dtype__"));
+            (*funcpp)->argTypes((*funcpp)->argTypes() + m_dtypeArgs);
+            (*funcpp)->user2p(m_traVscp);
+        }
+
+        AstCCall* const callp = new AstCCall{flp, *funcpp};
+        callp->dtypeSetVoid();
+        callp->argTypes(callArgs);
+        m_dtypeDeclp = addTraceDecl(VNumRange{}, skipTypep->width(), callp);
+        addToSubFunc(callp->makeStmt());
+
+        if (pair.second) {
+            VL_RESTORER(m_offset);
+            m_offset = 0;
+
+            VL_RESTORER(m_dtypeFuncp);
+            VL_RESTORER(m_dtypeSubFuncp);
+            VL_RESTORER(m_subFuncSize);
+            m_dtypeFuncp = *funcpp;
+            newDeclSubFunc();
+            if (AstStructDType* const dtypep = VN_CAST(skipTypep, StructDType)) {
+                declStruct(dtypep, true);
+            } else if (AstUnpackArrayDType* const dtypep = VN_CAST(skipTypep, UnpackArrayDType)) {
+                declUnpackedArray(dtypep, true);
+            } else if (AstPackArrayDType* const dtypep = VN_CAST(skipTypep, PackArrayDType)) {
+                declPackedArray(dtypep, true);
+            } else {
+                UASSERT_OBJ(false, skipTypep, "Creating a trace function for an unexpected type");
+            }
+            m_dtypeFuncp->user1(m_offset);
+        }
+
+        m_dtypeDeclp->codeInc((*funcpp)->user1());
+        m_offset += m_dtypeDeclp->codeInc();
+    }
+    void declUnpackedArray(AstUnpackArrayDType* const nodep, bool newFunc) {
+        string prefixName(newFunc ? "name" : m_traName);
+
+        VL_RESTORER(m_traName);
+        FileLine* const flp = nodep->fileline();
+
+        addToSubFunc(new AstTracePushPrefix{flp, prefixName, VTracePrefixType::ARRAY_UNPACKED,
+                                            nodep->left(), nodep->right(), !newFunc});
+
+        if (VN_IS(nodep->subDTypep()->skipRefToEnump(),
+                  BasicDType)  // Nothing lower than this array
+            && m_traVscp->dtypep()->skipRefToEnump() == nodep) {  // Nothing above this array
+            // Simple 1-D array, use existing V3EmitC runtime loop rather than unrolling
+            // This will put "(index)" at end of signal name for us
+            if (m_traVscp->dtypep()->skipRefToEnump()->isString()) {
+                addIgnore("Unsupported: strings");
+            } else {
+                m_traName = "";
+                addTraceDecl(nodep->declRange(), 0);
+            }
+        } else {
+            AstNodeDType* const subtypep = nodep->subDTypep()->skipRefToEnump();
+            // Always iterate left index to right index
+            const int inc = nodep->rangep()->ascending() ? 1 : -1;
+            for (int i = nodep->left(); i != nodep->right() + inc; i += inc) {
+                VL_RESTORER(m_traValuep);
+                m_traName = '[' + std::to_string(i) + ']';
+                m_traValuep = m_traValuep->cloneTree(false);
+                m_traValuep = new AstArraySel{flp, m_traValuep, i - nodep->lo()};
+                m_traValuep->dtypep(subtypep);
+                iterate(subtypep);
+                VL_DO_DANGLING(m_traValuep->deleteTree(), m_traValuep);
+            }
+        }
+
+        addToSubFunc(new AstTracePopPrefix{flp});
+    }
+    void declPackedArray(AstPackArrayDType* const nodep, bool newFunc) {
+        string prefixName(newFunc ? "name" : m_traName);
+        AstNodeDType* const subtypep = nodep->subDTypep()->skipRefToEnump();
+
+        VL_RESTORER(m_traName);
+        FileLine* const flp = nodep->fileline();
+
+        addToSubFunc(new AstTracePushPrefix{flp, prefixName, VTracePrefixType::ARRAY_PACKED,
+                                            nodep->left(), nodep->right(), !newFunc});
+
+        // Always iterate left index to right index
+        const int inc = nodep->rangep()->ascending() ? 1 : -1;
+        for (int i = nodep->left(); i != nodep->right() + inc; i += inc) {
+            VL_RESTORER(m_traValuep);
+            m_traName = '[' + std::to_string(i) + ']';
+            const int lsb = (i - nodep->lo()) * subtypep->width();
+            m_traValuep = m_traValuep->cloneTree(false);
+            m_traValuep = new AstSel{flp, m_traValuep, lsb, subtypep->width()};
+            m_traValuep->dtypep(subtypep);
+            iterate(subtypep);
+            VL_DO_CLEAR(m_traValuep->deleteTree(), m_traValuep = nullptr);
+        }
+
+        addToSubFunc(new AstTracePopPrefix{flp});
+    }
+    void declStruct(AstStructDType* const nodep, bool newFunc) {
+        FileLine* const flp = nodep->fileline();
+        string prefixName(newFunc ? "name" : m_traName);
+        int nMembers = 0;
+        for (AstNode* mp = nodep->membersp(); mp; mp = mp->nextp()) ++nMembers;
+        if (!nodep->packed()) {
+            addToSubFunc(new AstTracePushPrefix{flp, prefixName,  //
+                                                VTracePrefixType::STRUCT_UNPACKED, nMembers, 0,
+                                                !newFunc});
+            for (const AstMemberDType *itemp = nodep->membersp(), *nextp; itemp; itemp = nextp) {
+                nextp = VN_AS(itemp->nextp(), MemberDType);
+                AstNodeDType* const subtypep = itemp->subDTypep()->skipRefToEnump();
+                m_traName = itemp->prettyName();
+                VL_RESTORER(m_traValuep);
+                m_traValuep = m_traValuep->cloneTree(false);
+                m_traValuep = new AstStructSel{flp, m_traValuep, itemp->name()};
+                m_traValuep->dtypep(subtypep);
+                iterate(subtypep);
+                VL_DO_DANGLING(m_traValuep->deleteTree(), m_traValuep);
+            }
+            addToSubFunc(new AstTracePopPrefix{flp});
+        } else {
+            addToSubFunc(new AstTracePushPrefix{flp, prefixName,  //
+                                                VTracePrefixType::STRUCT_PACKED, nMembers, 0,
+                                                !newFunc});
+            for (const AstMemberDType *itemp = nodep->membersp(), *nextp; itemp; itemp = nextp) {
+                nextp = VN_AS(itemp->nextp(), MemberDType);
+                AstNodeDType* const subtypep = itemp->subDTypep()->skipRefToEnump();
+                m_traName = itemp->prettyName();
+                VL_RESTORER(m_traValuep);
+                m_traValuep = m_traValuep->cloneTree(false);
+                m_traValuep = new AstSel{flp, m_traValuep, itemp->lsb(), subtypep->width()};
+                m_traValuep->dtypep(subtypep);
+                iterate(subtypep);
+                VL_DO_DANGLING(m_traValuep->deleteTree(), m_traValuep);
+            }
+            addToSubFunc(new AstTracePopPrefix{flp});
+        }
+    }
+
     // VISITORS
     void visit(AstScope* nodep) override {
         UINFO(9, "visit " << nodep);
@@ -545,10 +765,14 @@ class TraceDeclVisitor final : public VNVisitor {
     // VISITORS - Data types when tracing
     void visit(AstConstDType* nodep) override {
         if (!m_traVscp) return;
+        VL_RESTORER(m_offset);
+        VL_RESTORER(m_skipDtypeFunc);
+        m_skipDtypeFunc = true;
         iterate(nodep->subDTypep()->skipRefToEnump());
     }
     void visit(AstRefDType* nodep) override {
         if (!m_traVscp) return;
+        VL_RESTORER(m_offset);
         iterate(nodep->subDTypep()->skipRefToEnump());
     }
     void visit(AstIfaceRefDType* /*nodep*/) override {
@@ -570,39 +794,22 @@ class TraceDeclVisitor final : public VNVisitor {
             return;
         }
 
-        VL_RESTORER(m_traName);
-        FileLine* const flp = nodep->fileline();
-
-        addToSubFunc(new AstTracePushPrefix{flp, m_traName, VTracePrefixType::ARRAY_UNPACKED,
-                                            nodep->left(), nodep->right()});
-
-        if (VN_IS(nodep->subDTypep()->skipRefToEnump(),
-                  BasicDType)  // Nothing lower than this array
-            && m_traVscp->dtypep()->skipRefToEnump() == nodep) {  // Nothing above this array
-            // Simple 1-D array, use existing V3EmitC runtime loop rather than unrolling
-            // This will put "(index)" at end of signal name for us
-            if (m_traVscp->dtypep()->skipRefToEnump()->isString()) {
-                addIgnore("Unsupported: strings");
-            } else {
-                m_traName = "";
-                addTraceDecl(nodep->declRange(), 0);
-            }
-        } else {
-            AstNodeDType* const subtypep = nodep->subDTypep()->skipRefToEnump();
-            // Always iterate left index to right index
-            const int inc = nodep->rangep()->ascending() ? 1 : -1;
-            for (int i = nodep->left(); i != nodep->right() + inc; i += inc) {
-                VL_RESTORER(m_traValuep);
-                m_traName = '[' + std::to_string(i) + ']';
-                m_traValuep = m_traValuep->cloneTree(false);
-                m_traValuep = new AstArraySel{flp, m_traValuep, i - nodep->lo()};
-                m_traValuep->dtypep(subtypep);
-                iterate(subtypep);
-                VL_DO_DANGLING(m_traValuep->deleteTree(), m_traValuep);
-            }
+        // Skip unpacked arrays of non-traceable leaf types (e.g. strings)
+        if (VN_IS(nodep->subDTypep()->skipRefToEnump(), BasicDType)
+            && nodep->subDTypep()->skipRefToEnump()->isString()) {
+            addIgnore("Unsupported: strings");
+            return;
         }
 
-        addToSubFunc(new AstTracePopPrefix{flp});
+        VL_RESTORER(m_skipDtypeFunc);
+        VL_RESTORER(m_dtypeDeclp);
+        if (isBasicIO()) m_skipDtypeFunc = true;
+
+        if (!(m_skipDtypeFunc || m_dtypeDeclp)) {
+            VL_RESTORER(m_offset);
+            newDeclFunc(nodep);
+        }
+        declUnpackedArray(nodep, false);
     }
     void visit(AstPackArrayDType* nodep) override {
         if (!m_traVscp) return;
@@ -625,26 +832,15 @@ class TraceDeclVisitor final : public VNVisitor {
             }
         }
 
-        VL_RESTORER(m_traName);
-        FileLine* const flp = nodep->fileline();
+        VL_RESTORER(m_skipDtypeFunc);
+        VL_RESTORER(m_dtypeDeclp);
+        if (isBasicIO()) m_skipDtypeFunc = true;
 
-        addToSubFunc(new AstTracePushPrefix{flp, m_traName, VTracePrefixType::ARRAY_PACKED,
-                                            nodep->left(), nodep->right()});
-
-        // Always iterate left index to right index
-        const int inc = nodep->rangep()->ascending() ? 1 : -1;
-        for (int i = nodep->left(); i != nodep->right() + inc; i += inc) {
-            VL_RESTORER(m_traValuep);
-            m_traName = '[' + std::to_string(i) + ']';
-            const int lsb = (i - nodep->lo()) * subtypep->width();
-            m_traValuep = m_traValuep->cloneTree(false);
-            m_traValuep = new AstSel{flp, m_traValuep, lsb, subtypep->width()};
-            m_traValuep->dtypep(subtypep);
-            iterate(subtypep);
-            VL_DO_CLEAR(m_traValuep->deleteTree(), m_traValuep = nullptr);
+        if (!(m_skipDtypeFunc || m_dtypeDeclp)) {
+            VL_RESTORER(m_offset);
+            newDeclFunc(nodep);
         }
-
-        addToSubFunc(new AstTracePopPrefix{flp});
+        declPackedArray(nodep, false);
     }
     void visit(AstStructDType* nodep) override {
         if (!m_traVscp) return;
@@ -657,47 +853,26 @@ class TraceDeclVisitor final : public VNVisitor {
             return;
         }
 
-        VL_RESTORER(m_traName);
-        FileLine* const flp = nodep->fileline();
+        VL_RESTORER(m_skipDtypeFunc);
+        VL_RESTORER(m_dtypeDeclp);
+        if (isBasicIO()) m_skipDtypeFunc = true;
 
-        int nMembers = 0;
-        for (AstNode* mp = nodep->membersp(); mp; mp = mp->nextp()) ++nMembers;
-
-        if (!nodep->packed()) {
-            addToSubFunc(new AstTracePushPrefix{flp, m_traName,  //
-                                                VTracePrefixType::STRUCT_UNPACKED, nMembers});
-            for (const AstMemberDType *itemp = nodep->membersp(), *nextp; itemp; itemp = nextp) {
-                nextp = VN_AS(itemp->nextp(), MemberDType);
-                AstNodeDType* const subtypep = itemp->subDTypep()->skipRefToEnump();
-                m_traName = itemp->prettyName();
-                VL_RESTORER(m_traValuep);
-                m_traValuep = m_traValuep->cloneTree(false);
-                m_traValuep = new AstStructSel{flp, m_traValuep, itemp->name()};
-                m_traValuep->dtypep(subtypep);
-                iterate(subtypep);
-                VL_DO_DANGLING(m_traValuep->deleteTree(), m_traValuep);
-            }
-            addToSubFunc(new AstTracePopPrefix{flp});
-        } else {
-            addToSubFunc(new AstTracePushPrefix{flp, m_traName,  //
-                                                VTracePrefixType::STRUCT_PACKED, nMembers});
-            for (const AstMemberDType *itemp = nodep->membersp(), *nextp; itemp; itemp = nextp) {
-                nextp = VN_AS(itemp->nextp(), MemberDType);
-                AstNodeDType* const subtypep = itemp->subDTypep()->skipRefToEnump();
-                m_traName = itemp->prettyName();
-                VL_RESTORER(m_traValuep);
-                m_traValuep = m_traValuep->cloneTree(false);
-                m_traValuep = new AstSel{flp, m_traValuep, itemp->lsb(), subtypep->width()};
-                m_traValuep->dtypep(subtypep);
-                iterate(subtypep);
-                VL_DO_DANGLING(m_traValuep->deleteTree(), m_traValuep);
-            }
-            addToSubFunc(new AstTracePopPrefix{flp});
+        // Only create sub functions for top-level structs, i.e. don't have struct funcs
+        // call other struct funcs for child types.  This could easily be done for decl funcs
+        // but full / chg funcs would require copying / aligning data for child types or more
+        // complicated / wonky / generalized data access.
+        if (!(m_skipDtypeFunc || m_dtypeDeclp)) {
+            VL_RESTORER(m_offset);
+            newDeclFunc(nodep);
         }
+        declStruct(nodep, false);
     }
     void visit(AstUnionDType* nodep) override {
         if (!m_traVscp) return;
 
+        VL_RESTORER(m_skipDtypeFunc);
+        m_skipDtypeFunc = true;
+
         if (nodep->packed() && !v3Global.opt.traceStructs()) {
             // Everything downstream is packed, so deal with as one trace unit
             // This may not be the nicest for user presentation, but is
diff --git a/test_regress/driver.py b/test_regress/driver.py
index 44156b8ab..6f214145b 100755
--- a/test_regress/driver.py
+++ b/test_regress/driver.py
@@ -2634,49 +2634,85 @@ class VlTest:
             case _:
                 self.error("Unknown trace file format " + traceFn)
 
-    def _vcd_read(self, filename: str) -> dict:
-        data = {}
+    @staticmethod
+    def _vcd_parse_header(filename: str, root_scope: 'str | None' = None) -> 'tuple[dict, dict]':
+        """Parse VCD header into hierarchy data and signal-code mapping.
+
+        Returns (hier_data, var_codes) where:
+          hier_data: dict used by _vcd_read for hierarchy comparison
+                     (scope paths -> scope description, var paths -> $var prefix,
+                      attr paths -> $attrbegin text)
+          var_codes: dict mapping 'scope.signal' -> VCD code identifier
+        """
+        hier_data: dict = {}
+        var_codes: dict = {}
+        hier_stack = [root_scope] if root_scope else []
+        attr: list = []
         with open(filename, 'r', encoding='latin-1') as fh:
-            hier_stack = ["TOP"]
-            var = []
-            attr = []
             for line in fh:
-                match1 = re.search(r'\$scope (\S*)\s+(\S+)', line)
-                match2 = re.search(r'(\$var \S+\s+\d+\s+)\S+\s+(.+)\s+\$end', line)
-                match3 = re.search(r'(\$attrbegin .* \$end)', line)
-                line = line.rstrip()
-                # print("VR"+ ' '*len(hier_stack) +" L " + line)
-                if match1:  # $scope
-                    name = match1.group(2)
-                    # print("VR"+ ' '*len(hier_stack) +" scope " + line)
-                    hier_stack += [name]
+                m_scope = re.search(r'\$scope\s+(\S*)\s+(\S+)', line)
+                m_var = re.search(r'(\$var\s+\S+\s+\d+\s+)(\S+)\s+(.+)\s+\$end', line)
+                m_attr = re.search(r'(\$attrbegin .* \$end)', line)
+                if m_scope:
+                    scope_type = m_scope.group(1)
+                    name = m_scope.group(2)
+                    hier_stack.append(name)
                     scope = '.'.join(hier_stack)
-                    data[scope] = match1.group(1) + " " + name
+                    hier_data[scope] = scope_type + " " + name
                     if attr:
-                        data[scope + "#"] = " ".join(attr)
+                        hier_data[scope + "#"] = " ".join(attr)
                         attr = []
-                elif match2:  # $var
-                    # print("VR"+ ' '*len(hier_stack) +" var " + line)
+                elif m_var:
                     scope = '.'.join(hier_stack)
-                    var = match2.group(2)
-                    data[scope + "." + var] = match2.group(1)
+                    decl_prefix = m_var.group(1)
+                    code = m_var.group(2)
+                    var_name = m_var.group(3)
+                    hier_data[scope + "." + var_name] = decl_prefix
                     if attr:
-                        data[scope + "." + var + "#"] = " ".join(attr)
+                        hier_data[scope + "." + var_name + "#"] = " ".join(attr)
                         attr = []
-                elif match3:  # $attrbegin
-                    # print("VR"+ ' '*len(hier_stack) +" attr " + line)
-                    attr.append(match3.group(1))
+                    bare_name = var_name.split()[0]
+                    var_codes[scope + "." + bare_name] = code
+                elif m_attr:
+                    attr.append(m_attr.group(1))
                 elif re.search(r'\$enddefinitions', line):
                     break
                 n = len(re.findall(r'\$upscope', line))
                 if n:
-                    for i in range(0, n):  # pylint: disable=unused-variable
-                        # print("VR"+ ' '*len(hier_stack) +" upscope " + line)
+                    for _i in range(0, n):
                         hier_stack.pop()
-            if attr:
-                self.error(f"Unhandled attribute: {attr}")
+        return hier_data, var_codes
+
+    def _vcd_read(self, filename: str) -> dict:
+        data, _ = self._vcd_parse_header(filename, root_scope="TOP")
         return data
 
+    def vcd_extract_codes(self, filename: str) -> dict:
+        _, codes = self._vcd_parse_header(filename)
+        return codes
+
+    def vcd_check_aliased(self, codes: dict, sig_a: str, sig_b: str) -> None:
+        code_a = codes.get(sig_a)
+        code_b = codes.get(sig_b)
+        if code_a is None:
+            self.error(f"Signal '{sig_a}' not found in VCD")
+        if code_b is None:
+            self.error(f"Signal '{sig_b}' not found in VCD")
+        if code_a != code_b:
+            self.error(f"Expected '{sig_a}' (code {code_a}) to alias "
+                       f"'{sig_b}' (code {code_b})")
+
+    def vcd_check_not_aliased(self, codes: dict, sig_a: str, sig_b: str) -> None:
+        code_a = codes.get(sig_a)
+        code_b = codes.get(sig_b)
+        if code_a is None:
+            self.error(f"Signal '{sig_a}' not found in VCD")
+        if code_b is None:
+            self.error(f"Signal '{sig_b}' not found in VCD")
+        if code_a == code_b:
+            self.error(f"Expected '{sig_a}' and '{sig_b}' to have different codes, "
+                       f"both have code {code_a}")
+
     def inline_checks(self) -> None:
         covfn = self.coverage_filename
         contents = self.file_contents(covfn)
@@ -2771,7 +2807,7 @@ class VlTest:
         contents = self.file_contents(filename)
         if contents == "_Already_Errored_":
             return
-        count = len(re.findall(regexp, contents))
+        count = len(re.findall(regexp, contents, re.MULTILINE))
         if expcount != count:
             self.error("File_grep_count: " + filename + ": Got='" + str(count) + "' Expected='" +
                        str(expcount) + "' in regexp: '" + regexp + "'")
@@ -2781,7 +2817,7 @@ class VlTest:
             contents = self.file_contents(filename)
             if contents == "_Already_Errored_":
                 return
-            match = re.search(regexp, contents)
+            match = re.search(regexp, contents, re.MULTILINE)
             if match:
                 if expvalue is not None and str(expvalue) != match.group(1):
                     self.error("file_grep: " + filename + ": Got='" + match.group(1) +
diff --git a/test_regress/t/t_cast_signed.v b/test_regress/t/t_cast_signed.v
index 28aa9d473..82b9ab02d 100644
--- a/test_regress/t/t_cast_signed.v
+++ b/test_regress/t/t_cast_signed.v
@@ -13,7 +13,6 @@ module t;
   initial begin
     smaller = 8'hfa;
     bigger = bigger_t'(signed'(smaller));
-    $display("%x", bigger);  // NOCOMMIT
     if (bigger != 16'hfffa) $stop;
 
     $write("*-* All Finished *-*\n");
diff --git a/test_regress/t/t_mem_trace_split.py b/test_regress/t/t_mem_trace_split.py
index cfdafbaff..13eac0ce8 100755
--- a/test_regress/t/t_mem_trace_split.py
+++ b/test_regress/t/t_mem_trace_split.py
@@ -14,8 +14,11 @@ test.scenarios('simulator')
 test.compile(verilator_flags2=["--trace-vcd", "--trace-structs", "--output-split-ctrace", "32"])
 
 if test.vlt_all:
-    test.file_grep_count(test.obj_dir + "/V" + test.name + "__Trace__0.cpp",
-                         r'void Vt.*trace_chg_.*sub.*{', 3)
+    test.file_grep_count(
+        test.obj_dir + "/V" + test.name + "__Trace__0.cpp",
+        # dtype sub funcs prevent trace_chg splitting, but --vltmt still forces three of them
+        r'void Vt.*trace_chg_.*sub.*{',
+        3 if test.vltmt else 1)
 
 test.execute()
 
diff --git a/test_regress/t/t_trace_abort_cc_fst.out b/test_regress/t/t_trace_abort_cc_fst.out
index 55b39ad82..0b4072402 100644
--- a/test_regress/t/t_trace_abort_cc_fst.out
+++ b/test_regress/t/t_trace_abort_cc_fst.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 14 09:17:24 2026
+Tue Apr 14 15:20:27 2026
 
 $end
 $version
diff --git a/test_regress/t/t_trace_abort_cc_vcd.out b/test_regress/t/t_trace_abort_cc_vcd.out
index 9601161a6..aa2e97c9e 100644
--- a/test_regress/t/t_trace_abort_cc_vcd.out
+++ b/test_regress/t/t_trace_abort_cc_vcd.out
@@ -1,51 +1,50 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
-
  $scope module top $end
-  $var wire 1 # clk $end
+  $var wire 1 " clk $end
   $scope module t $end
-   $var wire 1 # clk $end
-   $var wire 3 $ cyc [2:0] $end
+   $var wire 1 " clk $end
+   $var wire 3 # cyc [2:0] $end
   $upscope $end
  $upscope $end
 $enddefinitions $end
 
 
 #0
-0#
-b000 $
+0"
+b000 #
 #10
-1#
-b001 $
+1"
+b001 #
 #15
-0#
+0"
 #20
-1#
-b010 $
+1"
+b010 #
 #25
-0#
+0"
 #30
-1#
-b011 $
+1"
+b011 #
 #35
-0#
+0"
 #40
-1#
-b100 $
+1"
+b100 #
 #45
-0#
+0"
 #50
-1#
-b101 $
+1"
+b101 #
 #55
-0#
+0"
 #60
-1#
-b110 $
+1"
+b110 #
 #65
-0#
+0"
 #70
-1#
-b111 $
+1"
+b111 #
 #75
-0#
+0"
diff --git a/test_regress/t/t_trace_abort_sc_fst.out b/test_regress/t/t_trace_abort_sc_fst.out
index 345549be8..4704b830d 100644
--- a/test_regress/t/t_trace_abort_sc_fst.out
+++ b/test_regress/t/t_trace_abort_sc_fst.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 14 09:16:46 2026
+Tue Apr 14 15:20:28 2026
 
 $end
 $version
diff --git a/test_regress/t/t_trace_array_cc_fst.out b/test_regress/t/t_trace_array_cc_fst.out
index 8bccd3973..13e0dd49e 100644
--- a/test_regress/t/t_trace_array_cc_fst.out
+++ b/test_regress/t/t_trace_array_cc_fst.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 14 09:16:42 2026
+Tue Apr 14 15:20:28 2026
 
 $end
 $version
diff --git a/test_regress/t/t_trace_array_cc_vcd.out b/test_regress/t/t_trace_array_cc_vcd.out
index a0f552feb..15d19cfc7 100644
--- a/test_regress/t/t_trace_array_cc_vcd.out
+++ b/test_regress/t/t_trace_array_cc_vcd.out
@@ -1,12 +1,12 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module top $end
-  $var wire 1 [K clk $end
+  $var wire 1 ZK clk $end
   $scope module t $end
-   $var wire 1 [K clk $end
-   $var wire 32 # cyc [31:0] $end
+   $var wire 1 ZK clk $end
+   $var wire 32 " cyc [31:0] $end
    $scope module biggie $end
-    $var wire 131073 $ d [131072:0] $end
+    $var wire 131073 # d [131072:0] $end
    $upscope $end
   $upscope $end
  $upscope $end
@@ -14,40 +14,40 @@ $enddefinitions $end
 
 
 #0
-b00000000000000000000000000000000 #
-b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000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-b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 C
-b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 L
-b111 \
-b111111111111111 ]
-b1111111111111111111111111111111 ^
-b111111111111111111111111111111111111111111111111111111111111111 _
-b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 a
-b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 e
-b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 m
-1}
+b00000000000000000000000000000001 "
+1#
+b11 $
+b11111111 %
+b111111111 &
+b1111111111111111 '
+b11111111111111111 (
+b11111111111111111111111111111111 )
+b111111111111111111111111111111111 *
+b1111111111111111111111111111111111111111111111111111111111111111 ,
+b11111111111111111111111111111111111111111111111111111111111111111 .
+b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 1
+b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 5
+b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 :
+b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 B
+b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 K
+b111 [
+b111111111111111 \
+b1111111111111111111111111111111 ]
+b111111111111111111111111111111111111111111111111111111111111111 ^
+b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 `
+b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 d
+b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 l
+1|
 #15
-0}
+0|
 #20
-b00000000000000000000000000000010 #
-0$
-b10 %
-b11111110 &
-b111111110 '
-b1111111111111110 (
-b11111111111111110 )
-b11111111111111111111111111111110 *
-b111111111111111111111111111111110 +
-b1111111111111111111111111111111111111111111111111111111111111110 -
-b11111111111111111111111111111111111111111111111111111111111111110 /
-b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 2
-b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 6
-b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 ;
-b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 C
-b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 L
-b110 \
-b111111111111110 ]
-b1111111111111111111111111111110 ^
-b111111111111111111111111111111111111111111111111111111111111110 _
-b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 a
-b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 e
-b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 m
-1}
+b00000000000000000000000000000010 "
+0#
+b10 $
+b11111110 %
+b111111110 &
+b1111111111111110 '
+b11111111111111110 (
+b11111111111111111111111111111110 )
+b111111111111111111111111111111110 *
+b1111111111111111111111111111111111111111111111111111111111111110 ,
+b11111111111111111111111111111111111111111111111111111111111111110 .
+b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 1
+b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 5
+b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 :
+b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 B
+b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 K
+b110 [
+b111111111111110 \
+b1111111111111111111111111111110 ]
+b111111111111111111111111111111111111111111111111111111111111110 ^
+b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 `
+b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 d
+b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 l
+1|
 #25
-0}
+0|
 #30
-b00000000000000000000000000000011 #
-b00 %
-b11111100 &
-b111111100 '
-b1111111111111100 (
-b11111111111111100 )
-b11111111111111111111111111111100 *
-b111111111111111111111111111111100 +
-b1111111111111111111111111111111111111111111111111111111111111100 -
-b11111111111111111111111111111111111111111111111111111111111111100 /
-b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 2
-b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 6
-b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 ;
-b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 C
-b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 L
-b100 \
-b111111111111100 ]
-b1111111111111111111111111111100 ^
-b111111111111111111111111111111111111111111111111111111111111100 _
-b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 a
-b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 e
-b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 m
-1}
+b00000000000000000000000000000011 "
+b00 $
+b11111100 %
+b111111100 &
+b1111111111111100 '
+b11111111111111100 (
+b11111111111111111111111111111100 )
+b111111111111111111111111111111100 *
+b1111111111111111111111111111111111111111111111111111111111111100 ,
+b11111111111111111111111111111111111111111111111111111111111111100 .
+b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 1
+b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 5
+b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 :
+b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 B
+b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 K
+b100 [
+b111111111111100 \
+b1111111111111111111111111111100 ]
+b111111111111111111111111111111111111111111111111111111111111100 ^
+b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 `
+b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 d
+b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 l
+1|
diff --git a/test_regress/t/t_trace_ascendingrange_sc_fst.out b/test_regress/t/t_trace_ascendingrange_sc_fst.out
index 89a55ae51..80f6ff6fe 100644
--- a/test_regress/t/t_trace_ascendingrange_sc_fst.out
+++ b/test_regress/t/t_trace_ascendingrange_sc_fst.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 14 09:17:01 2026
+Tue Apr 14 15:20:31 2026
 
 $end
 $version
diff --git a/test_regress/t/t_trace_basic_cc_fst.out b/test_regress/t/t_trace_basic_cc_fst.out
index b10a8a91e..6c408a7c4 100644
--- a/test_regress/t/t_trace_basic_cc_fst.out
+++ b/test_regress/t/t_trace_basic_cc_fst.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 14 09:17:07 2026
+Tue Apr 14 15:20:33 2026
 
 $end
 $version
@@ -15,43 +15,43 @@ $end
   $scope module t $end
    $var wire 1 ! clk $end
    $var wire 5 " state [4:0] $end
-   $var wire 1 # fst_inout $end
-   $var int 32 $ cyc [31:0] $end
-   $var logic 1 % rstn $end
-   $var real_parameter 64 & fst_gparam_real $end
-   $var real_parameter 64 ' fst_lparam_real $end
-   $var real 64 & fst_real $end
-   $var integer 32 ( fst_integer [31:0] $end
-   $var bit 1 ) fst_bit $end
-   $var logic 1 * fst_logic $end
-   $var int 32 + fst_int [31:0] $end
-   $var shortint 16 , fst_shortint [15:0] $end
-   $var longint 64 - fst_longint [63:0] $end
-   $var byte 8 . fst_byte [7:0] $end
-   $var time 64 / fst_time [63:0] $end
-   $var parameter 32 0 fst_parameter [31:0] $end
-   $var parameter 32 1 fst_lparam [31:0] $end
-   $var supply0 1 # fst_supply0 $end
-   $var supply1 1 2 fst_supply1 $end
-   $var tri0 1 # fst_tri0 $end
-   $var tri1 1 2 fst_tri1 $end
-   $var tri 1 3 fst_tri $end
-   $var triand 1 4 fst_triand $end
-   $var trior 1 5 fst_trior $end
-   $var triand 1 6 fst_wand $end
-   $var trior 1 7 fst_wor $end
-   $var wire 1 8 fst_wire $end
-   $var wire 1 9 fst_uwire $end
+   $var wire 1 $ fst_inout $end
+   $var int 32 % cyc [31:0] $end
+   $var logic 1 & rstn $end
+   $var real_parameter 64 ' fst_gparam_real $end
+   $var real_parameter 64 ( fst_lparam_real $end
+   $var real 64 ' fst_real $end
+   $var integer 32 ) fst_integer [31:0] $end
+   $var bit 1 * fst_bit $end
+   $var logic 1 + fst_logic $end
+   $var int 32 , fst_int [31:0] $end
+   $var shortint 16 - fst_shortint [15:0] $end
+   $var longint 64 . fst_longint [63:0] $end
+   $var byte 8 / fst_byte [7:0] $end
+   $var time 64 0 fst_time [63:0] $end
+   $var parameter 32 1 fst_parameter [31:0] $end
+   $var parameter 32 2 fst_lparam [31:0] $end
+   $var supply0 1 $ fst_supply0 $end
+   $var supply1 1 3 fst_supply1 $end
+   $var tri0 1 $ fst_tri0 $end
+   $var tri1 1 3 fst_tri1 $end
+   $var tri 1 4 fst_tri $end
+   $var triand 1 5 fst_triand $end
+   $var trior 1 6 fst_trior $end
+   $var triand 1 7 fst_wand $end
+   $var trior 1 8 fst_wor $end
+   $var wire 1 9 fst_wire $end
+   $var wire 1 : fst_uwire $end
    $scope module test $end
     $var wire 1 ! clk $end
-    $var wire 1 % rstn $end
+    $var wire 1 & rstn $end
     $var wire 5 " state [4:0] $end
-    $var logic 5 : state_w [4:0] $end
+    $var logic 5 ; state_w [4:0] $end
     $attrbegin array unpacked bounds 2 $end
     $scope sv_array state_array $end
-     $var logic 5 ; state_array[0] [4:0] $end
-     $var logic 5 < state_array[1] [4:0] $end
-     $var logic 5 = state_array[2] [4:0] $end
+     $var logic 5 < state_array[0] [4:0] $end
+     $var logic 5 = state_array[1] [4:0] $end
+     $var logic 5 > state_array[2] [4:0] $end
     $upscope $end
    $upscope $end
   $upscope $end
@@ -59,32 +59,33 @@ $end
 $enddefinitions $end
 #0
 $dumpvars
+b00000 >
 b00000 =
 b00000 <
 b00000 ;
-b00000 :
+0:
 09
 08
 07
 06
 05
 04
-03
-12
-b00000000000000000000000111001000 1
-b00000000000000000000000001111011 0
-b0000000000000000000000000000000000000000000000000000000000000000 /
-b00000000 .
-b0000000000000000000000000000000000000000000000000000000000000000 -
-b0000000000000000 ,
-b00000000000000000000000000000000 +
+13
+b00000000000000000000000111001000 2
+b00000000000000000000000001111011 1
+b0000000000000000000000000000000000000000000000000000000000000000 0
+b00000000 /
+b0000000000000000000000000000000000000000000000000000000000000000 .
+b0000000000000000 -
+b00000000000000000000000000000000 ,
+0+
 0*
-0)
-b00000000000000000000000000000000 (
-r4.56 '
-r1.23 &
-0%
-b00000000000000000000000000000000 $
+b00000000000000000000000000000000 )
+r4.56 (
+r1.23 '
+0&
+b00000000000000000000000000000000 %
+0$
 0#
 b00000 "
 0!
@@ -92,1044 +93,1044 @@ $end
 #10
 1!
 b00001 "
-b00000000000000000000000000000001 $
-b0000000000000000000000000000000000000000000000000000000000001010 /
-b10100 :
-b00001 ;
+b00000000000000000000000000000001 %
+b0000000000000000000000000000000000000000000000000000000000001010 0
+b10100 ;
 b00001 <
 b00001 =
+b00001 >
 #15
 0!
 #20
 1!
-b0000000000000000000000000000000000000000000000000000000000010100 /
-b00000000000000000000000000000010 $
+b0000000000000000000000000000000000000000000000000000000000010100 0
+b00000000000000000000000000000010 %
 #25
 0!
 #30
 1!
-b00000000000000000000000000000011 $
-b0000000000000000000000000000000000000000000000000000000000011110 /
+b00000000000000000000000000000011 %
+b0000000000000000000000000000000000000000000000000000000000011110 0
 #35
 0!
 #40
 1!
-b0000000000000000000000000000000000000000000000000000000000101000 /
-b00000000000000000000000000000100 $
+b0000000000000000000000000000000000000000000000000000000000101000 0
+b00000000000000000000000000000100 %
 #45
 0!
 #50
 1!
-b00000000000000000000000000000101 $
-b0000000000000000000000000000000000000000000000000000000000110010 /
+b00000000000000000000000000000101 %
+b0000000000000000000000000000000000000000000000000000000000110010 0
 #55
 0!
 #60
 1!
-b0000000000000000000000000000000000000000000000000000000000111100 /
-b00000000000000000000000000000110 $
+b0000000000000000000000000000000000000000000000000000000000111100 0
+b00000000000000000000000000000110 %
 #65
 0!
 #70
 1!
-b00000000000000000000000000000111 $
-b0000000000000000000000000000000000000000000000000000000001000110 /
+b00000000000000000000000000000111 %
+b0000000000000000000000000000000000000000000000000000000001000110 0
 #75
 0!
 #80
 1!
-b0000000000000000000000000000000000000000000000000000000001010000 /
-b00000000000000000000000000001000 $
+b0000000000000000000000000000000000000000000000000000000001010000 0
+b00000000000000000000000000001000 %
 #85
 0!
 #90
 1!
-b00000000000000000000000000001001 $
-b0000000000000000000000000000000000000000000000000000000001011010 /
+b00000000000000000000000000001001 %
+b0000000000000000000000000000000000000000000000000000000001011010 0
 #95
 0!
 #100
 1!
-b0000000000000000000000000000000000000000000000000000000001100100 /
-b00000000000000000000000000001010 $
+b0000000000000000000000000000000000000000000000000000000001100100 0
+b00000000000000000000000000001010 %
 #105
 0!
 #110
 1!
-b00000000000000000000000000001011 $
-b0000000000000000000000000000000000000000000000000000000001101110 /
-1%
+b00000000000000000000000000001011 %
+b0000000000000000000000000000000000000000000000000000000001101110 0
+1&
 #115
 0!
 #120
 1!
-b0000000000000000000000000000000000000000000000000000000001111000 /
-b00000000000000000000000000001100 $
-b10100 =
-b01010 :
+b0000000000000000000000000000000000000000000000000000000001111000 0
+b00000000000000000000000000001100 %
+b10100 >
+b01010 ;
 #125
 0!
 #130
 1!
-b00101 :
-b01010 =
-b00000000000000000000000000001101 $
-b0000000000000000000000000000000000000000000000000000000010000010 /
-b10100 <
+b00101 ;
+b01010 >
+b00000000000000000000000000001101 %
+b0000000000000000000000000000000000000000000000000000000010000010 0
+b10100 =
 #135
 0!
 #140
 1!
-b01010 <
-b0000000000000000000000000000000000000000000000000000000010001100 /
-b00000000000000000000000000001110 $
-b00101 =
-b10110 :
-b10100 ;
+b01010 =
+b0000000000000000000000000000000000000000000000000000000010001100 0
+b00000000000000000000000000001110 %
+b00101 >
+b10110 ;
+b10100 <
 b10100 "
 #145
 0!
 #150
 1!
 b01010 "
-b01010 ;
-b01011 :
-b10110 =
-b00000000000000000000000000001111 $
-b0000000000000000000000000000000000000000000000000000000010010110 /
-b00101 <
+b01010 <
+b01011 ;
+b10110 >
+b00000000000000000000000000001111 %
+b0000000000000000000000000000000000000000000000000000000010010110 0
+b00101 =
 #155
 0!
 #160
 1!
-b10110 <
-b0000000000000000000000000000000000000000000000000000000010100000 /
-b00000000000000000000000000010000 $
-b01011 =
-b10001 :
-b00101 ;
+b10110 =
+b0000000000000000000000000000000000000000000000000000000010100000 0
+b00000000000000000000000000010000 %
+b01011 >
+b10001 ;
+b00101 <
 b00101 "
 #165
 0!
 #170
 1!
 b10110 "
-b10110 ;
-b11100 :
-b10001 =
-b00000000000000000000000000010001 $
-b0000000000000000000000000000000000000000000000000000000010101010 /
-b01011 <
+b10110 <
+b11100 ;
+b10001 >
+b00000000000000000000000000010001 %
+b0000000000000000000000000000000000000000000000000000000010101010 0
+b01011 =
 #175
 0!
 #180
 1!
-b10001 <
-b0000000000000000000000000000000000000000000000000000000010110100 /
-b00000000000000000000000000010010 $
-b11100 =
-b01110 :
-b01011 ;
+b10001 =
+b0000000000000000000000000000000000000000000000000000000010110100 0
+b00000000000000000000000000010010 %
+b11100 >
+b01110 ;
+b01011 <
 b01011 "
 #185
 0!
 #190
 1!
 b10001 "
-b10001 ;
-b00111 :
-b01110 =
-b00000000000000000000000000010011 $
-b0000000000000000000000000000000000000000000000000000000010111110 /
-b11100 <
+b10001 <
+b00111 ;
+b01110 >
+b00000000000000000000000000010011 %
+b0000000000000000000000000000000000000000000000000000000010111110 0
+b11100 =
 #195
 0!
 #200
 1!
-b01110 <
-b0000000000000000000000000000000000000000000000000000000011001000 /
-b00000000000000000000000000010100 $
-b00111 =
-b10111 :
-b11100 ;
+b01110 =
+b0000000000000000000000000000000000000000000000000000000011001000 0
+b00000000000000000000000000010100 %
+b00111 >
+b10111 ;
+b11100 <
 b11100 "
 #205
 0!
 #210
 1!
 b01110 "
-b01110 ;
-b11111 :
-b10111 =
-b00000000000000000000000000010101 $
-b0000000000000000000000000000000000000000000000000000000011010010 /
-b00111 <
+b01110 <
+b11111 ;
+b10111 >
+b00000000000000000000000000010101 %
+b0000000000000000000000000000000000000000000000000000000011010010 0
+b00111 =
 #215
 0!
 #220
 1!
-b10111 <
-b0000000000000000000000000000000000000000000000000000000011011100 /
-b00000000000000000000000000010110 $
-b11111 =
-b11011 :
-b00111 ;
+b10111 =
+b0000000000000000000000000000000000000000000000000000000011011100 0
+b00000000000000000000000000010110 %
+b11111 >
+b11011 ;
+b00111 <
 b00111 "
 #225
 0!
 #230
 1!
 b10111 "
-b10111 ;
-b11001 :
-b11011 =
-b00000000000000000000000000010111 $
-b0000000000000000000000000000000000000000000000000000000011100110 /
-b11111 <
+b10111 <
+b11001 ;
+b11011 >
+b00000000000000000000000000010111 %
+b0000000000000000000000000000000000000000000000000000000011100110 0
+b11111 =
 #235
 0!
 #240
 1!
-b11011 <
-b0000000000000000000000000000000000000000000000000000000011110000 /
-b00000000000000000000000000011000 $
-b11001 =
-b11000 :
-b11111 ;
+b11011 =
+b0000000000000000000000000000000000000000000000000000000011110000 0
+b00000000000000000000000000011000 %
+b11001 >
+b11000 ;
+b11111 <
 b11111 "
 #245
 0!
 #250
 1!
 b11011 "
-b11011 ;
-b01100 :
-b11000 =
-b00000000000000000000000000011001 $
-b0000000000000000000000000000000000000000000000000000000011111010 /
-b11001 <
+b11011 <
+b01100 ;
+b11000 >
+b00000000000000000000000000011001 %
+b0000000000000000000000000000000000000000000000000000000011111010 0
+b11001 =
 #255
 0!
 #260
 1!
-b11000 <
-b0000000000000000000000000000000000000000000000000000000100000100 /
-b00000000000000000000000000011010 $
-b01100 =
-b00110 :
-b11001 ;
+b11000 =
+b0000000000000000000000000000000000000000000000000000000100000100 0
+b00000000000000000000000000011010 %
+b01100 >
+b00110 ;
+b11001 <
 b11001 "
 #265
 0!
 #270
 1!
 b11000 "
-b11000 ;
-b00011 :
-b00110 =
-b00000000000000000000000000011011 $
-b0000000000000000000000000000000000000000000000000000000100001110 /
-b01100 <
+b11000 <
+b00011 ;
+b00110 >
+b00000000000000000000000000011011 %
+b0000000000000000000000000000000000000000000000000000000100001110 0
+b01100 =
 #275
 0!
 #280
 1!
-b00110 <
-b0000000000000000000000000000000000000000000000000000000100011000 /
-b00000000000000000000000000011100 $
-b00011 =
-b10101 :
-b01100 ;
+b00110 =
+b0000000000000000000000000000000000000000000000000000000100011000 0
+b00000000000000000000000000011100 %
+b00011 >
+b10101 ;
+b01100 <
 b01100 "
 #285
 0!
 #290
 1!
 b00110 "
-b00110 ;
-b11110 :
-b10101 =
-b00000000000000000000000000011101 $
-b0000000000000000000000000000000000000000000000000000000100100010 /
-b00011 <
+b00110 <
+b11110 ;
+b10101 >
+b00000000000000000000000000011101 %
+b0000000000000000000000000000000000000000000000000000000100100010 0
+b00011 =
 #295
 0!
 #300
 1!
-b10101 <
-b0000000000000000000000000000000000000000000000000000000100101100 /
-b00000000000000000000000000011110 $
-b11110 =
-b01111 :
-b00011 ;
+b10101 =
+b0000000000000000000000000000000000000000000000000000000100101100 0
+b00000000000000000000000000011110 %
+b11110 >
+b01111 ;
+b00011 <
 b00011 "
 #305
 0!
 #310
 1!
 b10101 "
-b10101 ;
-b10011 :
-b01111 =
-b00000000000000000000000000011111 $
-b0000000000000000000000000000000000000000000000000000000100110110 /
-b11110 <
+b10101 <
+b10011 ;
+b01111 >
+b00000000000000000000000000011111 %
+b0000000000000000000000000000000000000000000000000000000100110110 0
+b11110 =
 #315
 0!
 #320
 1!
-b01111 <
-b0000000000000000000000000000000000000000000000000000000101000000 /
-b00000000000000000000000000100000 $
-b10011 =
-b11101 :
-b11110 ;
+b01111 =
+b0000000000000000000000000000000000000000000000000000000101000000 0
+b00000000000000000000000000100000 %
+b10011 >
+b11101 ;
+b11110 <
 b11110 "
 #325
 0!
 #330
 1!
 b01111 "
-b01111 ;
-b11010 :
-b11101 =
-b00000000000000000000000000100001 $
-b0000000000000000000000000000000000000000000000000000000101001010 /
-b10011 <
+b01111 <
+b11010 ;
+b11101 >
+b00000000000000000000000000100001 %
+b0000000000000000000000000000000000000000000000000000000101001010 0
+b10011 =
 #335
 0!
 #340
 1!
-b11101 <
-b0000000000000000000000000000000000000000000000000000000101010100 /
-b00000000000000000000000000100010 $
-b11010 =
-b01101 :
-b10011 ;
+b11101 =
+b0000000000000000000000000000000000000000000000000000000101010100 0
+b00000000000000000000000000100010 %
+b11010 >
+b01101 ;
+b10011 <
 b10011 "
 #345
 0!
 #350
 1!
 b11101 "
-b11101 ;
-b10010 :
-b01101 =
-b00000000000000000000000000100011 $
-b0000000000000000000000000000000000000000000000000000000101011110 /
-b11010 <
+b11101 <
+b10010 ;
+b01101 >
+b00000000000000000000000000100011 %
+b0000000000000000000000000000000000000000000000000000000101011110 0
+b11010 =
 #355
 0!
 #360
 1!
-b01101 <
-b0000000000000000000000000000000000000000000000000000000101101000 /
-b00000000000000000000000000100100 $
-b10010 =
-b01001 :
-b11010 ;
+b01101 =
+b0000000000000000000000000000000000000000000000000000000101101000 0
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diff --git a/test_regress/t/t_trace_basic_cc_vcd.out b/test_regress/t/t_trace_basic_cc_vcd.out
index 8c62a5081..7c7cbc7d8 100644
--- a/test_regress/t/t_trace_basic_cc_vcd.out
+++ b/test_regress/t/t_trace_basic_cc_vcd.out
@@ -7,33 +7,33 @@ $timescale 1ps $end
   $scope module t $end
    $var wire 1 & clk $end
    $var wire 5 ' state [4:0] $end
-   $var wire 1 , fst_inout $end
+   $var wire 1 - fst_inout $end
    $var wire 32 ( cyc [31:0] $end
    $var wire 1 ) rstn $end
-   $var real 64 - fst_gparam_real $end
-   $var real 64 / fst_lparam_real $end
-   $var real 64 - fst_real $end
-   $var wire 32 1 fst_integer [31:0] $end
-   $var wire 1 2 fst_bit $end
-   $var wire 1 3 fst_logic $end
-   $var wire 32 4 fst_int [31:0] $end
-   $var wire 16 5 fst_shortint [15:0] $end
-   $var wire 64 6 fst_longint [63:0] $end
-   $var wire 8 8 fst_byte [7:0] $end
+   $var real 64 . fst_gparam_real $end
+   $var real 64 0 fst_lparam_real $end
+   $var real 64 . fst_real $end
+   $var wire 32 2 fst_integer [31:0] $end
+   $var wire 1 3 fst_bit $end
+   $var wire 1 4 fst_logic $end
+   $var wire 32 5 fst_int [31:0] $end
+   $var wire 16 6 fst_shortint [15:0] $end
+   $var wire 64 7 fst_longint [63:0] $end
+   $var wire 8 9 fst_byte [7:0] $end
    $var wire 64 * fst_time [63:0] $end
-   $var wire 32 9 fst_parameter [31:0] $end
-   $var wire 32 : fst_lparam [31:0] $end
-   $var wire 1 , fst_supply0 $end
-   $var wire 1 ; fst_supply1 $end
-   $var wire 1 , fst_tri0 $end
-   $var wire 1 ; fst_tri1 $end
-   $var wire 1 < fst_tri $end
-   $var wire 1 = fst_triand $end
-   $var wire 1 > fst_trior $end
-   $var wire 1 ? fst_wand $end
-   $var wire 1 @ fst_wor $end
-   $var wire 1 A fst_wire $end
-   $var wire 1 B fst_uwire $end
+   $var wire 32 : fst_parameter [31:0] $end
+   $var wire 32 ; fst_lparam [31:0] $end
+   $var wire 1 - fst_supply0 $end
+   $var wire 1 < fst_supply1 $end
+   $var wire 1 - fst_tri0 $end
+   $var wire 1 < fst_tri1 $end
+   $var wire 1 = fst_tri $end
+   $var wire 1 > fst_triand $end
+   $var wire 1 ? fst_trior $end
+   $var wire 1 @ fst_wand $end
+   $var wire 1 A fst_wor $end
+   $var wire 1 B fst_wire $end
+   $var wire 1 C fst_uwire $end
    $scope module test $end
     $var wire 1 & clk $end
     $var wire 1 ) rstn $end
@@ -59,25 +59,26 @@ b00000000000000000000000000000000 (
 0)
 b0000000000000000000000000000000000000000000000000000000000000000 *
 0,
-r1.23 -
-r4.56 /
-b00000000000000000000000000000000 1
-02
+0-
+r1.23 .
+r4.56 0
+b00000000000000000000000000000000 2
 03
-b00000000000000000000000000000000 4
-b0000000000000000 5
-b0000000000000000000000000000000000000000000000000000000000000000 6
-b00000000 8
-b00000000000000000000000001111011 9
-b00000000000000000000000111001000 :
-1;
-0<
+04
+b00000000000000000000000000000000 5
+b0000000000000000 6
+b0000000000000000000000000000000000000000000000000000000000000000 7
+b00000000 9
+b00000000000000000000000001111011 :
+b00000000000000000000000111001000 ;
+1<
 0=
 0>
 0?
 0@
 0A
 0B
+0C
 #10
 b10100 "
 b00001 #
diff --git a/test_regress/t/t_trace_basic_sc_fst.out b/test_regress/t/t_trace_basic_sc_fst.out
index 1cafa6260..83a2b7042 100644
--- a/test_regress/t/t_trace_basic_sc_fst.out
+++ b/test_regress/t/t_trace_basic_sc_fst.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 14 09:17:04 2026
+Tue Apr 14 15:20:34 2026
 
 $end
 $version
diff --git a/test_regress/t/t_trace_binary.out b/test_regress/t/t_trace_binary.out
index cec4aa1d5..06f290756 100644
--- a/test_regress/t/t_trace_binary.out
+++ b/test_regress/t/t_trace_binary.out
@@ -1,12 +1,12 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module t $end
-  $var wire 32 # sig [31:0] $end
+  $var wire 32 " sig [31:0] $end
  $upscope $end
 $enddefinitions $end
 
 
 #0
-b00000000000000000000000000001010 #
+b00000000000000000000000000001010 "
 #20
-b00000000000000000000000000010100 #
+b00000000000000000000000000010100 "
diff --git a/test_regress/t/t_trace_cat_renew_fst_part_0000.out b/test_regress/t/t_trace_cat_renew_fst_part_0000.out
index 99ed7e50f..21cd714dd 100644
--- a/test_regress/t/t_trace_cat_renew_fst_part_0000.out
+++ b/test_regress/t/t_trace_cat_renew_fst_part_0000.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 14 09:17:00 2026
+Tue Apr 14 15:20:35 2026
 
 $end
 $version
diff --git a/test_regress/t/t_trace_cat_renew_fst_part_0100.out b/test_regress/t/t_trace_cat_renew_fst_part_0100.out
index f3db05a63..a04f97b25 100644
--- a/test_regress/t/t_trace_cat_renew_fst_part_0100.out
+++ b/test_regress/t/t_trace_cat_renew_fst_part_0100.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 14 09:17:49 2026
+Tue Apr 14 15:21:24 2026
 
 $end
 $version
diff --git a/test_regress/t/t_trace_cat_reopen_fst_part_0000.out b/test_regress/t/t_trace_cat_reopen_fst_part_0000.out
index 2ed6b4680..8f556706c 100644
--- a/test_regress/t/t_trace_cat_reopen_fst_part_0000.out
+++ b/test_regress/t/t_trace_cat_reopen_fst_part_0000.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 14 09:16:55 2026
+Tue Apr 14 15:20:36 2026
 
 $end
 $version
diff --git a/test_regress/t/t_trace_cat_reopen_fst_part_0100.out b/test_regress/t/t_trace_cat_reopen_fst_part_0100.out
index 967ec48e5..a04f97b25 100644
--- a/test_regress/t/t_trace_cat_reopen_fst_part_0100.out
+++ b/test_regress/t/t_trace_cat_reopen_fst_part_0100.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 14 09:17:45 2026
+Tue Apr 14 15:21:24 2026
 
 $end
 $version
diff --git a/test_regress/t/t_trace_class.out b/test_regress/t/t_trace_class.out
index a7c8f9fe0..d34e4b42e 100644
--- a/test_regress/t/t_trace_class.out
+++ b/test_regress/t/t_trace_class.out
@@ -1,10 +1,10 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module $unit::Cls__P0__Vclpkg $end
-  $var wire 32 # PARAM [31:0] $end
+  $var wire 32 " PARAM [31:0] $end
  $upscope $end
 $enddefinitions $end
 
 
 #0
-b00000000000000000000000000000000 #
+b00000000000000000000000000000000 "
diff --git a/test_regress/t/t_trace_complex.v b/test_regress/t/t_trace_complex.v
index 0391bbe8c..a6cdc68b1 100644
--- a/test_regress/t/t_trace_complex.v
+++ b/test_regress/t/t_trace_complex.v
@@ -38,6 +38,7 @@ module t (
   typedef strp_t arru_strp_t[4:3];
 
   strp_t v_strp;
+  strp_t v_strp2;
   strp_strp_t v_strp_strp;
   unip_strp_t v_unip_strp;
   arrp_t v_arrp;
@@ -98,6 +99,7 @@ module t (
   always @(posedge clk) begin
     cyc <= cyc + 1;
     v_strp <= ~v_strp;
+    v_strp2 <= ~v_strp2;
     v_strp_strp <= ~v_strp_strp;
     v_unip_strp <= ~v_unip_strp;
     v_arrp_strp <= ~v_arrp_strp;
diff --git a/test_regress/t/t_trace_complex_default_cc_fst.out b/test_regress/t/t_trace_complex_default_cc_fst.out
index 184ccc1e8..dd52c681b 100644
--- a/test_regress/t/t_trace_complex_default_cc_fst.out
+++ b/test_regress/t/t_trace_complex_default_cc_fst.out
@@ -1,5 +1,9 @@
 $date
-Sat Mar 14 09:16:56 2026
+<<<<<<< HEAD
+Tue Apr 14 15:20:37 2026
+=======
+Tue Mar 31 17:14:29 2026
+>>>>>>> 8895f96e4 (CR)
 
 $end
 $version
@@ -19,106 +23,108 @@ $end
    $var wire 1 ! clk $end
    $var integer 32 # cyc [31:0] $end
    $var bit 2 $ v_strp [1:0] $end
-   $var bit 4 % v_strp_strp [3:0] $end
-   $var bit 2 & v_unip_strp [1:0] $end
-   $var bit 2 ' v_arrp [2:1] $end
-   $var bit 4 ( v_arrp_arrp [3:0] $end
-   $var bit 4 ) v_arrp_strp [3:0] $end
+   $var bit 2 % v_strp2 [1:0] $end
+   $var bit 4 & v_strp_strp [3:0] $end
+   $var bit 2 ' v_unip_strp [1:0] $end
+   $var bit 2 ( v_arrp [2:1] $end
+   $var bit 4 ) v_arrp_arrp [3:0] $end
+   $var bit 4 * v_arrp_strp [3:0] $end
    $attrbegin array unpacked bounds 8589934593 $end
    $scope sv_array v_arru $end
-    $var bit 1 * v_arru[2] $end
-    $var bit 1 + v_arru[1] $end
+    $var bit 1 + v_arru[2] $end
+    $var bit 1 , v_arru[1] $end
    $upscope $end
    $attrbegin array unpacked bounds 17179869187 $end
    $scope sv_array v_arru_arru $end
     $attrbegin array unpacked bounds 8589934593 $end
     $scope sv_array [4] $end
-     $var bit 1 , v_arru_arru[4][2] $end
-     $var bit 1 - v_arru_arru[4][1] $end
+     $var bit 1 - v_arru_arru[4][2] $end
+     $var bit 1 . v_arru_arru[4][1] $end
     $upscope $end
     $attrbegin array unpacked bounds 8589934593 $end
     $scope sv_array [3] $end
-     $var bit 1 . v_arru_arru[3][2] $end
-     $var bit 1 / v_arru_arru[3][1] $end
+     $var bit 1 / v_arru_arru[3][2] $end
+     $var bit 1 0 v_arru_arru[3][1] $end
     $upscope $end
    $upscope $end
    $attrbegin array unpacked bounds 17179869187 $end
    $scope sv_array v_arru_arrp $end
-    $var bit 2 0 v_arru_arrp[4] [2:1] $end
-    $var bit 2 1 v_arru_arrp[3] [2:1] $end
+    $var bit 2 1 v_arru_arrp[4] [2:1] $end
+    $var bit 2 2 v_arru_arrp[3] [2:1] $end
    $upscope $end
    $attrbegin array unpacked bounds 17179869187 $end
    $scope sv_array v_arru_strp $end
-    $var bit 2 2 v_arru_strp[4] [1:0] $end
-    $var bit 2 3 v_arru_strp[3] [1:0] $end
+    $var bit 2 3 v_arru_strp[4] [1:0] $end
+    $var bit 2 4 v_arru_strp[3] [1:0] $end
    $upscope $end
-   $var real 64 4 v_real $end
+   $var real 64 5 v_real $end
    $attrbegin array unpacked bounds 1 $end
    $scope sv_array v_arr_real $end
-    $var real 64 5 v_arr_real[0] $end
-    $var real 64 6 v_arr_real[1] $end
+    $var real 64 6 v_arr_real[0] $end
+    $var real 64 7 v_arr_real[1] $end
    $upscope $end
-   $var longint 64 7 v_chandle [63:0] $end
-   $var logic 64 8 v_str32x2 [63:0] $end
+   $var longint 64 8 v_chandle [63:0] $end
+   $var logic 64 9 v_str32x2 [63:0] $end
    $attrbegin misc 07 "" 1 $end
-   $var int 32 9 v_enumed [31:0] $end
+   $var int 32 : v_enumed [31:0] $end
    $attrbegin misc 07 "" 1 $end
-   $var int 32 : v_enumed2 [31:0] $end
+   $var int 32 ; v_enumed2 [31:0] $end
    $attrbegin misc 07 "" 2 $end
-   $var logic 3 ; v_enumb [2:0] $end
-   $var logic 6 < v_enumb2_str [5:0] $end
+   $var logic 3 < v_enumb [2:0] $end
+   $var logic 6 = v_enumb2_str [5:0] $end
    $attrbegin array unpacked bounds -8589934592 $end
    $scope sv_array unpacked_array $end
-    $var logic 8 = unpacked_array[-2] [7:0] $end
-    $var logic 8 > unpacked_array[-1] [7:0] $end
-    $var logic 8 ? unpacked_array[0] [7:0] $end
+    $var logic 8 > unpacked_array[-2] [7:0] $end
+    $var logic 8 ? unpacked_array[-1] [7:0] $end
+    $var logic 8 @ unpacked_array[0] [7:0] $end
    $upscope $end
-   $var bit 1 @ LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
+   $var bit 1 A LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
    $scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end
-    $var parameter 32 A PARAM [31:0] $end
-   $upscope $end
-   $scope module p2 $end
     $var parameter 32 B PARAM [31:0] $end
    $upscope $end
-   $scope module p3 $end
+   $scope module p2 $end
     $var parameter 32 C PARAM [31:0] $end
    $upscope $end
+   $scope module p3 $end
+    $var parameter 32 D PARAM [31:0] $end
+   $upscope $end
   $upscope $end
  $upscope $end
 $enddefinitions $end
 #0
 $dumpvars
-b00000000000000000000000000000011 C
-b00000000000000000000000000000010 B
-b00000000000000000000000000000100 A
-0@
+b00000000000000000000000000000011 D
+b00000000000000000000000000000010 C
+b00000000000000000000000000000100 B
+0A
+b00000000 @
 b00000000 ?
 b00000000 >
-b00000000 =
-b000000 <
-b000 ;
+b000000 =
+b000 <
+b00000000000000000000000000000000 ;
 b00000000000000000000000000000000 :
-b00000000000000000000000000000000 9
-b0000000000000000000000000000000000000000000000000000000011111111 8
-b0000000000000000000000000000000000000000000000000000000000000000 7
+b0000000000000000000000000000000000000000000000000000000011111111 9
+b0000000000000000000000000000000000000000000000000000000000000000 8
+r0 7
 r0 6
 r0 5
-r0 4
+b00 4
 b00 3
 b00 2
 b00 1
-b00 0
+00
 0/
 0.
 0-
 0,
 0+
-0*
+b0000 *
 b0000 )
-b0000 (
+b00 (
 b00 '
-b00 &
-b0000 %
+b0000 &
+b00 %
 b00 $
 b00000000000000000000000000000000 #
 1"
@@ -128,134 +134,140 @@ $end
 1!
 b00000000000000000000000000000001 #
 b11 $
-b1111 %
-b11 &
+b11 %
+b1111 &
 b11 '
-b1111 (
+b11 (
 b1111 )
-b11 0
+b1111 *
 b11 1
 b11 2
 b11 3
-r0.1 4
-r0.2 5
-r0.3 6
-b0000000000000000000000000000000100000000000000000000000011111110 8
-b00000000000000000000000000000001 9
-b00000000000000000000000000000010 :
-b111 ;
+b11 4
+r0.1 5
+r0.2 6
+r0.3 7
+b0000000000000000000000000000000100000000000000000000000011111110 9
+b00000000000000000000000000000001 :
+b00000000000000000000000000000010 ;
+b111 <
 #15
 0!
 #20
 1!
-b110 ;
-b00000000000000000000000000000100 :
-b00000000000000000000000000000010 9
-b0000000000000000000000000000001000000000000000000000000011111101 8
-r0.6 6
-r0.4 5
-r0.2 4
+b110 <
+b00000000000000000000000000000100 ;
+b00000000000000000000000000000010 :
+b0000000000000000000000000000001000000000000000000000000011111101 9
+r0.6 7
+r0.4 6
+r0.2 5
+b00 4
 b00 3
 b00 2
 b00 1
-b00 0
+b0000 *
 b0000 )
-b0000 (
+b00 (
 b00 '
-b00 &
-b0000 %
+b0000 &
+b00 %
 b00 $
 b00000000000000000000000000000010 #
-b111111 <
+b111111 =
 #25
 0!
 #30
 1!
-b110110 <
+b110110 =
 b00000000000000000000000000000011 #
 b11 $
-b1111 %
-b11 &
+b11 %
+b1111 &
 b11 '
-b1111 (
+b11 (
 b1111 )
-b11 0
+b1111 *
 b11 1
 b11 2
 b11 3
-r0.3 4
-r0.6000000000000001 5
-r0.8999999999999999 6
-b0000000000000000000000000000001100000000000000000000000011111100 8
-b00000000000000000000000000000011 9
-b00000000000000000000000000000110 :
-b101 ;
+b11 4
+r0.3 5
+r0.6000000000000001 6
+r0.8999999999999999 7
+b0000000000000000000000000000001100000000000000000000000011111100 9
+b00000000000000000000000000000011 :
+b00000000000000000000000000000110 ;
+b101 <
 #35
 0!
 #40
 1!
-b100 ;
-b00000000000000000000000000001000 :
-b00000000000000000000000000000100 9
-b0000000000000000000000000000010000000000000000000000000011111011 8
-r1.2 6
-r0.8 5
-r0.4 4
+b100 <
+b00000000000000000000000000001000 ;
+b00000000000000000000000000000100 :
+b0000000000000000000000000000010000000000000000000000000011111011 9
+r1.2 7
+r0.8 6
+r0.4 5
+b00 4
 b00 3
 b00 2
 b00 1
-b00 0
+b0000 *
 b0000 )
-b0000 (
+b00 (
 b00 '
-b00 &
-b0000 %
+b0000 &
+b00 %
 b00 $
 b00000000000000000000000000000100 #
-b101101 <
+b101101 =
 #45
 0!
 #50
 1!
-b100100 <
+b100100 =
 b00000000000000000000000000000101 #
 b11 $
-b1111 %
-b11 &
+b11 %
+b1111 &
 b11 '
-b1111 (
+b11 (
 b1111 )
-b11 0
+b1111 *
 b11 1
 b11 2
 b11 3
-r0.5 4
-r1 5
-r1.5 6
-b0000000000000000000000000000010100000000000000000000000011111010 8
-b00000000000000000000000000000101 9
-b00000000000000000000000000001010 :
-b011 ;
+b11 4
+r0.5 5
+r1 6
+r1.5 7
+b0000000000000000000000000000010100000000000000000000000011111010 9
+b00000000000000000000000000000101 :
+b00000000000000000000000000001010 ;
+b011 <
 #55
 0!
 #60
 1!
-b010 ;
-b00000000000000000000000000001100 :
-b00000000000000000000000000000110 9
-b0000000000000000000000000000011000000000000000000000000011111001 8
-r1.8 6
-r1.2 5
-r0.6 4
+b010 <
+b00000000000000000000000000001100 ;
+b00000000000000000000000000000110 :
+b0000000000000000000000000000011000000000000000000000000011111001 9
+r1.8 7
+r1.2 6
+r0.6 5
+b00 4
 b00 3
 b00 2
 b00 1
-b00 0
+b0000 *
 b0000 )
-b0000 (
+b00 (
 b00 '
-b00 &
-b0000 %
+b0000 &
+b00 %
 b00 $
 b00000000000000000000000000000110 #
-b011011 <
+b011011 =
diff --git a/test_regress/t/t_trace_complex_default_cc_saif.out b/test_regress/t/t_trace_complex_default_cc_saif.out
index 7d002ed88..67bf81183 100644
--- a/test_regress/t/t_trace_complex_default_cc_saif.out
+++ b/test_regress/t/t_trace_complex_default_cc_saif.out
@@ -52,6 +52,8 @@
     (cyc\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
     (v_strp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
     (v_strp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_strp2\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_strp2\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
     (v_strp_strp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
     (v_strp_strp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
     (v_strp_strp\[2\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
@@ -68,20 +70,20 @@
     (v_arrp_strp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
     (v_arrp_strp\[2\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
     (v_arrp_strp\[3\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
-    (v_arru[1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
     (v_arru[2] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-    (v_arru_arru[3][1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-    (v_arru_arru[3][2] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-    (v_arru_arru[4][1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (v_arru[1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
     (v_arru_arru[4][2] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-    (v_arru_arrp[3]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
-    (v_arru_arrp[3]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_arru[4][1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (v_arru_arru[3][2] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (v_arru_arru[3][1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
     (v_arru_arrp[4]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
     (v_arru_arrp[4]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
-    (v_arru_strp[3]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
-    (v_arru_strp[3]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_arrp[3]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_arrp[3]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
     (v_arru_strp[4]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
     (v_arru_strp[4]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_strp[3]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_strp[3]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
     (v_real\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
     (v_real\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
     (v_real\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
diff --git a/test_regress/t/t_trace_complex_default_cc_vcd.out b/test_regress/t/t_trace_complex_default_cc_vcd.out
index dbfe9faa0..7b2db76cd 100644
--- a/test_regress/t/t_trace_complex_default_cc_vcd.out
+++ b/test_regress/t/t_trace_complex_default_cc_vcd.out
@@ -1,51 +1,52 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module top $end
-  $var wire 1 : clk $end
+  $var wire 1 ; clk $end
   $scope module $unit $end
    $var wire 1 " global_bit $end
   $upscope $end
   $scope module t $end
-   $var wire 1 : clk $end
+   $var wire 1 ; clk $end
    $var wire 32 # cyc [31:0] $end
    $var wire 2 $ v_strp [1:0] $end
-   $var wire 4 % v_strp_strp [3:0] $end
-   $var wire 2 & v_unip_strp [1:0] $end
-   $var wire 2 ' v_arrp [2:1] $end
-   $var wire 4 ( v_arrp_arrp [3:0] $end
-   $var wire 4 ) v_arrp_strp [3:0] $end
-   $var wire 1 ; v_arru[1] $end
+   $var wire 2 % v_strp2 [1:0] $end
+   $var wire 4 & v_strp_strp [3:0] $end
+   $var wire 2 ' v_unip_strp [1:0] $end
+   $var wire 2 ( v_arrp [2:1] $end
+   $var wire 4 ) v_arrp_arrp [3:0] $end
+   $var wire 4 * v_arrp_strp [3:0] $end
    $var wire 1 < v_arru[2] $end
-   $var wire 1 = v_arru_arru[3][1] $end
-   $var wire 1 > v_arru_arru[3][2] $end
+   $var wire 1 = v_arru[1] $end
+   $var wire 1 > v_arru_arru[4][2] $end
    $var wire 1 ? v_arru_arru[4][1] $end
-   $var wire 1 @ v_arru_arru[4][2] $end
-   $var wire 2 * v_arru_arrp[3] [2:1] $end
+   $var wire 1 @ v_arru_arru[3][2] $end
+   $var wire 1 A v_arru_arru[3][1] $end
    $var wire 2 + v_arru_arrp[4] [2:1] $end
-   $var wire 2 , v_arru_strp[3] [1:0] $end
+   $var wire 2 , v_arru_arrp[3] [2:1] $end
    $var wire 2 - v_arru_strp[4] [1:0] $end
-   $var real 64 . v_real $end
-   $var real 64 0 v_arr_real[0] $end
-   $var real 64 2 v_arr_real[1] $end
-   $var wire 64 A v_chandle [63:0] $end
-   $var wire 64 4 v_str32x2 [63:0] $end
-   $var wire 32 6 v_enumed [31:0] $end
-   $var wire 32 7 v_enumed2 [31:0] $end
-   $var wire 3 8 v_enumb [2:0] $end
-   $var wire 6 9 v_enumb2_str [5:0] $end
-   $var wire 8 C unpacked_array[-2] [7:0] $end
-   $var wire 8 D unpacked_array[-1] [7:0] $end
-   $var wire 8 E unpacked_array[0] [7:0] $end
-   $var wire 1 F LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
+   $var wire 2 . v_arru_strp[3] [1:0] $end
+   $var real 64 / v_real $end
+   $var real 64 1 v_arr_real[0] $end
+   $var real 64 3 v_arr_real[1] $end
+   $var wire 64 B v_chandle [63:0] $end
+   $var wire 64 5 v_str32x2 [63:0] $end
+   $var wire 32 7 v_enumed [31:0] $end
+   $var wire 32 8 v_enumed2 [31:0] $end
+   $var wire 3 9 v_enumb [2:0] $end
+   $var wire 6 : v_enumb2_str [5:0] $end
+   $var wire 8 D unpacked_array[-2] [7:0] $end
+   $var wire 8 E unpacked_array[-1] [7:0] $end
+   $var wire 8 F unpacked_array[0] [7:0] $end
+   $var wire 1 G LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
    $scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end
-    $var wire 32 G PARAM [31:0] $end
-   $upscope $end
-   $scope module p2 $end
     $var wire 32 H PARAM [31:0] $end
    $upscope $end
-   $scope module p3 $end
+   $scope module p2 $end
     $var wire 32 I PARAM [31:0] $end
    $upscope $end
+   $scope module p3 $end
+    $var wire 32 J PARAM [31:0] $end
+   $upscope $end
   $upscope $end
  $upscope $end
 $enddefinitions $end
@@ -55,170 +56,177 @@ $enddefinitions $end
 1"
 b00000000000000000000000000000000 #
 b00 $
-b0000 %
-b00 &
+b00 %
+b0000 &
 b00 '
-b0000 (
+b00 (
 b0000 )
-b00 *
+b0000 *
 b00 +
 b00 ,
 b00 -
-r0 .
-r0 0
-r0 2
-b0000000000000000000000000000000000000000000000000000000011111111 4
-b00000000000000000000000000000000 6
+b00 .
+r0 /
+r0 1
+r0 3
+b0000000000000000000000000000000000000000000000000000000011111111 5
 b00000000000000000000000000000000 7
-b000 8
-b000000 9
-0:
+b00000000000000000000000000000000 8
+b000 9
+b000000 :
 0;
 0<
 0=
 0>
 0?
 0@
-b0000000000000000000000000000000000000000000000000000000000000000 A
-b00000000 C
+0A
+b0000000000000000000000000000000000000000000000000000000000000000 B
 b00000000 D
 b00000000 E
-0F
-b00000000000000000000000000000100 G
-b00000000000000000000000000000010 H
-b00000000000000000000000000000011 I
+b00000000 F
+0G
+b00000000000000000000000000000100 H
+b00000000000000000000000000000010 I
+b00000000000000000000000000000011 J
 #10
 b00000000000000000000000000000001 #
 b11 $
-b1111 %
-b11 &
+b11 %
+b1111 &
 b11 '
-b1111 (
+b11 (
 b1111 )
-b11 *
+b1111 *
 b11 +
 b11 ,
 b11 -
-r0.1 .
-r0.2 0
-r0.3 2
-b0000000000000000000000000000000100000000000000000000000011111110 4
-b00000000000000000000000000000001 6
-b00000000000000000000000000000010 7
-b111 8
-1:
+b11 .
+r0.1 /
+r0.2 1
+r0.3 3
+b0000000000000000000000000000000100000000000000000000000011111110 5
+b00000000000000000000000000000001 7
+b00000000000000000000000000000010 8
+b111 9
+1;
 #15
-0:
+0;
 #20
 b00000000000000000000000000000010 #
 b00 $
-b0000 %
-b00 &
+b00 %
+b0000 &
 b00 '
-b0000 (
+b00 (
 b0000 )
-b00 *
+b0000 *
 b00 +
 b00 ,
 b00 -
-r0.2 .
-r0.4 0
-r0.6 2
-b0000000000000000000000000000001000000000000000000000000011111101 4
-b00000000000000000000000000000010 6
-b00000000000000000000000000000100 7
-b110 8
-b111111 9
-1:
+b00 .
+r0.2 /
+r0.4 1
+r0.6 3
+b0000000000000000000000000000001000000000000000000000000011111101 5
+b00000000000000000000000000000010 7
+b00000000000000000000000000000100 8
+b110 9
+b111111 :
+1;
 #25
-0:
+0;
 #30
 b00000000000000000000000000000011 #
 b11 $
-b1111 %
-b11 &
+b11 %
+b1111 &
 b11 '
-b1111 (
+b11 (
 b1111 )
-b11 *
+b1111 *
 b11 +
 b11 ,
 b11 -
-r0.3 .
-r0.6000000000000001 0
-r0.8999999999999999 2
-b0000000000000000000000000000001100000000000000000000000011111100 4
-b00000000000000000000000000000011 6
-b00000000000000000000000000000110 7
-b101 8
-b110110 9
-1:
+b11 .
+r0.3 /
+r0.6000000000000001 1
+r0.8999999999999999 3
+b0000000000000000000000000000001100000000000000000000000011111100 5
+b00000000000000000000000000000011 7
+b00000000000000000000000000000110 8
+b101 9
+b110110 :
+1;
 #35
-0:
+0;
 #40
 b00000000000000000000000000000100 #
 b00 $
-b0000 %
-b00 &
+b00 %
+b0000 &
 b00 '
-b0000 (
+b00 (
 b0000 )
-b00 *
+b0000 *
 b00 +
 b00 ,
 b00 -
-r0.4 .
-r0.8 0
-r1.2 2
-b0000000000000000000000000000010000000000000000000000000011111011 4
-b00000000000000000000000000000100 6
-b00000000000000000000000000001000 7
-b100 8
-b101101 9
-1:
+b00 .
+r0.4 /
+r0.8 1
+r1.2 3
+b0000000000000000000000000000010000000000000000000000000011111011 5
+b00000000000000000000000000000100 7
+b00000000000000000000000000001000 8
+b100 9
+b101101 :
+1;
 #45
-0:
+0;
 #50
 b00000000000000000000000000000101 #
 b11 $
-b1111 %
-b11 &
+b11 %
+b1111 &
 b11 '
-b1111 (
+b11 (
 b1111 )
-b11 *
+b1111 *
 b11 +
 b11 ,
 b11 -
-r0.5 .
-r1 0
-r1.5 2
-b0000000000000000000000000000010100000000000000000000000011111010 4
-b00000000000000000000000000000101 6
-b00000000000000000000000000001010 7
-b011 8
-b100100 9
-1:
+b11 .
+r0.5 /
+r1 1
+r1.5 3
+b0000000000000000000000000000010100000000000000000000000011111010 5
+b00000000000000000000000000000101 7
+b00000000000000000000000000001010 8
+b011 9
+b100100 :
+1;
 #55
-0:
+0;
 #60
 b00000000000000000000000000000110 #
 b00 $
-b0000 %
-b00 &
+b00 %
+b0000 &
 b00 '
-b0000 (
+b00 (
 b0000 )
-b00 *
+b0000 *
 b00 +
 b00 ,
 b00 -
-r0.6 .
-r1.2 0
-r1.8 2
-b0000000000000000000000000000011000000000000000000000000011111001 4
-b00000000000000000000000000000110 6
-b00000000000000000000000000001100 7
-b010 8
-b011011 9
-1:
+b00 .
+r0.6 /
+r1.2 1
+r1.8 3
+b0000000000000000000000000000011000000000000000000000000011111001 5
+b00000000000000000000000000000110 7
+b00000000000000000000000000001100 8
+b010 9
+b011011 :
+1;
diff --git a/test_regress/t/t_trace_complex_default_sc_fst.out b/test_regress/t/t_trace_complex_default_sc_fst.out
index 862a3da01..0069d6a7f 100644
--- a/test_regress/t/t_trace_complex_default_sc_fst.out
+++ b/test_regress/t/t_trace_complex_default_sc_fst.out
@@ -1,5 +1,9 @@
 $date
-Sat Mar 14 09:16:46 2026
+<<<<<<< HEAD
+Tue Apr 14 15:20:39 2026
+=======
+Tue Mar 31 17:14:34 2026
+>>>>>>> 8895f96e4 (CR)
 
 $end
 $version
@@ -18,106 +22,108 @@ $end
    $var wire 1 " clk $end
    $var integer 32 # cyc [31:0] $end
    $var bit 2 $ v_strp [1:0] $end
-   $var bit 4 % v_strp_strp [3:0] $end
-   $var bit 2 & v_unip_strp [1:0] $end
-   $var bit 2 ' v_arrp [2:1] $end
-   $var bit 4 ( v_arrp_arrp [3:0] $end
-   $var bit 4 ) v_arrp_strp [3:0] $end
+   $var bit 2 % v_strp2 [1:0] $end
+   $var bit 4 & v_strp_strp [3:0] $end
+   $var bit 2 ' v_unip_strp [1:0] $end
+   $var bit 2 ( v_arrp [2:1] $end
+   $var bit 4 ) v_arrp_arrp [3:0] $end
+   $var bit 4 * v_arrp_strp [3:0] $end
    $attrbegin array unpacked bounds 8589934593 $end
    $scope sv_array v_arru $end
-    $var bit 1 * v_arru[2] $end
-    $var bit 1 + v_arru[1] $end
+    $var bit 1 + v_arru[2] $end
+    $var bit 1 , v_arru[1] $end
    $upscope $end
    $attrbegin array unpacked bounds 17179869187 $end
    $scope sv_array v_arru_arru $end
     $attrbegin array unpacked bounds 8589934593 $end
     $scope sv_array [4] $end
-     $var bit 1 , v_arru_arru[4][2] $end
-     $var bit 1 - v_arru_arru[4][1] $end
+     $var bit 1 - v_arru_arru[4][2] $end
+     $var bit 1 . v_arru_arru[4][1] $end
     $upscope $end
     $attrbegin array unpacked bounds 8589934593 $end
     $scope sv_array [3] $end
-     $var bit 1 . v_arru_arru[3][2] $end
-     $var bit 1 / v_arru_arru[3][1] $end
+     $var bit 1 / v_arru_arru[3][2] $end
+     $var bit 1 0 v_arru_arru[3][1] $end
     $upscope $end
    $upscope $end
    $attrbegin array unpacked bounds 17179869187 $end
    $scope sv_array v_arru_arrp $end
-    $var bit 2 0 v_arru_arrp[4] [2:1] $end
-    $var bit 2 1 v_arru_arrp[3] [2:1] $end
+    $var bit 2 1 v_arru_arrp[4] [2:1] $end
+    $var bit 2 2 v_arru_arrp[3] [2:1] $end
    $upscope $end
    $attrbegin array unpacked bounds 17179869187 $end
    $scope sv_array v_arru_strp $end
-    $var bit 2 2 v_arru_strp[4] [1:0] $end
-    $var bit 2 3 v_arru_strp[3] [1:0] $end
+    $var bit 2 3 v_arru_strp[4] [1:0] $end
+    $var bit 2 4 v_arru_strp[3] [1:0] $end
    $upscope $end
-   $var real 64 4 v_real $end
+   $var real 64 5 v_real $end
    $attrbegin array unpacked bounds 1 $end
    $scope sv_array v_arr_real $end
-    $var real 64 5 v_arr_real[0] $end
-    $var real 64 6 v_arr_real[1] $end
+    $var real 64 6 v_arr_real[0] $end
+    $var real 64 7 v_arr_real[1] $end
    $upscope $end
-   $var longint 64 7 v_chandle [63:0] $end
-   $var logic 64 8 v_str32x2 [63:0] $end
+   $var longint 64 8 v_chandle [63:0] $end
+   $var logic 64 9 v_str32x2 [63:0] $end
    $attrbegin misc 07 "" 1 $end
-   $var int 32 9 v_enumed [31:0] $end
+   $var int 32 : v_enumed [31:0] $end
    $attrbegin misc 07 "" 1 $end
-   $var int 32 : v_enumed2 [31:0] $end
+   $var int 32 ; v_enumed2 [31:0] $end
    $attrbegin misc 07 "" 2 $end
-   $var logic 3 ; v_enumb [2:0] $end
-   $var logic 6 < v_enumb2_str [5:0] $end
+   $var logic 3 < v_enumb [2:0] $end
+   $var logic 6 = v_enumb2_str [5:0] $end
    $attrbegin array unpacked bounds -8589934592 $end
    $scope sv_array unpacked_array $end
-    $var logic 8 = unpacked_array[-2] [7:0] $end
-    $var logic 8 > unpacked_array[-1] [7:0] $end
-    $var logic 8 ? unpacked_array[0] [7:0] $end
+    $var logic 8 > unpacked_array[-2] [7:0] $end
+    $var logic 8 ? unpacked_array[-1] [7:0] $end
+    $var logic 8 @ unpacked_array[0] [7:0] $end
    $upscope $end
-   $var bit 1 @ LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
+   $var bit 1 A LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
    $scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end
-    $var parameter 32 A PARAM [31:0] $end
-   $upscope $end
-   $scope module p2 $end
     $var parameter 32 B PARAM [31:0] $end
    $upscope $end
-   $scope module p3 $end
+   $scope module p2 $end
     $var parameter 32 C PARAM [31:0] $end
    $upscope $end
+   $scope module p3 $end
+    $var parameter 32 D PARAM [31:0] $end
+   $upscope $end
   $upscope $end
  $upscope $end
 $enddefinitions $end
 #0
 $dumpvars
-b00000000000000000000000000000011 C
-b00000000000000000000000000000010 B
-b00000000000000000000000000000100 A
-0@
+b00000000000000000000000000000011 D
+b00000000000000000000000000000010 C
+b00000000000000000000000000000100 B
+0A
+b00000000 @
 b00000000 ?
 b00000000 >
-b00000000 =
-b000000 <
-b000 ;
+b000000 =
+b000 <
+b00000000000000000000000000000000 ;
 b00000000000000000000000000000000 :
-b00000000000000000000000000000000 9
-b0000000000000000000000000000000000000000000000000000000011111111 8
-b0000000000000000000000000000000000000000000000000000000000000000 7
+b0000000000000000000000000000000000000000000000000000000011111111 9
+b0000000000000000000000000000000000000000000000000000000000000000 8
+r0 7
 r0 6
 r0 5
-r0 4
+b00 4
 b00 3
 b00 2
 b00 1
-b00 0
+00
 0/
 0.
 0-
 0,
 0+
-0*
+b0000 *
 b0000 )
-b0000 (
+b00 (
 b00 '
-b00 &
-b0000 %
+b0000 &
+b00 %
 b00 $
 b00000000000000000000000000000000 #
 0"
@@ -127,135 +133,141 @@ $end
 1"
 b00000000000000000000000000000001 #
 b11 $
-b1111 %
-b11 &
+b11 %
+b1111 &
 b11 '
-b1111 (
+b11 (
 b1111 )
-b11 0
+b1111 *
 b11 1
 b11 2
 b11 3
-r0.1 4
-r0.2 5
-r0.3 6
-b0000000000000000000000000000000100000000000000000000000011111110 8
-b00000000000000000000000000000001 9
-b00000000000000000000000000000010 :
-b111 ;
+b11 4
+r0.1 5
+r0.2 6
+r0.3 7
+b0000000000000000000000000000000100000000000000000000000011111110 9
+b00000000000000000000000000000001 :
+b00000000000000000000000000000010 ;
+b111 <
 #15
 0"
 #20
 1"
-b110 ;
-b00000000000000000000000000000100 :
-b00000000000000000000000000000010 9
-b0000000000000000000000000000001000000000000000000000000011111101 8
-r0.6 6
-r0.4 5
-r0.2 4
+b110 <
+b00000000000000000000000000000100 ;
+b00000000000000000000000000000010 :
+b0000000000000000000000000000001000000000000000000000000011111101 9
+r0.6 7
+r0.4 6
+r0.2 5
+b00 4
 b00 3
 b00 2
 b00 1
-b00 0
+b0000 *
 b0000 )
-b0000 (
+b00 (
 b00 '
-b00 &
-b0000 %
+b0000 &
+b00 %
 b00 $
 b00000000000000000000000000000010 #
-b111111 <
+b111111 =
 #25
 0"
 #30
 1"
-b110110 <
+b110110 =
 b00000000000000000000000000000011 #
 b11 $
-b1111 %
-b11 &
+b11 %
+b1111 &
 b11 '
-b1111 (
+b11 (
 b1111 )
-b11 0
+b1111 *
 b11 1
 b11 2
 b11 3
-r0.3 4
-r0.6000000000000001 5
-r0.8999999999999999 6
-b0000000000000000000000000000001100000000000000000000000011111100 8
-b00000000000000000000000000000011 9
-b00000000000000000000000000000110 :
-b101 ;
+b11 4
+r0.3 5
+r0.6000000000000001 6
+r0.8999999999999999 7
+b0000000000000000000000000000001100000000000000000000000011111100 9
+b00000000000000000000000000000011 :
+b00000000000000000000000000000110 ;
+b101 <
 #35
 0"
 #40
 1"
-b100 ;
-b00000000000000000000000000001000 :
-b00000000000000000000000000000100 9
-b0000000000000000000000000000010000000000000000000000000011111011 8
-r1.2 6
-r0.8 5
-r0.4 4
+b100 <
+b00000000000000000000000000001000 ;
+b00000000000000000000000000000100 :
+b0000000000000000000000000000010000000000000000000000000011111011 9
+r1.2 7
+r0.8 6
+r0.4 5
+b00 4
 b00 3
 b00 2
 b00 1
-b00 0
+b0000 *
 b0000 )
-b0000 (
+b00 (
 b00 '
-b00 &
-b0000 %
+b0000 &
+b00 %
 b00 $
 b00000000000000000000000000000100 #
-b101101 <
+b101101 =
 #45
 0"
 #50
 1"
-b100100 <
+b100100 =
 b00000000000000000000000000000101 #
 b11 $
-b1111 %
-b11 &
+b11 %
+b1111 &
 b11 '
-b1111 (
+b11 (
 b1111 )
-b11 0
+b1111 *
 b11 1
 b11 2
 b11 3
-r0.5 4
-r1 5
-r1.5 6
-b0000000000000000000000000000010100000000000000000000000011111010 8
-b00000000000000000000000000000101 9
-b00000000000000000000000000001010 :
-b011 ;
+b11 4
+r0.5 5
+r1 6
+r1.5 7
+b0000000000000000000000000000010100000000000000000000000011111010 9
+b00000000000000000000000000000101 :
+b00000000000000000000000000001010 ;
+b011 <
 #55
 0"
 #60
 1"
-b010 ;
-b00000000000000000000000000001100 :
-b00000000000000000000000000000110 9
-b0000000000000000000000000000011000000000000000000000000011111001 8
-r1.8 6
-r1.2 5
-r0.6 4
+b010 <
+b00000000000000000000000000001100 ;
+b00000000000000000000000000000110 :
+b0000000000000000000000000000011000000000000000000000000011111001 9
+r1.8 7
+r1.2 6
+r0.6 5
+b00 4
 b00 3
 b00 2
 b00 1
-b00 0
+b0000 *
 b0000 )
-b0000 (
+b00 (
 b00 '
-b00 &
-b0000 %
+b0000 &
+b00 %
 b00 $
 b00000000000000000000000000000110 #
-b011011 <
+b011011 =
 #64
diff --git a/test_regress/t/t_trace_complex_default_sc_vcd.out b/test_regress/t/t_trace_complex_default_sc_vcd.out
index c894c8109..363053c5c 100644
--- a/test_regress/t/t_trace_complex_default_sc_vcd.out
+++ b/test_regress/t/t_trace_complex_default_sc_vcd.out
@@ -5,46 +5,47 @@ $timescale 1ps $end
    $var wire 1 " global_bit $end
   $upscope $end
   $scope module t $end
-   $var wire 1 : clk $end
+   $var wire 1 ; clk $end
    $var wire 32 # cyc [31:0] $end
    $var wire 2 $ v_strp [1:0] $end
-   $var wire 4 % v_strp_strp [3:0] $end
-   $var wire 2 & v_unip_strp [1:0] $end
-   $var wire 2 ' v_arrp [2:1] $end
-   $var wire 4 ( v_arrp_arrp [3:0] $end
-   $var wire 4 ) v_arrp_strp [3:0] $end
-   $var wire 1 ; v_arru[2] $end
-   $var wire 1 < v_arru[1] $end
-   $var wire 1 = v_arru_arru[4][2] $end
-   $var wire 1 > v_arru_arru[4][1] $end
-   $var wire 1 ? v_arru_arru[3][2] $end
-   $var wire 1 @ v_arru_arru[3][1] $end
-   $var wire 2 * v_arru_arrp[4] [2:1] $end
-   $var wire 2 + v_arru_arrp[3] [2:1] $end
-   $var wire 2 , v_arru_strp[4] [1:0] $end
-   $var wire 2 - v_arru_strp[3] [1:0] $end
-   $var real 64 . v_real $end
-   $var real 64 0 v_arr_real[0] $end
-   $var real 64 2 v_arr_real[1] $end
-   $var wire 64 A v_chandle [63:0] $end
-   $var wire 64 4 v_str32x2 [63:0] $end
-   $var wire 32 6 v_enumed [31:0] $end
-   $var wire 32 7 v_enumed2 [31:0] $end
-   $var wire 3 8 v_enumb [2:0] $end
-   $var wire 6 9 v_enumb2_str [5:0] $end
-   $var wire 8 C unpacked_array[-2] [7:0] $end
-   $var wire 8 D unpacked_array[-1] [7:0] $end
-   $var wire 8 E unpacked_array[0] [7:0] $end
-   $var wire 1 F LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
+   $var wire 2 % v_strp2 [1:0] $end
+   $var wire 4 & v_strp_strp [3:0] $end
+   $var wire 2 ' v_unip_strp [1:0] $end
+   $var wire 2 ( v_arrp [2:1] $end
+   $var wire 4 ) v_arrp_arrp [3:0] $end
+   $var wire 4 * v_arrp_strp [3:0] $end
+   $var wire 1 < v_arru[2] $end
+   $var wire 1 = v_arru[1] $end
+   $var wire 1 > v_arru_arru[4][2] $end
+   $var wire 1 ? v_arru_arru[4][1] $end
+   $var wire 1 @ v_arru_arru[3][2] $end
+   $var wire 1 A v_arru_arru[3][1] $end
+   $var wire 2 + v_arru_arrp[4] [2:1] $end
+   $var wire 2 , v_arru_arrp[3] [2:1] $end
+   $var wire 2 - v_arru_strp[4] [1:0] $end
+   $var wire 2 . v_arru_strp[3] [1:0] $end
+   $var real 64 / v_real $end
+   $var real 64 1 v_arr_real[0] $end
+   $var real 64 3 v_arr_real[1] $end
+   $var wire 64 B v_chandle [63:0] $end
+   $var wire 64 5 v_str32x2 [63:0] $end
+   $var wire 32 7 v_enumed [31:0] $end
+   $var wire 32 8 v_enumed2 [31:0] $end
+   $var wire 3 9 v_enumb [2:0] $end
+   $var wire 6 : v_enumb2_str [5:0] $end
+   $var wire 8 D unpacked_array[-2] [7:0] $end
+   $var wire 8 E unpacked_array[-1] [7:0] $end
+   $var wire 8 F unpacked_array[0] [7:0] $end
+   $var wire 1 G LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
    $scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end
-    $var wire 32 G PARAM [31:0] $end
-   $upscope $end
-   $scope module p2 $end
     $var wire 32 H PARAM [31:0] $end
    $upscope $end
-   $scope module p3 $end
+   $scope module p2 $end
     $var wire 32 I PARAM [31:0] $end
    $upscope $end
+   $scope module p3 $end
+    $var wire 32 J PARAM [31:0] $end
+   $upscope $end
   $upscope $end
  $upscope $end
 $enddefinitions $end
@@ -54,171 +55,178 @@ $enddefinitions $end
 1"
 b00000000000000000000000000000000 #
 b00 $
-b0000 %
-b00 &
+b00 %
+b0000 &
 b00 '
-b0000 (
+b00 (
 b0000 )
-b00 *
+b0000 *
 b00 +
 b00 ,
 b00 -
-r0 .
-r0 0
-r0 2
-b0000000000000000000000000000000000000000000000000000000011111111 4
-b00000000000000000000000000000000 6
+b00 .
+r0 /
+r0 1
+r0 3
+b0000000000000000000000000000000000000000000000000000000011111111 5
 b00000000000000000000000000000000 7
-b000 8
-b000000 9
-0:
+b00000000000000000000000000000000 8
+b000 9
+b000000 :
 0;
 0<
 0=
 0>
 0?
 0@
-b0000000000000000000000000000000000000000000000000000000000000000 A
-b00000000 C
+0A
+b0000000000000000000000000000000000000000000000000000000000000000 B
 b00000000 D
 b00000000 E
-0F
-b00000000000000000000000000000100 G
-b00000000000000000000000000000010 H
-b00000000000000000000000000000011 I
+b00000000 F
+0G
+b00000000000000000000000000000100 H
+b00000000000000000000000000000010 I
+b00000000000000000000000000000011 J
 #10
 b00000000000000000000000000000001 #
 b11 $
-b1111 %
-b11 &
+b11 %
+b1111 &
 b11 '
-b1111 (
+b11 (
 b1111 )
-b11 *
+b1111 *
 b11 +
 b11 ,
 b11 -
-r0.1 .
-r0.2 0
-r0.3 2
-b0000000000000000000000000000000100000000000000000000000011111110 4
-b00000000000000000000000000000001 6
-b00000000000000000000000000000010 7
-b111 8
-1:
+b11 .
+r0.1 /
+r0.2 1
+r0.3 3
+b0000000000000000000000000000000100000000000000000000000011111110 5
+b00000000000000000000000000000001 7
+b00000000000000000000000000000010 8
+b111 9
+1;
 #15
-0:
+0;
 #20
 b00000000000000000000000000000010 #
 b00 $
-b0000 %
-b00 &
+b00 %
+b0000 &
 b00 '
-b0000 (
+b00 (
 b0000 )
-b00 *
+b0000 *
 b00 +
 b00 ,
 b00 -
-r0.2 .
-r0.4 0
-r0.6 2
-b0000000000000000000000000000001000000000000000000000000011111101 4
-b00000000000000000000000000000010 6
-b00000000000000000000000000000100 7
-b110 8
-b111111 9
-1:
+b00 .
+r0.2 /
+r0.4 1
+r0.6 3
+b0000000000000000000000000000001000000000000000000000000011111101 5
+b00000000000000000000000000000010 7
+b00000000000000000000000000000100 8
+b110 9
+b111111 :
+1;
 #25
-0:
+0;
 #30
 b00000000000000000000000000000011 #
 b11 $
-b1111 %
-b11 &
+b11 %
+b1111 &
 b11 '
-b1111 (
+b11 (
 b1111 )
-b11 *
+b1111 *
 b11 +
 b11 ,
 b11 -
-r0.3 .
-r0.6000000000000001 0
-r0.8999999999999999 2
-b0000000000000000000000000000001100000000000000000000000011111100 4
-b00000000000000000000000000000011 6
-b00000000000000000000000000000110 7
-b101 8
-b110110 9
-1:
+b11 .
+r0.3 /
+r0.6000000000000001 1
+r0.8999999999999999 3
+b0000000000000000000000000000001100000000000000000000000011111100 5
+b00000000000000000000000000000011 7
+b00000000000000000000000000000110 8
+b101 9
+b110110 :
+1;
 #35
-0:
+0;
 #40
 b00000000000000000000000000000100 #
 b00 $
-b0000 %
-b00 &
+b00 %
+b0000 &
 b00 '
-b0000 (
+b00 (
 b0000 )
-b00 *
+b0000 *
 b00 +
 b00 ,
 b00 -
-r0.4 .
-r0.8 0
-r1.2 2
-b0000000000000000000000000000010000000000000000000000000011111011 4
-b00000000000000000000000000000100 6
-b00000000000000000000000000001000 7
-b100 8
-b101101 9
-1:
+b00 .
+r0.4 /
+r0.8 1
+r1.2 3
+b0000000000000000000000000000010000000000000000000000000011111011 5
+b00000000000000000000000000000100 7
+b00000000000000000000000000001000 8
+b100 9
+b101101 :
+1;
 #45
-0:
+0;
 #50
 b00000000000000000000000000000101 #
 b11 $
-b1111 %
-b11 &
+b11 %
+b1111 &
 b11 '
-b1111 (
+b11 (
 b1111 )
-b11 *
+b1111 *
 b11 +
 b11 ,
 b11 -
-r0.5 .
-r1 0
-r1.5 2
-b0000000000000000000000000000010100000000000000000000000011111010 4
-b00000000000000000000000000000101 6
-b00000000000000000000000000001010 7
-b011 8
-b100100 9
-1:
+b11 .
+r0.5 /
+r1 1
+r1.5 3
+b0000000000000000000000000000010100000000000000000000000011111010 5
+b00000000000000000000000000000101 7
+b00000000000000000000000000001010 8
+b011 9
+b100100 :
+1;
 #55
-0:
+0;
 #60
 b00000000000000000000000000000110 #
 b00 $
-b0000 %
-b00 &
+b00 %
+b0000 &
 b00 '
-b0000 (
+b00 (
 b0000 )
-b00 *
+b0000 *
 b00 +
 b00 ,
 b00 -
-r0.6 .
-r1.2 0
-r1.8 2
-b0000000000000000000000000000011000000000000000000000000011111001 4
-b00000000000000000000000000000110 6
-b00000000000000000000000000001100 7
-b010 8
-b011011 9
-1:
+b00 .
+r0.6 /
+r1.2 1
+r1.8 3
+b0000000000000000000000000000011000000000000000000000000011111001 5
+b00000000000000000000000000000110 7
+b00000000000000000000000000001100 8
+b010 9
+b011011 :
+1;
 #64
diff --git a/test_regress/t/t_trace_complex_params_cc_fst.out b/test_regress/t/t_trace_complex_params_cc_fst.out
index c1658ae63..3f10e2e50 100644
--- a/test_regress/t/t_trace_complex_params_cc_fst.out
+++ b/test_regress/t/t_trace_complex_params_cc_fst.out
@@ -1,5 +1,9 @@
 $date
-Sat Mar 14 09:16:42 2026
+<<<<<<< HEAD
+Tue Apr 14 15:20:39 2026
+=======
+Tue Mar 31 17:14:36 2026
+>>>>>>> 8895f96e4 (CR)
 
 $end
 $version
@@ -19,106 +23,108 @@ $end
    $var wire 1 ! clk $end
    $var integer 32 # cyc [31:0] $end
    $var bit 2 $ v_strp [1:0] $end
-   $var bit 4 % v_strp_strp [3:0] $end
-   $var bit 2 & v_unip_strp [1:0] $end
-   $var bit 2 ' v_arrp [2:1] $end
-   $var bit 4 ( v_arrp_arrp [3:0] $end
-   $var bit 4 ) v_arrp_strp [3:0] $end
+   $var bit 2 % v_strp2 [1:0] $end
+   $var bit 4 & v_strp_strp [3:0] $end
+   $var bit 2 ' v_unip_strp [1:0] $end
+   $var bit 2 ( v_arrp [2:1] $end
+   $var bit 4 ) v_arrp_arrp [3:0] $end
+   $var bit 4 * v_arrp_strp [3:0] $end
    $attrbegin array unpacked bounds 8589934593 $end
    $scope sv_array v_arru $end
-    $var bit 1 * v_arru[2] $end
-    $var bit 1 + v_arru[1] $end
+    $var bit 1 + v_arru[2] $end
+    $var bit 1 , v_arru[1] $end
    $upscope $end
    $attrbegin array unpacked bounds 17179869187 $end
    $scope sv_array v_arru_arru $end
     $attrbegin array unpacked bounds 8589934593 $end
     $scope sv_array [4] $end
-     $var bit 1 , v_arru_arru[4][2] $end
-     $var bit 1 - v_arru_arru[4][1] $end
+     $var bit 1 - v_arru_arru[4][2] $end
+     $var bit 1 . v_arru_arru[4][1] $end
     $upscope $end
     $attrbegin array unpacked bounds 8589934593 $end
     $scope sv_array [3] $end
-     $var bit 1 . v_arru_arru[3][2] $end
-     $var bit 1 / v_arru_arru[3][1] $end
+     $var bit 1 / v_arru_arru[3][2] $end
+     $var bit 1 0 v_arru_arru[3][1] $end
     $upscope $end
    $upscope $end
    $attrbegin array unpacked bounds 17179869187 $end
    $scope sv_array v_arru_arrp $end
-    $var bit 2 0 v_arru_arrp[4] [2:1] $end
-    $var bit 2 1 v_arru_arrp[3] [2:1] $end
+    $var bit 2 1 v_arru_arrp[4] [2:1] $end
+    $var bit 2 2 v_arru_arrp[3] [2:1] $end
    $upscope $end
    $attrbegin array unpacked bounds 17179869187 $end
    $scope sv_array v_arru_strp $end
-    $var bit 2 2 v_arru_strp[4] [1:0] $end
-    $var bit 2 3 v_arru_strp[3] [1:0] $end
+    $var bit 2 3 v_arru_strp[4] [1:0] $end
+    $var bit 2 4 v_arru_strp[3] [1:0] $end
    $upscope $end
-   $var real 64 4 v_real $end
+   $var real 64 5 v_real $end
    $attrbegin array unpacked bounds 1 $end
    $scope sv_array v_arr_real $end
-    $var real 64 5 v_arr_real[0] $end
-    $var real 64 6 v_arr_real[1] $end
+    $var real 64 6 v_arr_real[0] $end
+    $var real 64 7 v_arr_real[1] $end
    $upscope $end
-   $var longint 64 7 v_chandle [63:0] $end
-   $var logic 64 8 v_str32x2 [63:0] $end
+   $var longint 64 8 v_chandle [63:0] $end
+   $var logic 64 9 v_str32x2 [63:0] $end
    $attrbegin misc 07 "" 1 $end
-   $var int 32 9 v_enumed [31:0] $end
+   $var int 32 : v_enumed [31:0] $end
    $attrbegin misc 07 "" 1 $end
-   $var int 32 : v_enumed2 [31:0] $end
+   $var int 32 ; v_enumed2 [31:0] $end
    $attrbegin misc 07 "" 2 $end
-   $var logic 3 ; v_enumb [2:0] $end
-   $var logic 6 < v_enumb2_str [5:0] $end
+   $var logic 3 < v_enumb [2:0] $end
+   $var logic 6 = v_enumb2_str [5:0] $end
    $attrbegin array unpacked bounds -8589934592 $end
    $scope sv_array unpacked_array $end
-    $var logic 8 = unpacked_array[-2] [7:0] $end
-    $var logic 8 > unpacked_array[-1] [7:0] $end
-    $var logic 8 ? unpacked_array[0] [7:0] $end
+    $var logic 8 > unpacked_array[-2] [7:0] $end
+    $var logic 8 ? unpacked_array[-1] [7:0] $end
+    $var logic 8 @ unpacked_array[0] [7:0] $end
    $upscope $end
-   $var bit 1 @ LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
+   $var bit 1 A LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
    $scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end
-    $var parameter 32 A PARAM [31:0] $end
-   $upscope $end
-   $scope module p2 $end
     $var parameter 32 B PARAM [31:0] $end
    $upscope $end
-   $scope module p3 $end
+   $scope module p2 $end
     $var parameter 32 C PARAM [31:0] $end
    $upscope $end
+   $scope module p3 $end
+    $var parameter 32 D PARAM [31:0] $end
+   $upscope $end
   $upscope $end
  $upscope $end
 $enddefinitions $end
 #0
 $dumpvars
-b00000000000000000000000000000011 C
-b00000000000000000000000000000010 B
-b00000000000000000000000000000100 A
-0@
+b00000000000000000000000000000011 D
+b00000000000000000000000000000010 C
+b00000000000000000000000000000100 B
+0A
+b00000000 @
 b00000000 ?
 b00000000 >
-b00000000 =
-b000000 <
-b000 ;
+b000000 =
+b000 <
+b00000000000000000000000000000000 ;
 b00000000000000000000000000000000 :
-b00000000000000000000000000000000 9
-b0000000000000000000000000000000000000000000000000000000011111111 8
-b0000000000000000000000000000000000000000000000000000000000000000 7
+b0000000000000000000000000000000000000000000000000000000011111111 9
+b0000000000000000000000000000000000000000000000000000000000000000 8
+r0 7
 r0 6
 r0 5
-r0 4
+b00 4
 b00 3
 b00 2
 b00 1
-b00 0
+00
 0/
 0.
 0-
 0,
 0+
-0*
+b0000 *
 b0000 )
-b0000 (
+b00 (
 b00 '
-b00 &
-b0000 %
+b0000 &
+b00 %
 b00 $
 b00000000000000000000000000000000 #
 1"
@@ -128,134 +134,140 @@ $end
 1!
 b00000000000000000000000000000001 #
 b11 $
-b1111 %
-b11 &
+b11 %
+b1111 &
 b11 '
-b1111 (
+b11 (
 b1111 )
-b11 0
+b1111 *
 b11 1
 b11 2
 b11 3
-r0.1 4
-r0.2 5
-r0.3 6
-b0000000000000000000000000000000100000000000000000000000011111110 8
-b00000000000000000000000000000001 9
-b00000000000000000000000000000010 :
-b111 ;
+b11 4
+r0.1 5
+r0.2 6
+r0.3 7
+b0000000000000000000000000000000100000000000000000000000011111110 9
+b00000000000000000000000000000001 :
+b00000000000000000000000000000010 ;
+b111 <
 #15
 0!
 #20
 1!
-b110 ;
-b00000000000000000000000000000100 :
-b00000000000000000000000000000010 9
-b0000000000000000000000000000001000000000000000000000000011111101 8
-r0.6 6
-r0.4 5
-r0.2 4
+b110 <
+b00000000000000000000000000000100 ;
+b00000000000000000000000000000010 :
+b0000000000000000000000000000001000000000000000000000000011111101 9
+r0.6 7
+r0.4 6
+r0.2 5
+b00 4
 b00 3
 b00 2
 b00 1
-b00 0
+b0000 *
 b0000 )
-b0000 (
+b00 (
 b00 '
-b00 &
-b0000 %
+b0000 &
+b00 %
 b00 $
 b00000000000000000000000000000010 #
-b111111 <
+b111111 =
 #25
 0!
 #30
 1!
-b110110 <
+b110110 =
 b00000000000000000000000000000011 #
 b11 $
-b1111 %
-b11 &
+b11 %
+b1111 &
 b11 '
-b1111 (
+b11 (
 b1111 )
-b11 0
+b1111 *
 b11 1
 b11 2
 b11 3
-r0.3 4
-r0.6000000000000001 5
-r0.8999999999999999 6
-b0000000000000000000000000000001100000000000000000000000011111100 8
-b00000000000000000000000000000011 9
-b00000000000000000000000000000110 :
-b101 ;
+b11 4
+r0.3 5
+r0.6000000000000001 6
+r0.8999999999999999 7
+b0000000000000000000000000000001100000000000000000000000011111100 9
+b00000000000000000000000000000011 :
+b00000000000000000000000000000110 ;
+b101 <
 #35
 0!
 #40
 1!
-b100 ;
-b00000000000000000000000000001000 :
-b00000000000000000000000000000100 9
-b0000000000000000000000000000010000000000000000000000000011111011 8
-r1.2 6
-r0.8 5
-r0.4 4
+b100 <
+b00000000000000000000000000001000 ;
+b00000000000000000000000000000100 :
+b0000000000000000000000000000010000000000000000000000000011111011 9
+r1.2 7
+r0.8 6
+r0.4 5
+b00 4
 b00 3
 b00 2
 b00 1
-b00 0
+b0000 *
 b0000 )
-b0000 (
+b00 (
 b00 '
-b00 &
-b0000 %
+b0000 &
+b00 %
 b00 $
 b00000000000000000000000000000100 #
-b101101 <
+b101101 =
 #45
 0!
 #50
 1!
-b100100 <
+b100100 =
 b00000000000000000000000000000101 #
 b11 $
-b1111 %
-b11 &
+b11 %
+b1111 &
 b11 '
-b1111 (
+b11 (
 b1111 )
-b11 0
+b1111 *
 b11 1
 b11 2
 b11 3
-r0.5 4
-r1 5
-r1.5 6
-b0000000000000000000000000000010100000000000000000000000011111010 8
-b00000000000000000000000000000101 9
-b00000000000000000000000000001010 :
-b011 ;
+b11 4
+r0.5 5
+r1 6
+r1.5 7
+b0000000000000000000000000000010100000000000000000000000011111010 9
+b00000000000000000000000000000101 :
+b00000000000000000000000000001010 ;
+b011 <
 #55
 0!
 #60
 1!
-b010 ;
-b00000000000000000000000000001100 :
-b00000000000000000000000000000110 9
-b0000000000000000000000000000011000000000000000000000000011111001 8
-r1.8 6
-r1.2 5
-r0.6 4
+b010 <
+b00000000000000000000000000001100 ;
+b00000000000000000000000000000110 :
+b0000000000000000000000000000011000000000000000000000000011111001 9
+r1.8 7
+r1.2 6
+r0.6 5
+b00 4
 b00 3
 b00 2
 b00 1
-b00 0
+b0000 *
 b0000 )
-b0000 (
+b00 (
 b00 '
-b00 &
-b0000 %
+b0000 &
+b00 %
 b00 $
 b00000000000000000000000000000110 #
-b011011 <
+b011011 =
diff --git a/test_regress/t/t_trace_complex_params_cc_saif.out b/test_regress/t/t_trace_complex_params_cc_saif.out
index 7d002ed88..67bf81183 100644
--- a/test_regress/t/t_trace_complex_params_cc_saif.out
+++ b/test_regress/t/t_trace_complex_params_cc_saif.out
@@ -52,6 +52,8 @@
     (cyc\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
     (v_strp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
     (v_strp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_strp2\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_strp2\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
     (v_strp_strp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
     (v_strp_strp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
     (v_strp_strp\[2\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
@@ -68,20 +70,20 @@
     (v_arrp_strp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
     (v_arrp_strp\[2\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
     (v_arrp_strp\[3\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
-    (v_arru[1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
     (v_arru[2] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-    (v_arru_arru[3][1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-    (v_arru_arru[3][2] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-    (v_arru_arru[4][1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (v_arru[1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
     (v_arru_arru[4][2] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-    (v_arru_arrp[3]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
-    (v_arru_arrp[3]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_arru[4][1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (v_arru_arru[3][2] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (v_arru_arru[3][1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
     (v_arru_arrp[4]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
     (v_arru_arrp[4]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
-    (v_arru_strp[3]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
-    (v_arru_strp[3]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_arrp[3]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_arrp[3]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
     (v_arru_strp[4]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
     (v_arru_strp[4]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_strp[3]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_strp[3]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
     (v_real\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
     (v_real\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
     (v_real\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
diff --git a/test_regress/t/t_trace_complex_params_cc_vcd.out b/test_regress/t/t_trace_complex_params_cc_vcd.out
index dbfe9faa0..1c9866e4b 100644
--- a/test_regress/t/t_trace_complex_params_cc_vcd.out
+++ b/test_regress/t/t_trace_complex_params_cc_vcd.out
@@ -1,44 +1,45 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module top $end
-  $var wire 1 : clk $end
+  $var wire 1 ; clk $end
   $scope module $unit $end
    $var wire 1 " global_bit $end
   $upscope $end
   $scope module t $end
-   $var wire 1 : clk $end
+   $var wire 1 ; clk $end
    $var wire 32 # cyc [31:0] $end
    $var wire 2 $ v_strp [1:0] $end
-   $var wire 4 % v_strp_strp [3:0] $end
-   $var wire 2 & v_unip_strp [1:0] $end
-   $var wire 2 ' v_arrp [2:1] $end
-   $var wire 4 ( v_arrp_arrp [3:0] $end
-   $var wire 4 ) v_arrp_strp [3:0] $end
-   $var wire 1 ; v_arru[1] $end
+   $var wire 2 % v_strp2 [1:0] $end
+   $var wire 4 & v_strp_strp [3:0] $end
+   $var wire 2 ' v_unip_strp [1:0] $end
+   $var wire 2 ( v_arrp [2:1] $end
+   $var wire 4 ) v_arrp_arrp [3:0] $end
+   $var wire 4 * v_arrp_strp [3:0] $end
    $var wire 1 < v_arru[2] $end
-   $var wire 1 = v_arru_arru[3][1] $end
-   $var wire 1 > v_arru_arru[3][2] $end
+   $var wire 1 = v_arru[1] $end
+   $var wire 1 > v_arru_arru[4][2] $end
    $var wire 1 ? v_arru_arru[4][1] $end
-   $var wire 1 @ v_arru_arru[4][2] $end
-   $var wire 2 * v_arru_arrp[3] [2:1] $end
+   $var wire 1 @ v_arru_arru[3][2] $end
+   $var wire 1 A v_arru_arru[3][1] $end
    $var wire 2 + v_arru_arrp[4] [2:1] $end
-   $var wire 2 , v_arru_strp[3] [1:0] $end
+   $var wire 2 , v_arru_arrp[3] [2:1] $end
    $var wire 2 - v_arru_strp[4] [1:0] $end
-   $var real 64 . v_real $end
-   $var real 64 0 v_arr_real[0] $end
-   $var real 64 2 v_arr_real[1] $end
-   $var wire 64 A v_chandle [63:0] $end
-   $var wire 64 4 v_str32x2 [63:0] $end
-   $var wire 32 6 v_enumed [31:0] $end
-   $var wire 32 7 v_enumed2 [31:0] $end
-   $var wire 3 8 v_enumb [2:0] $end
-   $var wire 6 9 v_enumb2_str [5:0] $end
-   $var wire 8 C unpacked_array[-2] [7:0] $end
-   $var wire 8 D unpacked_array[-1] [7:0] $end
-   $var wire 8 E unpacked_array[0] [7:0] $end
-   $var wire 1 F LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
+   $var wire 2 . v_arru_strp[3] [1:0] $end
+   $var real 64 / v_real $end
+   $var real 64 1 v_arr_real[0] $end
+   $var real 64 3 v_arr_real[1] $end
+   $var wire 64 B v_chandle [63:0] $end
+   $var wire 64 5 v_str32x2 [63:0] $end
+   $var wire 32 7 v_enumed [31:0] $end
+   $var wire 32 8 v_enumed2 [31:0] $end
+   $var wire 3 9 v_enumb [2:0] $end
+   $var wire 6 : v_enumb2_str [5:0] $end
+   $var wire 8 D unpacked_array[-2] [7:0] $end
+   $var wire 8 E unpacked_array[-1] [7:0] $end
+   $var wire 8 F unpacked_array[0] [7:0] $end
+   $var wire 1 G LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
    $scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end
-    $var wire 32 G PARAM [31:0] $end
+    $var wire 32 J PARAM [31:0] $end
    $upscope $end
    $scope module p2 $end
     $var wire 32 H PARAM [31:0] $end
@@ -55,170 +56,177 @@ $enddefinitions $end
 1"
 b00000000000000000000000000000000 #
 b00 $
-b0000 %
-b00 &
+b00 %
+b0000 &
 b00 '
-b0000 (
+b00 (
 b0000 )
-b00 *
+b0000 *
 b00 +
 b00 ,
 b00 -
-r0 .
-r0 0
-r0 2
-b0000000000000000000000000000000000000000000000000000000011111111 4
-b00000000000000000000000000000000 6
+b00 .
+r0 /
+r0 1
+r0 3
+b0000000000000000000000000000000000000000000000000000000011111111 5
 b00000000000000000000000000000000 7
-b000 8
-b000000 9
-0:
+b00000000000000000000000000000000 8
+b000 9
+b000000 :
 0;
 0<
 0=
 0>
 0?
 0@
-b0000000000000000000000000000000000000000000000000000000000000000 A
-b00000000 C
+0A
+b0000000000000000000000000000000000000000000000000000000000000000 B
 b00000000 D
 b00000000 E
-0F
-b00000000000000000000000000000100 G
+b00000000 F
+0G
 b00000000000000000000000000000010 H
 b00000000000000000000000000000011 I
+b00000000000000000000000000000100 J
 #10
 b00000000000000000000000000000001 #
 b11 $
-b1111 %
-b11 &
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+b1111 &
 b11 '
-b1111 (
+b11 (
 b1111 )
-b11 *
+b1111 *
 b11 +
 b11 ,
 b11 -
-r0.1 .
-r0.2 0
-r0.3 2
-b0000000000000000000000000000000100000000000000000000000011111110 4
-b00000000000000000000000000000001 6
-b00000000000000000000000000000010 7
-b111 8
-1:
+b11 .
+r0.1 /
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+r0.3 3
+b0000000000000000000000000000000100000000000000000000000011111110 5
+b00000000000000000000000000000001 7
+b00000000000000000000000000000010 8
+b111 9
+1;
 #15
-0:
+0;
 #20
 b00000000000000000000000000000010 #
 b00 $
-b0000 %
-b00 &
+b00 %
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 b00 '
-b0000 (
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 b0000 )
-b00 *
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 b00 +
 b00 ,
 b00 -
-r0.2 .
-r0.4 0
-r0.6 2
-b0000000000000000000000000000001000000000000000000000000011111101 4
-b00000000000000000000000000000010 6
-b00000000000000000000000000000100 7
-b110 8
-b111111 9
-1:
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+b0000000000000000000000000000001000000000000000000000000011111101 5
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 #25
-0:
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 #30
 b00000000000000000000000000000011 #
 b11 $
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 b11 '
-b1111 (
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 b1111 )
-b11 *
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 b11 +
 b11 ,
 b11 -
-r0.3 .
-r0.6000000000000001 0
-r0.8999999999999999 2
-b0000000000000000000000000000001100000000000000000000000011111100 4
-b00000000000000000000000000000011 6
-b00000000000000000000000000000110 7
-b101 8
-b110110 9
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+b0000000000000000000000000000001100000000000000000000000011111100 5
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+b00000000000000000000000000000110 8
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+1;
 #35
-0:
+0;
 #40
 b00000000000000000000000000000100 #
 b00 $
-b0000 %
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 b00 '
-b0000 (
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 b0000 )
-b00 *
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 b00 +
 b00 ,
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-r0.4 .
-r0.8 0
-r1.2 2
-b0000000000000000000000000000010000000000000000000000000011111011 4
-b00000000000000000000000000000100 6
-b00000000000000000000000000001000 7
-b100 8
-b101101 9
-1:
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+b0000000000000000000000000000010000000000000000000000000011111011 5
+b00000000000000000000000000000100 7
+b00000000000000000000000000001000 8
+b100 9
+b101101 :
+1;
 #45
-0:
+0;
 #50
 b00000000000000000000000000000101 #
 b11 $
-b1111 %
-b11 &
+b11 %
+b1111 &
 b11 '
-b1111 (
+b11 (
 b1111 )
-b11 *
+b1111 *
 b11 +
 b11 ,
 b11 -
-r0.5 .
-r1 0
-r1.5 2
-b0000000000000000000000000000010100000000000000000000000011111010 4
-b00000000000000000000000000000101 6
-b00000000000000000000000000001010 7
-b011 8
-b100100 9
-1:
+b11 .
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+b0000000000000000000000000000010100000000000000000000000011111010 5
+b00000000000000000000000000000101 7
+b00000000000000000000000000001010 8
+b011 9
+b100100 :
+1;
 #55
-0:
+0;
 #60
 b00000000000000000000000000000110 #
 b00 $
-b0000 %
-b00 &
+b00 %
+b0000 &
 b00 '
-b0000 (
+b00 (
 b0000 )
-b00 *
+b0000 *
 b00 +
 b00 ,
 b00 -
-r0.6 .
-r1.2 0
-r1.8 2
-b0000000000000000000000000000011000000000000000000000000011111001 4
-b00000000000000000000000000000110 6
-b00000000000000000000000000001100 7
-b010 8
-b011011 9
-1:
+b00 .
+r0.6 /
+r1.2 1
+r1.8 3
+b0000000000000000000000000000011000000000000000000000000011111001 5
+b00000000000000000000000000000110 7
+b00000000000000000000000000001100 8
+b010 9
+b011011 :
+1;
diff --git a/test_regress/t/t_trace_complex_params_sc_fst.out b/test_regress/t/t_trace_complex_params_sc_fst.out
index 4f338341b..34c978935 100644
--- a/test_regress/t/t_trace_complex_params_sc_fst.out
+++ b/test_regress/t/t_trace_complex_params_sc_fst.out
@@ -1,5 +1,9 @@
 $date
-Sat Mar 14 09:17:23 2026
+<<<<<<< HEAD
+Tue Apr 14 15:20:41 2026
+=======
+Tue Mar 31 17:14:39 2026
+>>>>>>> 8895f96e4 (CR)
 
 $end
 $version
@@ -18,106 +22,108 @@ $end
    $var wire 1 " clk $end
    $var integer 32 # cyc [31:0] $end
    $var bit 2 $ v_strp [1:0] $end
-   $var bit 4 % v_strp_strp [3:0] $end
-   $var bit 2 & v_unip_strp [1:0] $end
-   $var bit 2 ' v_arrp [2:1] $end
-   $var bit 4 ( v_arrp_arrp [3:0] $end
-   $var bit 4 ) v_arrp_strp [3:0] $end
+   $var bit 2 % v_strp2 [1:0] $end
+   $var bit 4 & v_strp_strp [3:0] $end
+   $var bit 2 ' v_unip_strp [1:0] $end
+   $var bit 2 ( v_arrp [2:1] $end
+   $var bit 4 ) v_arrp_arrp [3:0] $end
+   $var bit 4 * v_arrp_strp [3:0] $end
    $attrbegin array unpacked bounds 8589934593 $end
    $scope sv_array v_arru $end
-    $var bit 1 * v_arru[2] $end
-    $var bit 1 + v_arru[1] $end
+    $var bit 1 + v_arru[2] $end
+    $var bit 1 , v_arru[1] $end
    $upscope $end
    $attrbegin array unpacked bounds 17179869187 $end
    $scope sv_array v_arru_arru $end
     $attrbegin array unpacked bounds 8589934593 $end
     $scope sv_array [4] $end
-     $var bit 1 , v_arru_arru[4][2] $end
-     $var bit 1 - v_arru_arru[4][1] $end
+     $var bit 1 - v_arru_arru[4][2] $end
+     $var bit 1 . v_arru_arru[4][1] $end
     $upscope $end
     $attrbegin array unpacked bounds 8589934593 $end
     $scope sv_array [3] $end
-     $var bit 1 . v_arru_arru[3][2] $end
-     $var bit 1 / v_arru_arru[3][1] $end
+     $var bit 1 / v_arru_arru[3][2] $end
+     $var bit 1 0 v_arru_arru[3][1] $end
     $upscope $end
    $upscope $end
    $attrbegin array unpacked bounds 17179869187 $end
    $scope sv_array v_arru_arrp $end
-    $var bit 2 0 v_arru_arrp[4] [2:1] $end
-    $var bit 2 1 v_arru_arrp[3] [2:1] $end
+    $var bit 2 1 v_arru_arrp[4] [2:1] $end
+    $var bit 2 2 v_arru_arrp[3] [2:1] $end
    $upscope $end
    $attrbegin array unpacked bounds 17179869187 $end
    $scope sv_array v_arru_strp $end
-    $var bit 2 2 v_arru_strp[4] [1:0] $end
-    $var bit 2 3 v_arru_strp[3] [1:0] $end
+    $var bit 2 3 v_arru_strp[4] [1:0] $end
+    $var bit 2 4 v_arru_strp[3] [1:0] $end
    $upscope $end
-   $var real 64 4 v_real $end
+   $var real 64 5 v_real $end
    $attrbegin array unpacked bounds 1 $end
    $scope sv_array v_arr_real $end
-    $var real 64 5 v_arr_real[0] $end
-    $var real 64 6 v_arr_real[1] $end
+    $var real 64 6 v_arr_real[0] $end
+    $var real 64 7 v_arr_real[1] $end
    $upscope $end
-   $var longint 64 7 v_chandle [63:0] $end
-   $var logic 64 8 v_str32x2 [63:0] $end
+   $var longint 64 8 v_chandle [63:0] $end
+   $var logic 64 9 v_str32x2 [63:0] $end
    $attrbegin misc 07 "" 1 $end
-   $var int 32 9 v_enumed [31:0] $end
+   $var int 32 : v_enumed [31:0] $end
    $attrbegin misc 07 "" 1 $end
-   $var int 32 : v_enumed2 [31:0] $end
+   $var int 32 ; v_enumed2 [31:0] $end
    $attrbegin misc 07 "" 2 $end
-   $var logic 3 ; v_enumb [2:0] $end
-   $var logic 6 < v_enumb2_str [5:0] $end
+   $var logic 3 < v_enumb [2:0] $end
+   $var logic 6 = v_enumb2_str [5:0] $end
    $attrbegin array unpacked bounds -8589934592 $end
    $scope sv_array unpacked_array $end
-    $var logic 8 = unpacked_array[-2] [7:0] $end
-    $var logic 8 > unpacked_array[-1] [7:0] $end
-    $var logic 8 ? unpacked_array[0] [7:0] $end
+    $var logic 8 > unpacked_array[-2] [7:0] $end
+    $var logic 8 ? unpacked_array[-1] [7:0] $end
+    $var logic 8 @ unpacked_array[0] [7:0] $end
    $upscope $end
-   $var bit 1 @ LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
+   $var bit 1 A LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
    $scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end
-    $var parameter 32 A PARAM [31:0] $end
-   $upscope $end
-   $scope module p2 $end
     $var parameter 32 B PARAM [31:0] $end
    $upscope $end
-   $scope module p3 $end
+   $scope module p2 $end
     $var parameter 32 C PARAM [31:0] $end
    $upscope $end
+   $scope module p3 $end
+    $var parameter 32 D PARAM [31:0] $end
+   $upscope $end
   $upscope $end
  $upscope $end
 $enddefinitions $end
 #0
 $dumpvars
-b00000000000000000000000000000011 C
-b00000000000000000000000000000010 B
-b00000000000000000000000000000100 A
-0@
+b00000000000000000000000000000011 D
+b00000000000000000000000000000010 C
+b00000000000000000000000000000100 B
+0A
+b00000000 @
 b00000000 ?
 b00000000 >
-b00000000 =
-b000000 <
-b000 ;
+b000000 =
+b000 <
+b00000000000000000000000000000000 ;
 b00000000000000000000000000000000 :
-b00000000000000000000000000000000 9
-b0000000000000000000000000000000000000000000000000000000011111111 8
-b0000000000000000000000000000000000000000000000000000000000000000 7
+b0000000000000000000000000000000000000000000000000000000011111111 9
+b0000000000000000000000000000000000000000000000000000000000000000 8
+r0 7
 r0 6
 r0 5
-r0 4
+b00 4
 b00 3
 b00 2
 b00 1
-b00 0
+00
 0/
 0.
 0-
 0,
 0+
-0*
+b0000 *
 b0000 )
-b0000 (
+b00 (
 b00 '
-b00 &
-b0000 %
+b0000 &
+b00 %
 b00 $
 b00000000000000000000000000000000 #
 0"
@@ -127,135 +133,141 @@ $end
 1"
 b00000000000000000000000000000001 #
 b11 $
-b1111 %
-b11 &
+b11 %
+b1111 &
 b11 '
-b1111 (
+b11 (
 b1111 )
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 b11 1
 b11 2
 b11 3
-r0.1 4
-r0.2 5
-r0.3 6
-b0000000000000000000000000000000100000000000000000000000011111110 8
-b00000000000000000000000000000001 9
-b00000000000000000000000000000010 :
-b111 ;
+b11 4
+r0.1 5
+r0.2 6
+r0.3 7
+b0000000000000000000000000000000100000000000000000000000011111110 9
+b00000000000000000000000000000001 :
+b00000000000000000000000000000010 ;
+b111 <
 #15
 0"
 #20
 1"
-b110 ;
-b00000000000000000000000000000100 :
-b00000000000000000000000000000010 9
-b0000000000000000000000000000001000000000000000000000000011111101 8
-r0.6 6
-r0.4 5
-r0.2 4
+b110 <
+b00000000000000000000000000000100 ;
+b00000000000000000000000000000010 :
+b0000000000000000000000000000001000000000000000000000000011111101 9
+r0.6 7
+r0.4 6
+r0.2 5
+b00 4
 b00 3
 b00 2
 b00 1
-b00 0
+b0000 *
 b0000 )
-b0000 (
+b00 (
 b00 '
-b00 &
-b0000 %
+b0000 &
+b00 %
 b00 $
 b00000000000000000000000000000010 #
-b111111 <
+b111111 =
 #25
 0"
 #30
 1"
-b110110 <
+b110110 =
 b00000000000000000000000000000011 #
 b11 $
-b1111 %
-b11 &
+b11 %
+b1111 &
 b11 '
-b1111 (
+b11 (
 b1111 )
-b11 0
+b1111 *
 b11 1
 b11 2
 b11 3
-r0.3 4
-r0.6000000000000001 5
-r0.8999999999999999 6
-b0000000000000000000000000000001100000000000000000000000011111100 8
-b00000000000000000000000000000011 9
-b00000000000000000000000000000110 :
-b101 ;
+b11 4
+r0.3 5
+r0.6000000000000001 6
+r0.8999999999999999 7
+b0000000000000000000000000000001100000000000000000000000011111100 9
+b00000000000000000000000000000011 :
+b00000000000000000000000000000110 ;
+b101 <
 #35
 0"
 #40
 1"
-b100 ;
-b00000000000000000000000000001000 :
-b00000000000000000000000000000100 9
-b0000000000000000000000000000010000000000000000000000000011111011 8
-r1.2 6
-r0.8 5
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+b100 <
+b00000000000000000000000000001000 ;
+b00000000000000000000000000000100 :
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+r1.2 7
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 b00 3
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-b00 0
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 b0000 )
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 b00 '
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 b00000000000000000000000000000100 #
-b101101 <
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 #45
 0"
 #50
 1"
-b100100 <
+b100100 =
 b00000000000000000000000000000101 #
 b11 $
-b1111 %
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 b11 '
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 b1111 )
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-b0000000000000000000000000000010100000000000000000000000011111010 8
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-b00000000000000000000000000001010 :
-b011 ;
+b11 4
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+b0000000000000000000000000000010100000000000000000000000011111010 9
+b00000000000000000000000000000101 :
+b00000000000000000000000000001010 ;
+b011 <
 #55
 0"
 #60
 1"
-b010 ;
-b00000000000000000000000000001100 :
-b00000000000000000000000000000110 9
-b0000000000000000000000000000011000000000000000000000000011111001 8
-r1.8 6
-r1.2 5
-r0.6 4
+b010 <
+b00000000000000000000000000001100 ;
+b00000000000000000000000000000110 :
+b0000000000000000000000000000011000000000000000000000000011111001 9
+r1.8 7
+r1.2 6
+r0.6 5
+b00 4
 b00 3
 b00 2
 b00 1
-b00 0
+b0000 *
 b0000 )
-b0000 (
+b00 (
 b00 '
-b00 &
-b0000 %
+b0000 &
+b00 %
 b00 $
 b00000000000000000000000000000110 #
-b011011 <
+b011011 =
 #64
diff --git a/test_regress/t/t_trace_complex_params_sc_vcd.out b/test_regress/t/t_trace_complex_params_sc_vcd.out
index c894c8109..363053c5c 100644
--- a/test_regress/t/t_trace_complex_params_sc_vcd.out
+++ b/test_regress/t/t_trace_complex_params_sc_vcd.out
@@ -5,46 +5,47 @@ $timescale 1ps $end
    $var wire 1 " global_bit $end
   $upscope $end
   $scope module t $end
-   $var wire 1 : clk $end
+   $var wire 1 ; clk $end
    $var wire 32 # cyc [31:0] $end
    $var wire 2 $ v_strp [1:0] $end
-   $var wire 4 % v_strp_strp [3:0] $end
-   $var wire 2 & v_unip_strp [1:0] $end
-   $var wire 2 ' v_arrp [2:1] $end
-   $var wire 4 ( v_arrp_arrp [3:0] $end
-   $var wire 4 ) v_arrp_strp [3:0] $end
-   $var wire 1 ; v_arru[2] $end
-   $var wire 1 < v_arru[1] $end
-   $var wire 1 = v_arru_arru[4][2] $end
-   $var wire 1 > v_arru_arru[4][1] $end
-   $var wire 1 ? v_arru_arru[3][2] $end
-   $var wire 1 @ v_arru_arru[3][1] $end
-   $var wire 2 * v_arru_arrp[4] [2:1] $end
-   $var wire 2 + v_arru_arrp[3] [2:1] $end
-   $var wire 2 , v_arru_strp[4] [1:0] $end
-   $var wire 2 - v_arru_strp[3] [1:0] $end
-   $var real 64 . v_real $end
-   $var real 64 0 v_arr_real[0] $end
-   $var real 64 2 v_arr_real[1] $end
-   $var wire 64 A v_chandle [63:0] $end
-   $var wire 64 4 v_str32x2 [63:0] $end
-   $var wire 32 6 v_enumed [31:0] $end
-   $var wire 32 7 v_enumed2 [31:0] $end
-   $var wire 3 8 v_enumb [2:0] $end
-   $var wire 6 9 v_enumb2_str [5:0] $end
-   $var wire 8 C unpacked_array[-2] [7:0] $end
-   $var wire 8 D unpacked_array[-1] [7:0] $end
-   $var wire 8 E unpacked_array[0] [7:0] $end
-   $var wire 1 F LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
+   $var wire 2 % v_strp2 [1:0] $end
+   $var wire 4 & v_strp_strp [3:0] $end
+   $var wire 2 ' v_unip_strp [1:0] $end
+   $var wire 2 ( v_arrp [2:1] $end
+   $var wire 4 ) v_arrp_arrp [3:0] $end
+   $var wire 4 * v_arrp_strp [3:0] $end
+   $var wire 1 < v_arru[2] $end
+   $var wire 1 = v_arru[1] $end
+   $var wire 1 > v_arru_arru[4][2] $end
+   $var wire 1 ? v_arru_arru[4][1] $end
+   $var wire 1 @ v_arru_arru[3][2] $end
+   $var wire 1 A v_arru_arru[3][1] $end
+   $var wire 2 + v_arru_arrp[4] [2:1] $end
+   $var wire 2 , v_arru_arrp[3] [2:1] $end
+   $var wire 2 - v_arru_strp[4] [1:0] $end
+   $var wire 2 . v_arru_strp[3] [1:0] $end
+   $var real 64 / v_real $end
+   $var real 64 1 v_arr_real[0] $end
+   $var real 64 3 v_arr_real[1] $end
+   $var wire 64 B v_chandle [63:0] $end
+   $var wire 64 5 v_str32x2 [63:0] $end
+   $var wire 32 7 v_enumed [31:0] $end
+   $var wire 32 8 v_enumed2 [31:0] $end
+   $var wire 3 9 v_enumb [2:0] $end
+   $var wire 6 : v_enumb2_str [5:0] $end
+   $var wire 8 D unpacked_array[-2] [7:0] $end
+   $var wire 8 E unpacked_array[-1] [7:0] $end
+   $var wire 8 F unpacked_array[0] [7:0] $end
+   $var wire 1 G LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
    $scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end
-    $var wire 32 G PARAM [31:0] $end
-   $upscope $end
-   $scope module p2 $end
     $var wire 32 H PARAM [31:0] $end
    $upscope $end
-   $scope module p3 $end
+   $scope module p2 $end
     $var wire 32 I PARAM [31:0] $end
    $upscope $end
+   $scope module p3 $end
+    $var wire 32 J PARAM [31:0] $end
+   $upscope $end
   $upscope $end
  $upscope $end
 $enddefinitions $end
@@ -54,171 +55,178 @@ $enddefinitions $end
 1"
 b00000000000000000000000000000000 #
 b00 $
-b0000 %
-b00 &
+b00 %
+b0000 &
 b00 '
-b0000 (
+b00 (
 b0000 )
-b00 *
+b0000 *
 b00 +
 b00 ,
 b00 -
-r0 .
-r0 0
-r0 2
-b0000000000000000000000000000000000000000000000000000000011111111 4
-b00000000000000000000000000000000 6
+b00 .
+r0 /
+r0 1
+r0 3
+b0000000000000000000000000000000000000000000000000000000011111111 5
 b00000000000000000000000000000000 7
-b000 8
-b000000 9
-0:
+b00000000000000000000000000000000 8
+b000 9
+b000000 :
 0;
 0<
 0=
 0>
 0?
 0@
-b0000000000000000000000000000000000000000000000000000000000000000 A
-b00000000 C
+0A
+b0000000000000000000000000000000000000000000000000000000000000000 B
 b00000000 D
 b00000000 E
-0F
-b00000000000000000000000000000100 G
-b00000000000000000000000000000010 H
-b00000000000000000000000000000011 I
+b00000000 F
+0G
+b00000000000000000000000000000100 H
+b00000000000000000000000000000010 I
+b00000000000000000000000000000011 J
 #10
 b00000000000000000000000000000001 #
 b11 $
-b1111 %
-b11 &
+b11 %
+b1111 &
 b11 '
-b1111 (
+b11 (
 b1111 )
-b11 *
+b1111 *
 b11 +
 b11 ,
 b11 -
-r0.1 .
-r0.2 0
-r0.3 2
-b0000000000000000000000000000000100000000000000000000000011111110 4
-b00000000000000000000000000000001 6
-b00000000000000000000000000000010 7
-b111 8
-1:
+b11 .
+r0.1 /
+r0.2 1
+r0.3 3
+b0000000000000000000000000000000100000000000000000000000011111110 5
+b00000000000000000000000000000001 7
+b00000000000000000000000000000010 8
+b111 9
+1;
 #15
-0:
+0;
 #20
 b00000000000000000000000000000010 #
 b00 $
-b0000 %
-b00 &
+b00 %
+b0000 &
 b00 '
-b0000 (
+b00 (
 b0000 )
-b00 *
+b0000 *
 b00 +
 b00 ,
 b00 -
-r0.2 .
-r0.4 0
-r0.6 2
-b0000000000000000000000000000001000000000000000000000000011111101 4
-b00000000000000000000000000000010 6
-b00000000000000000000000000000100 7
-b110 8
-b111111 9
-1:
+b00 .
+r0.2 /
+r0.4 1
+r0.6 3
+b0000000000000000000000000000001000000000000000000000000011111101 5
+b00000000000000000000000000000010 7
+b00000000000000000000000000000100 8
+b110 9
+b111111 :
+1;
 #25
-0:
+0;
 #30
 b00000000000000000000000000000011 #
 b11 $
-b1111 %
-b11 &
+b11 %
+b1111 &
 b11 '
-b1111 (
+b11 (
 b1111 )
-b11 *
+b1111 *
 b11 +
 b11 ,
 b11 -
-r0.3 .
-r0.6000000000000001 0
-r0.8999999999999999 2
-b0000000000000000000000000000001100000000000000000000000011111100 4
-b00000000000000000000000000000011 6
-b00000000000000000000000000000110 7
-b101 8
-b110110 9
-1:
+b11 .
+r0.3 /
+r0.6000000000000001 1
+r0.8999999999999999 3
+b0000000000000000000000000000001100000000000000000000000011111100 5
+b00000000000000000000000000000011 7
+b00000000000000000000000000000110 8
+b101 9
+b110110 :
+1;
 #35
-0:
+0;
 #40
 b00000000000000000000000000000100 #
 b00 $
-b0000 %
-b00 &
+b00 %
+b0000 &
 b00 '
-b0000 (
+b00 (
 b0000 )
-b00 *
+b0000 *
 b00 +
 b00 ,
 b00 -
-r0.4 .
-r0.8 0
-r1.2 2
-b0000000000000000000000000000010000000000000000000000000011111011 4
-b00000000000000000000000000000100 6
-b00000000000000000000000000001000 7
-b100 8
-b101101 9
-1:
+b00 .
+r0.4 /
+r0.8 1
+r1.2 3
+b0000000000000000000000000000010000000000000000000000000011111011 5
+b00000000000000000000000000000100 7
+b00000000000000000000000000001000 8
+b100 9
+b101101 :
+1;
 #45
-0:
+0;
 #50
 b00000000000000000000000000000101 #
 b11 $
-b1111 %
-b11 &
+b11 %
+b1111 &
 b11 '
-b1111 (
+b11 (
 b1111 )
-b11 *
+b1111 *
 b11 +
 b11 ,
 b11 -
-r0.5 .
-r1 0
-r1.5 2
-b0000000000000000000000000000010100000000000000000000000011111010 4
-b00000000000000000000000000000101 6
-b00000000000000000000000000001010 7
-b011 8
-b100100 9
-1:
+b11 .
+r0.5 /
+r1 1
+r1.5 3
+b0000000000000000000000000000010100000000000000000000000011111010 5
+b00000000000000000000000000000101 7
+b00000000000000000000000000001010 8
+b011 9
+b100100 :
+1;
 #55
-0:
+0;
 #60
 b00000000000000000000000000000110 #
 b00 $
-b0000 %
-b00 &
+b00 %
+b0000 &
 b00 '
-b0000 (
+b00 (
 b0000 )
-b00 *
+b0000 *
 b00 +
 b00 ,
 b00 -
-r0.6 .
-r1.2 0
-r1.8 2
-b0000000000000000000000000000011000000000000000000000000011111001 4
-b00000000000000000000000000000110 6
-b00000000000000000000000000001100 7
-b010 8
-b011011 9
-1:
+b00 .
+r0.6 /
+r1.2 1
+r1.8 3
+b0000000000000000000000000000011000000000000000000000000011111001 5
+b00000000000000000000000000000110 7
+b00000000000000000000000000001100 8
+b010 9
+b011011 :
+1;
 #64
diff --git a/test_regress/t/t_trace_complex_structs_cc_fst.out b/test_regress/t/t_trace_complex_structs_cc_fst.out
index ecea2ec22..3486fb134 100644
--- a/test_regress/t/t_trace_complex_structs_cc_fst.out
+++ b/test_regress/t/t_trace_complex_structs_cc_fst.out
@@ -1,5 +1,9 @@
 $date
-Sat Mar 14 09:17:04 2026
+<<<<<<< HEAD
+Tue Apr 14 15:20:40 2026
+=======
+Tue Mar 31 17:14:42 2026
+>>>>>>> 8895f96e4 (CR)
 
 $end
 $version
@@ -24,150 +28,157 @@ $end
     $var bit 1 % b0 $end
    $upscope $end
    $attrbegin pack packed members 2 $end
+   $scope struct v_strp2 $end
+    $var bit 1 & b1 $end
+    $var bit 1 ' b0 $end
+   $upscope $end
+   $attrbegin pack packed members 2 $end
    $scope struct v_strp_strp $end
     $attrbegin pack packed members 2 $end
     $scope struct x1 $end
-     $var bit 1 & b1 $end
-     $var bit 1 ' b0 $end
+     $var bit 1 ( b1 $end
+     $var bit 1 ) b0 $end
     $upscope $end
     $attrbegin pack packed members 2 $end
     $scope struct x0 $end
-     $var bit 1 ( b1 $end
-     $var bit 1 ) b0 $end
+     $var bit 1 * b1 $end
+     $var bit 1 + b0 $end
     $upscope $end
    $upscope $end
    $attrbegin pack packed members 2 $end
    $scope union v_unip_strp $end
     $attrbegin pack packed members 2 $end
     $scope struct x1 $end
-     $var bit 1 * b1 $end
-     $var bit 1 + b0 $end
+     $var bit 1 , b1 $end
+     $var bit 1 - b0 $end
     $upscope $end
     $attrbegin pack packed members 2 $end
     $scope struct x0 $end
-     $var bit 1 * b1 $end
-     $var bit 1 + b0 $end
+     $var bit 1 , b1 $end
+     $var bit 1 - b0 $end
     $upscope $end
    $upscope $end
-   $var bit 2 , v_arrp [2:1] $end
+   $var bit 2 . v_arrp [2:1] $end
    $attrbegin array packed bounds 17179869187 $end
    $scope sv_array v_arrp_arrp $end
-    $var bit 2 - v_arrp_arrp[4] [2:1] $end
-    $var bit 2 . v_arrp_arrp[3] [2:1] $end
+    $var bit 2 / v_arrp_arrp[4] [2:1] $end
+    $var bit 2 0 v_arrp_arrp[3] [2:1] $end
    $upscope $end
    $attrbegin array packed bounds 17179869187 $end
    $scope sv_array v_arrp_strp $end
     $attrbegin pack packed members 2 $end
     $scope struct [4] $end
-     $var bit 1 / b1 $end
-     $var bit 1 0 b0 $end
+     $var bit 1 1 b1 $end
+     $var bit 1 2 b0 $end
     $upscope $end
     $attrbegin pack packed members 2 $end
     $scope struct [3] $end
-     $var bit 1 1 b1 $end
-     $var bit 1 2 b0 $end
+     $var bit 1 3 b1 $end
+     $var bit 1 4 b0 $end
     $upscope $end
    $upscope $end
    $attrbegin array unpacked bounds 8589934593 $end
    $scope sv_array v_arru $end
-    $var bit 1 3 v_arru[2] $end
-    $var bit 1 4 v_arru[1] $end
+    $var bit 1 5 v_arru[2] $end
+    $var bit 1 6 v_arru[1] $end
    $upscope $end
    $attrbegin array unpacked bounds 17179869187 $end
    $scope sv_array v_arru_arru $end
     $attrbegin array unpacked bounds 8589934593 $end
     $scope sv_array [4] $end
-     $var bit 1 5 v_arru_arru[4][2] $end
-     $var bit 1 6 v_arru_arru[4][1] $end
+     $var bit 1 7 v_arru_arru[4][2] $end
+     $var bit 1 8 v_arru_arru[4][1] $end
     $upscope $end
     $attrbegin array unpacked bounds 8589934593 $end
     $scope sv_array [3] $end
-     $var bit 1 7 v_arru_arru[3][2] $end
-     $var bit 1 8 v_arru_arru[3][1] $end
+     $var bit 1 9 v_arru_arru[3][2] $end
+     $var bit 1 : v_arru_arru[3][1] $end
     $upscope $end
    $upscope $end
    $attrbegin array unpacked bounds 17179869187 $end
    $scope sv_array v_arru_arrp $end
-    $var bit 2 9 v_arru_arrp[4] [2:1] $end
-    $var bit 2 : v_arru_arrp[3] [2:1] $end
+    $var bit 2 ; v_arru_arrp[4] [2:1] $end
+    $var bit 2 < v_arru_arrp[3] [2:1] $end
    $upscope $end
    $attrbegin array unpacked bounds 17179869187 $end
    $scope sv_array v_arru_strp $end
     $attrbegin pack packed members 2 $end
     $scope struct [4] $end
-     $var bit 1 ; b1 $end
-     $var bit 1 < b0 $end
-    $upscope $end
-    $attrbegin pack packed members 2 $end
-    $scope struct [3] $end
      $var bit 1 = b1 $end
      $var bit 1 > b0 $end
     $upscope $end
+    $attrbegin pack packed members 2 $end
+    $scope struct [3] $end
+     $var bit 1 ? b1 $end
+     $var bit 1 @ b0 $end
+    $upscope $end
    $upscope $end
-   $var real 64 ? v_real $end
+   $var real 64 A v_real $end
    $attrbegin array unpacked bounds 1 $end
    $scope sv_array v_arr_real $end
-    $var real 64 @ v_arr_real[0] $end
-    $var real 64 A v_arr_real[1] $end
+    $var real 64 B v_arr_real[0] $end
+    $var real 64 C v_arr_real[1] $end
    $upscope $end
-   $var longint 64 B v_chandle [63:0] $end
+   $var longint 64 D v_chandle [63:0] $end
    $attrbegin array packed bounds 4294967296 $end
    $scope sv_array v_str32x2 $end
     $attrbegin pack packed members 1 $end
     $scope struct [1] $end
-     $var logic 32 C data [31:0] $end
+     $var logic 32 E data [31:0] $end
     $upscope $end
     $attrbegin pack packed members 1 $end
     $scope struct [0] $end
-     $var logic 32 D data [31:0] $end
+     $var logic 32 F data [31:0] $end
     $upscope $end
    $upscope $end
    $attrbegin misc 07 "" 1 $end
-   $var int 32 E v_enumed [31:0] $end
+   $var int 32 G v_enumed [31:0] $end
    $attrbegin misc 07 "" 1 $end
-   $var int 32 F v_enumed2 [31:0] $end
+   $var int 32 H v_enumed2 [31:0] $end
    $attrbegin misc 07 "" 2 $end
-   $var logic 3 G v_enumb [2:0] $end
+   $var logic 3 I v_enumb [2:0] $end
    $attrbegin pack packed members 2 $end
    $scope struct v_enumb2_str $end
     $attrbegin misc 07 "" 2 $end
-    $var logic 3 H a [2:0] $end
+    $var logic 3 J a [2:0] $end
     $attrbegin misc 07 "" 2 $end
-    $var logic 3 I b [2:0] $end
+    $var logic 3 K b [2:0] $end
    $upscope $end
    $attrbegin array unpacked bounds -8589934592 $end
    $scope sv_array unpacked_array $end
-    $var logic 8 J unpacked_array[-2] [7:0] $end
-    $var logic 8 K unpacked_array[-1] [7:0] $end
-    $var logic 8 L unpacked_array[0] [7:0] $end
+    $var logic 8 L unpacked_array[-2] [7:0] $end
+    $var logic 8 M unpacked_array[-1] [7:0] $end
+    $var logic 8 N unpacked_array[0] [7:0] $end
    $upscope $end
-   $var bit 1 M LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
+   $var bit 1 O LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
   $upscope $end
  $upscope $end
 $enddefinitions $end
 #0
 $dumpvars
-0M
+0O
+b00000000 N
+b00000000 M
 b00000000 L
-b00000000 K
-b00000000 J
+b000 K
+b000 J
 b000 I
-b000 H
-b000 G
-b00000000000000000000000000000000 F
+b00000000000000000000000000000000 H
+b00000000000000000000000000000000 G
+b00000000000000000000000011111111 F
 b00000000000000000000000000000000 E
-b00000000000000000000000011111111 D
-b00000000000000000000000000000000 C
-b0000000000000000000000000000000000000000000000000000000000000000 B
+b0000000000000000000000000000000000000000000000000000000000000000 D
+r0 C
+r0 B
 r0 A
-r0 @
-r0 ?
+0@
+0?
 0>
 0=
-0<
-0;
-b00 :
-b00 9
+b00 <
+b00 ;
+0:
+09
 08
 07
 06
@@ -176,11 +187,11 @@ b00 9
 03
 02
 01
-00
-0/
+b00 0
+b00 /
 b00 .
-b00 -
-b00 ,
+0-
+0,
 0+
 0*
 0)
@@ -204,52 +215,56 @@ b00000000000000000000000000000001 #
 1)
 1*
 1+
-b11 ,
-b11 -
+1,
+1-
 b11 .
-1/
-10
+b11 /
+b11 0
 11
 12
-b11 9
-b11 :
-1;
-1<
+13
+14
+b11 ;
+b11 <
 1=
 1>
-r0.1 ?
-r0.2 @
-r0.3 A
-b00000000000000000000000000000001 C
-b00000000000000000000000011111110 D
+1?
+1@
+r0.1 A
+r0.2 B
+r0.3 C
 b00000000000000000000000000000001 E
-b00000000000000000000000000000010 F
-b111 G
+b00000000000000000000000011111110 F
+b00000000000000000000000000000001 G
+b00000000000000000000000000000010 H
+b111 I
 #15
 0!
 #20
 1!
-b110 G
-b00000000000000000000000000000100 F
+b110 I
+b00000000000000000000000000000100 H
+b00000000000000000000000000000010 G
+b00000000000000000000000011111101 F
 b00000000000000000000000000000010 E
-b00000000000000000000000011111101 D
-b00000000000000000000000000000010 C
-r0.6 A
-r0.4 @
-r0.2 ?
+r0.6 C
+r0.4 B
+r0.2 A
+0@
+0?
 0>
 0=
-0<
-0;
-b00 :
-b00 9
+b00 <
+b00 ;
+04
+03
 02
 01
-00
-0/
+b00 0
+b00 /
 b00 .
-b00 -
-b00 ,
+0-
+0,
 0+
 0*
 0)
@@ -259,14 +274,14 @@ b00 ,
 0%
 0$
 b00000000000000000000000000000010 #
-b111 H
-b111 I
+b111 J
+b111 K
 #25
 0!
 #30
 1!
-b110 I
-b110 H
+b110 K
+b110 J
 b00000000000000000000000000000011 #
 1$
 1%
@@ -276,52 +291,56 @@ b00000000000000000000000000000011 #
 1)
 1*
 1+
-b11 ,
-b11 -
+1,
+1-
 b11 .
-1/
-10
+b11 /
+b11 0
 11
 12
-b11 9
-b11 :
-1;
-1<
+13
+14
+b11 ;
+b11 <
 1=
 1>
-r0.3 ?
-r0.6000000000000001 @
-r0.8999999999999999 A
-b00000000000000000000000000000011 C
-b00000000000000000000000011111100 D
+1?
+1@
+r0.3 A
+r0.6000000000000001 B
+r0.8999999999999999 C
 b00000000000000000000000000000011 E
-b00000000000000000000000000000110 F
-b101 G
+b00000000000000000000000011111100 F
+b00000000000000000000000000000011 G
+b00000000000000000000000000000110 H
+b101 I
 #35
 0!
 #40
 1!
-b100 G
-b00000000000000000000000000001000 F
+b100 I
+b00000000000000000000000000001000 H
+b00000000000000000000000000000100 G
+b00000000000000000000000011111011 F
 b00000000000000000000000000000100 E
-b00000000000000000000000011111011 D
-b00000000000000000000000000000100 C
-r1.2 A
-r0.8 @
-r0.4 ?
+r1.2 C
+r0.8 B
+r0.4 A
+0@
+0?
 0>
 0=
-0<
-0;
-b00 :
-b00 9
+b00 <
+b00 ;
+04
+03
 02
 01
-00
-0/
+b00 0
+b00 /
 b00 .
-b00 -
-b00 ,
+0-
+0,
 0+
 0*
 0)
@@ -331,14 +350,14 @@ b00 ,
 0%
 0$
 b00000000000000000000000000000100 #
-b101 H
-b101 I
+b101 J
+b101 K
 #45
 0!
 #50
 1!
-b100 I
-b100 H
+b100 K
+b100 J
 b00000000000000000000000000000101 #
 1$
 1%
@@ -348,52 +367,56 @@ b00000000000000000000000000000101 #
 1)
 1*
 1+
-b11 ,
-b11 -
+1,
+1-
 b11 .
-1/
-10
+b11 /
+b11 0
 11
 12
-b11 9
-b11 :
-1;
-1<
+13
+14
+b11 ;
+b11 <
 1=
 1>
-r0.5 ?
-r1 @
-r1.5 A
-b00000000000000000000000000000101 C
-b00000000000000000000000011111010 D
+1?
+1@
+r0.5 A
+r1 B
+r1.5 C
 b00000000000000000000000000000101 E
-b00000000000000000000000000001010 F
-b011 G
+b00000000000000000000000011111010 F
+b00000000000000000000000000000101 G
+b00000000000000000000000000001010 H
+b011 I
 #55
 0!
 #60
 1!
-b010 G
-b00000000000000000000000000001100 F
+b010 I
+b00000000000000000000000000001100 H
+b00000000000000000000000000000110 G
+b00000000000000000000000011111001 F
 b00000000000000000000000000000110 E
-b00000000000000000000000011111001 D
-b00000000000000000000000000000110 C
-r1.8 A
-r1.2 @
-r0.6 ?
+r1.8 C
+r1.2 B
+r0.6 A
+0@
+0?
 0>
 0=
-0<
-0;
-b00 :
-b00 9
+b00 <
+b00 ;
+04
+03
 02
 01
-00
-0/
+b00 0
+b00 /
 b00 .
-b00 -
-b00 ,
+0-
+0,
 0+
 0*
 0)
@@ -403,5 +426,5 @@ b00 ,
 0%
 0$
 b00000000000000000000000000000110 #
-b011 H
-b011 I
+b011 J
+b011 K
diff --git a/test_regress/t/t_trace_complex_structs_cc_saif.out b/test_regress/t/t_trace_complex_structs_cc_saif.out
index ca02d9506..981a59d9e 100644
--- a/test_regress/t/t_trace_complex_structs_cc_saif.out
+++ b/test_regress/t/t_trace_complex_structs_cc_saif.out
@@ -52,20 +52,20 @@
     (cyc\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
     (v_arrp\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
     (v_arrp\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
-    (v_arrp_arrp[3]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
-    (v_arrp_arrp[3]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
     (v_arrp_arrp[4]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
     (v_arrp_arrp[4]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
-    (v_arru[1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (v_arrp_arrp[3]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arrp_arrp[3]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
     (v_arru[2] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-    (v_arru_arru[3][1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-    (v_arru_arru[3][2] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-    (v_arru_arru[4][1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (v_arru[1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
     (v_arru_arru[4][2] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-    (v_arru_arrp[3]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
-    (v_arru_arrp[3]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_arru[4][1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (v_arru_arru[3][2] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (v_arru_arru[3][1] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
     (v_arru_arrp[4]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
     (v_arru_arrp[4]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_arrp[3]\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (v_arru_arrp[3]\[1\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
     (v_real\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
     (v_real\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
     (v_real\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
@@ -421,6 +421,12 @@
      (b0 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
     )
    )
+   (INSTANCE v_strp2
+    (NET
+     (b1 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+     (b0 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    )
+   )
    (INSTANCE v_strp_strp
     (INSTANCE x1
      (NET
@@ -449,19 +455,13 @@
      )
     )
    )
-   (INSTANCE v_arrp_strp[3]
-    (NET
-     (b1 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
-     (b0 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
-    )
-   )
    (INSTANCE v_arrp_strp[4]
     (NET
      (b1 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
      (b0 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
     )
    )
-   (INSTANCE v_arru_strp[3]
+   (INSTANCE v_arrp_strp[3]
     (NET
      (b1 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
      (b0 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
@@ -473,16 +473,22 @@
      (b0 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
     )
    )
-   (INSTANCE v_str32x2[0]
+   (INSTANCE v_arru_strp[3]
     (NET
-     (data\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 7))
-     (data\[1\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
-     (data\[2\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
-     (data\[3\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
-     (data\[4\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
-     (data\[5\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
-     (data\[6\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
-     (data\[7\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (b1 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+     (b0 (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    )
+   )
+   (INSTANCE v_str32x2[1]
+    (NET
+     (data\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+     (data\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (data\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
      (data\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
      (data\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
      (data\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
@@ -509,16 +515,16 @@
      (data\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
     )
    )
-   (INSTANCE v_str32x2[1]
+   (INSTANCE v_str32x2[0]
     (NET
-     (data\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
-     (data\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
-     (data\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
-     (data\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-     (data\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-     (data\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-     (data\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-     (data\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 7))
+     (data\[1\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+     (data\[2\] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (data\[3\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data\[4\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data\[5\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data\[6\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data\[7\] (T0 0) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
      (data\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
      (data\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
      (data\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
diff --git a/test_regress/t/t_trace_complex_structs_cc_vcd.out b/test_regress/t/t_trace_complex_structs_cc_vcd.out
index 344918de0..f75ced95f 100644
--- a/test_regress/t/t_trace_complex_structs_cc_vcd.out
+++ b/test_regress/t/t_trace_complex_structs_cc_vcd.out
@@ -1,85 +1,89 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module top $end
-  $var wire 1 F clk $end
+  $var wire 1 H clk $end
   $scope module $unit $end
    $var wire 1 " global_bit $end
   $upscope $end
   $scope module t $end
-   $var wire 1 F clk $end
+   $var wire 1 H clk $end
    $var wire 32 # cyc [31:0] $end
    $scope module v_strp $end
     $var wire 1 $ b1 $end
     $var wire 1 % b0 $end
    $upscope $end
+   $scope module v_strp2 $end
+    $var wire 1 & b1 $end
+    $var wire 1 ' b0 $end
+   $upscope $end
    $scope module v_strp_strp $end
     $scope module x1 $end
-     $var wire 1 & b1 $end
-     $var wire 1 ' b0 $end
-    $upscope $end
-    $scope module x0 $end
      $var wire 1 ( b1 $end
      $var wire 1 ) b0 $end
     $upscope $end
+    $scope module x0 $end
+     $var wire 1 * b1 $end
+     $var wire 1 + b0 $end
+    $upscope $end
    $upscope $end
    $scope module v_unip_strp $end
     $scope module x1 $end
-     $var wire 1 * b1 $end
-     $var wire 1 + b0 $end
+     $var wire 1 , b1 $end
+     $var wire 1 - b0 $end
     $upscope $end
     $scope module x0 $end
-     $var wire 1 * b1 $end
-     $var wire 1 + b0 $end
+     $var wire 1 , b1 $end
+     $var wire 1 - b0 $end
     $upscope $end
    $upscope $end
-   $var wire 2 , v_arrp [2:1] $end
-   $var wire 2 - v_arrp_arrp[3] [2:1] $end
-   $var wire 2 . v_arrp_arrp[4] [2:1] $end
-   $scope module v_arrp_strp[3] $end
-    $var wire 1 / b1 $end
-    $var wire 1 0 b0 $end
-   $upscope $end
+   $var wire 2 . v_arrp [2:1] $end
+   $var wire 2 / v_arrp_arrp[4] [2:1] $end
+   $var wire 2 0 v_arrp_arrp[3] [2:1] $end
    $scope module v_arrp_strp[4] $end
     $var wire 1 1 b1 $end
     $var wire 1 2 b0 $end
    $upscope $end
-   $var wire 1 G v_arru[1] $end
-   $var wire 1 H v_arru[2] $end
-   $var wire 1 I v_arru_arru[3][1] $end
-   $var wire 1 J v_arru_arru[3][2] $end
-   $var wire 1 K v_arru_arru[4][1] $end
-   $var wire 1 L v_arru_arru[4][2] $end
-   $var wire 2 3 v_arru_arrp[3] [2:1] $end
-   $var wire 2 4 v_arru_arrp[4] [2:1] $end
-   $scope module v_arru_strp[3] $end
-    $var wire 1 5 b1 $end
-    $var wire 1 6 b0 $end
+   $scope module v_arrp_strp[3] $end
+    $var wire 1 3 b1 $end
+    $var wire 1 4 b0 $end
    $upscope $end
+   $var wire 1 I v_arru[2] $end
+   $var wire 1 J v_arru[1] $end
+   $var wire 1 K v_arru_arru[4][2] $end
+   $var wire 1 L v_arru_arru[4][1] $end
+   $var wire 1 M v_arru_arru[3][2] $end
+   $var wire 1 N v_arru_arru[3][1] $end
+   $var wire 2 5 v_arru_arrp[4] [2:1] $end
+   $var wire 2 6 v_arru_arrp[3] [2:1] $end
    $scope module v_arru_strp[4] $end
     $var wire 1 7 b1 $end
     $var wire 1 8 b0 $end
    $upscope $end
-   $var real 64 9 v_real $end
-   $var real 64 ; v_arr_real[0] $end
-   $var real 64 = v_arr_real[1] $end
-   $var wire 64 M v_chandle [63:0] $end
-   $scope module v_str32x2[0] $end
-    $var wire 32 ? data [31:0] $end
+   $scope module v_arru_strp[3] $end
+    $var wire 1 9 b1 $end
+    $var wire 1 : b0 $end
    $upscope $end
+   $var real 64 ; v_real $end
+   $var real 64 = v_arr_real[0] $end
+   $var real 64 ? v_arr_real[1] $end
+   $var wire 64 O v_chandle [63:0] $end
    $scope module v_str32x2[1] $end
-    $var wire 32 @ data [31:0] $end
+    $var wire 32 A data [31:0] $end
    $upscope $end
-   $var wire 32 A v_enumed [31:0] $end
-   $var wire 32 B v_enumed2 [31:0] $end
-   $var wire 3 C v_enumb [2:0] $end
+   $scope module v_str32x2[0] $end
+    $var wire 32 B data [31:0] $end
+   $upscope $end
+   $var wire 32 C v_enumed [31:0] $end
+   $var wire 32 D v_enumed2 [31:0] $end
+   $var wire 3 E v_enumb [2:0] $end
    $scope module v_enumb2_str $end
-    $var wire 3 D a [2:0] $end
-    $var wire 3 E b [2:0] $end
+    $var wire 3 F a [2:0] $end
+    $var wire 3 G b [2:0] $end
    $upscope $end
-   $var wire 8 O unpacked_array[-2] [7:0] $end
-   $var wire 8 P unpacked_array[-1] [7:0] $end
-   $var wire 8 Q unpacked_array[0] [7:0] $end
-   $var wire 1 R LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
+   $var wire 8 Q unpacked_array[-2] [7:0] $end
+   $var wire 8 R unpacked_array[-1] [7:0] $end
+   $var wire 8 S unpacked_array[0] [7:0] $end
+   $var wire 1 T LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
   $upscope $end
  $upscope $end
 $enddefinitions $end
@@ -96,41 +100,43 @@ b00000000000000000000000000000000 #
 0)
 0*
 0+
-b00 ,
-b00 -
+0,
+0-
 b00 .
-0/
-00
+b00 /
+b00 0
 01
 02
-b00 3
-b00 4
-05
-06
+03
+04
+b00 5
+b00 6
 07
 08
-r0 9
+09
+0:
 r0 ;
 r0 =
-b00000000000000000000000011111111 ?
-b00000000000000000000000000000000 @
+r0 ?
 b00000000000000000000000000000000 A
-b00000000000000000000000000000000 B
-b000 C
-b000 D
+b00000000000000000000000011111111 B
+b00000000000000000000000000000000 C
+b00000000000000000000000000000000 D
 b000 E
-0F
-0G
+b000 F
+b000 G
 0H
 0I
 0J
 0K
 0L
-b0000000000000000000000000000000000000000000000000000000000000000 M
-b00000000 O
-b00000000 P
+0M
+0N
+b0000000000000000000000000000000000000000000000000000000000000000 O
 b00000000 Q
-0R
+b00000000 R
+b00000000 S
+0T
 #10
 b00000000000000000000000000000001 #
 1$
@@ -141,30 +147,32 @@ b00000000000000000000000000000001 #
 1)
 1*
 1+
-b11 ,
-b11 -
+1,
+1-
 b11 .
-1/
-10
+b11 /
+b11 0
 11
 12
-b11 3
-b11 4
-15
-16
+13
+14
+b11 5
+b11 6
 17
 18
-r0.1 9
-r0.2 ;
-r0.3 =
-b00000000000000000000000011111110 ?
-b00000000000000000000000000000001 @
+19
+1:
+r0.1 ;
+r0.2 =
+r0.3 ?
 b00000000000000000000000000000001 A
-b00000000000000000000000000000010 B
-b111 C
-1F
+b00000000000000000000000011111110 B
+b00000000000000000000000000000001 C
+b00000000000000000000000000000010 D
+b111 E
+1H
 #15
-0F
+0H
 #20
 b00000000000000000000000000000010 #
 0$
@@ -175,32 +183,34 @@ b00000000000000000000000000000010 #
 0)
 0*
 0+
-b00 ,
-b00 -
+0,
+0-
 b00 .
-0/
-00
+b00 /
+b00 0
 01
 02
-b00 3
-b00 4
-05
-06
+03
+04
+b00 5
+b00 6
 07
 08
-r0.2 9
-r0.4 ;
-r0.6 =
-b00000000000000000000000011111101 ?
-b00000000000000000000000000000010 @
+09
+0:
+r0.2 ;
+r0.4 =
+r0.6 ?
 b00000000000000000000000000000010 A
-b00000000000000000000000000000100 B
-b110 C
-b111 D
-b111 E
-1F
+b00000000000000000000000011111101 B
+b00000000000000000000000000000010 C
+b00000000000000000000000000000100 D
+b110 E
+b111 F
+b111 G
+1H
 #25
-0F
+0H
 #30
 b00000000000000000000000000000011 #
 1$
@@ -211,32 +221,34 @@ b00000000000000000000000000000011 #
 1)
 1*
 1+
-b11 ,
-b11 -
+1,
+1-
 b11 .
-1/
-10
+b11 /
+b11 0
 11
 12
-b11 3
-b11 4
-15
-16
+13
+14
+b11 5
+b11 6
 17
 18
-r0.3 9
-r0.6000000000000001 ;
-r0.8999999999999999 =
-b00000000000000000000000011111100 ?
-b00000000000000000000000000000011 @
+19
+1:
+r0.3 ;
+r0.6000000000000001 =
+r0.8999999999999999 ?
 b00000000000000000000000000000011 A
-b00000000000000000000000000000110 B
-b101 C
-b110 D
-b110 E
-1F
+b00000000000000000000000011111100 B
+b00000000000000000000000000000011 C
+b00000000000000000000000000000110 D
+b101 E
+b110 F
+b110 G
+1H
 #35
-0F
+0H
 #40
 b00000000000000000000000000000100 #
 0$
@@ -247,32 +259,34 @@ b00000000000000000000000000000100 #
 0)
 0*
 0+
-b00 ,
-b00 -
+0,
+0-
 b00 .
-0/
-00
+b00 /
+b00 0
 01
 02
-b00 3
-b00 4
-05
-06
+03
+04
+b00 5
+b00 6
 07
 08
-r0.4 9
-r0.8 ;
-r1.2 =
-b00000000000000000000000011111011 ?
-b00000000000000000000000000000100 @
+09
+0:
+r0.4 ;
+r0.8 =
+r1.2 ?
 b00000000000000000000000000000100 A
-b00000000000000000000000000001000 B
-b100 C
-b101 D
-b101 E
-1F
+b00000000000000000000000011111011 B
+b00000000000000000000000000000100 C
+b00000000000000000000000000001000 D
+b100 E
+b101 F
+b101 G
+1H
 #45
-0F
+0H
 #50
 b00000000000000000000000000000101 #
 1$
@@ -283,32 +297,34 @@ b00000000000000000000000000000101 #
 1)
 1*
 1+
-b11 ,
-b11 -
+1,
+1-
 b11 .
-1/
-10
+b11 /
+b11 0
 11
 12
-b11 3
-b11 4
-15
-16
+13
+14
+b11 5
+b11 6
 17
 18
-r0.5 9
-r1 ;
-r1.5 =
-b00000000000000000000000011111010 ?
-b00000000000000000000000000000101 @
+19
+1:
+r0.5 ;
+r1 =
+r1.5 ?
 b00000000000000000000000000000101 A
-b00000000000000000000000000001010 B
-b011 C
-b100 D
-b100 E
-1F
+b00000000000000000000000011111010 B
+b00000000000000000000000000000101 C
+b00000000000000000000000000001010 D
+b011 E
+b100 F
+b100 G
+1H
 #55
-0F
+0H
 #60
 b00000000000000000000000000000110 #
 0$
@@ -319,27 +335,29 @@ b00000000000000000000000000000110 #
 0)
 0*
 0+
-b00 ,
-b00 -
+0,
+0-
 b00 .
-0/
-00
+b00 /
+b00 0
 01
 02
-b00 3
-b00 4
-05
-06
+03
+04
+b00 5
+b00 6
 07
 08
-r0.6 9
-r1.2 ;
-r1.8 =
-b00000000000000000000000011111001 ?
-b00000000000000000000000000000110 @
+09
+0:
+r0.6 ;
+r1.2 =
+r1.8 ?
 b00000000000000000000000000000110 A
-b00000000000000000000000000001100 B
-b010 C
-b011 D
-b011 E
-1F
+b00000000000000000000000011111001 B
+b00000000000000000000000000000110 C
+b00000000000000000000000000001100 D
+b010 E
+b011 F
+b011 G
+1H
diff --git a/test_regress/t/t_trace_complex_structs_sc_fst.out b/test_regress/t/t_trace_complex_structs_sc_fst.out
index 16376ed16..662f16239 100644
--- a/test_regress/t/t_trace_complex_structs_sc_fst.out
+++ b/test_regress/t/t_trace_complex_structs_sc_fst.out
@@ -1,5 +1,9 @@
 $date
-Sat Mar 14 09:16:58 2026
+<<<<<<< HEAD
+Tue Apr 14 15:20:41 2026
+=======
+Tue Mar 31 17:14:45 2026
+>>>>>>> 8895f96e4 (CR)
 
 $end
 $version
@@ -23,150 +27,157 @@ $end
     $var bit 1 % b0 $end
    $upscope $end
    $attrbegin pack packed members 2 $end
+   $scope struct v_strp2 $end
+    $var bit 1 & b1 $end
+    $var bit 1 ' b0 $end
+   $upscope $end
+   $attrbegin pack packed members 2 $end
    $scope struct v_strp_strp $end
     $attrbegin pack packed members 2 $end
     $scope struct x1 $end
-     $var bit 1 & b1 $end
-     $var bit 1 ' b0 $end
+     $var bit 1 ( b1 $end
+     $var bit 1 ) b0 $end
     $upscope $end
     $attrbegin pack packed members 2 $end
     $scope struct x0 $end
-     $var bit 1 ( b1 $end
-     $var bit 1 ) b0 $end
+     $var bit 1 * b1 $end
+     $var bit 1 + b0 $end
     $upscope $end
    $upscope $end
    $attrbegin pack packed members 2 $end
    $scope union v_unip_strp $end
     $attrbegin pack packed members 2 $end
     $scope struct x1 $end
-     $var bit 1 * b1 $end
-     $var bit 1 + b0 $end
+     $var bit 1 , b1 $end
+     $var bit 1 - b0 $end
     $upscope $end
     $attrbegin pack packed members 2 $end
     $scope struct x0 $end
-     $var bit 1 * b1 $end
-     $var bit 1 + b0 $end
+     $var bit 1 , b1 $end
+     $var bit 1 - b0 $end
     $upscope $end
    $upscope $end
-   $var bit 2 , v_arrp [2:1] $end
+   $var bit 2 . v_arrp [2:1] $end
    $attrbegin array packed bounds 17179869187 $end
    $scope sv_array v_arrp_arrp $end
-    $var bit 2 - v_arrp_arrp[4] [2:1] $end
-    $var bit 2 . v_arrp_arrp[3] [2:1] $end
+    $var bit 2 / v_arrp_arrp[4] [2:1] $end
+    $var bit 2 0 v_arrp_arrp[3] [2:1] $end
    $upscope $end
    $attrbegin array packed bounds 17179869187 $end
    $scope sv_array v_arrp_strp $end
     $attrbegin pack packed members 2 $end
     $scope struct [4] $end
-     $var bit 1 / b1 $end
-     $var bit 1 0 b0 $end
+     $var bit 1 1 b1 $end
+     $var bit 1 2 b0 $end
     $upscope $end
     $attrbegin pack packed members 2 $end
     $scope struct [3] $end
-     $var bit 1 1 b1 $end
-     $var bit 1 2 b0 $end
+     $var bit 1 3 b1 $end
+     $var bit 1 4 b0 $end
     $upscope $end
    $upscope $end
    $attrbegin array unpacked bounds 8589934593 $end
    $scope sv_array v_arru $end
-    $var bit 1 3 v_arru[2] $end
-    $var bit 1 4 v_arru[1] $end
+    $var bit 1 5 v_arru[2] $end
+    $var bit 1 6 v_arru[1] $end
    $upscope $end
    $attrbegin array unpacked bounds 17179869187 $end
    $scope sv_array v_arru_arru $end
     $attrbegin array unpacked bounds 8589934593 $end
     $scope sv_array [4] $end
-     $var bit 1 5 v_arru_arru[4][2] $end
-     $var bit 1 6 v_arru_arru[4][1] $end
+     $var bit 1 7 v_arru_arru[4][2] $end
+     $var bit 1 8 v_arru_arru[4][1] $end
     $upscope $end
     $attrbegin array unpacked bounds 8589934593 $end
     $scope sv_array [3] $end
-     $var bit 1 7 v_arru_arru[3][2] $end
-     $var bit 1 8 v_arru_arru[3][1] $end
+     $var bit 1 9 v_arru_arru[3][2] $end
+     $var bit 1 : v_arru_arru[3][1] $end
     $upscope $end
    $upscope $end
    $attrbegin array unpacked bounds 17179869187 $end
    $scope sv_array v_arru_arrp $end
-    $var bit 2 9 v_arru_arrp[4] [2:1] $end
-    $var bit 2 : v_arru_arrp[3] [2:1] $end
+    $var bit 2 ; v_arru_arrp[4] [2:1] $end
+    $var bit 2 < v_arru_arrp[3] [2:1] $end
    $upscope $end
    $attrbegin array unpacked bounds 17179869187 $end
    $scope sv_array v_arru_strp $end
     $attrbegin pack packed members 2 $end
     $scope struct [4] $end
-     $var bit 1 ; b1 $end
-     $var bit 1 < b0 $end
-    $upscope $end
-    $attrbegin pack packed members 2 $end
-    $scope struct [3] $end
      $var bit 1 = b1 $end
      $var bit 1 > b0 $end
     $upscope $end
+    $attrbegin pack packed members 2 $end
+    $scope struct [3] $end
+     $var bit 1 ? b1 $end
+     $var bit 1 @ b0 $end
+    $upscope $end
    $upscope $end
-   $var real 64 ? v_real $end
+   $var real 64 A v_real $end
    $attrbegin array unpacked bounds 1 $end
    $scope sv_array v_arr_real $end
-    $var real 64 @ v_arr_real[0] $end
-    $var real 64 A v_arr_real[1] $end
+    $var real 64 B v_arr_real[0] $end
+    $var real 64 C v_arr_real[1] $end
    $upscope $end
-   $var longint 64 B v_chandle [63:0] $end
+   $var longint 64 D v_chandle [63:0] $end
    $attrbegin array packed bounds 4294967296 $end
    $scope sv_array v_str32x2 $end
     $attrbegin pack packed members 1 $end
     $scope struct [1] $end
-     $var logic 32 C data [31:0] $end
+     $var logic 32 E data [31:0] $end
     $upscope $end
     $attrbegin pack packed members 1 $end
     $scope struct [0] $end
-     $var logic 32 D data [31:0] $end
+     $var logic 32 F data [31:0] $end
     $upscope $end
    $upscope $end
    $attrbegin misc 07 "" 1 $end
-   $var int 32 E v_enumed [31:0] $end
+   $var int 32 G v_enumed [31:0] $end
    $attrbegin misc 07 "" 1 $end
-   $var int 32 F v_enumed2 [31:0] $end
+   $var int 32 H v_enumed2 [31:0] $end
    $attrbegin misc 07 "" 2 $end
-   $var logic 3 G v_enumb [2:0] $end
+   $var logic 3 I v_enumb [2:0] $end
    $attrbegin pack packed members 2 $end
    $scope struct v_enumb2_str $end
     $attrbegin misc 07 "" 2 $end
-    $var logic 3 H a [2:0] $end
+    $var logic 3 J a [2:0] $end
     $attrbegin misc 07 "" 2 $end
-    $var logic 3 I b [2:0] $end
+    $var logic 3 K b [2:0] $end
    $upscope $end
    $attrbegin array unpacked bounds -8589934592 $end
    $scope sv_array unpacked_array $end
-    $var logic 8 J unpacked_array[-2] [7:0] $end
-    $var logic 8 K unpacked_array[-1] [7:0] $end
-    $var logic 8 L unpacked_array[0] [7:0] $end
+    $var logic 8 L unpacked_array[-2] [7:0] $end
+    $var logic 8 M unpacked_array[-1] [7:0] $end
+    $var logic 8 N unpacked_array[0] [7:0] $end
    $upscope $end
-   $var bit 1 M LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
+   $var bit 1 O LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
   $upscope $end
  $upscope $end
 $enddefinitions $end
 #0
 $dumpvars
-0M
+0O
+b00000000 N
+b00000000 M
 b00000000 L
-b00000000 K
-b00000000 J
+b000 K
+b000 J
 b000 I
-b000 H
-b000 G
-b00000000000000000000000000000000 F
+b00000000000000000000000000000000 H
+b00000000000000000000000000000000 G
+b00000000000000000000000011111111 F
 b00000000000000000000000000000000 E
-b00000000000000000000000011111111 D
-b00000000000000000000000000000000 C
-b0000000000000000000000000000000000000000000000000000000000000000 B
+b0000000000000000000000000000000000000000000000000000000000000000 D
+r0 C
+r0 B
 r0 A
-r0 @
-r0 ?
+0@
+0?
 0>
 0=
-0<
-0;
-b00 :
-b00 9
+b00 <
+b00 ;
+0:
+09
 08
 07
 06
@@ -175,11 +186,11 @@ b00 9
 03
 02
 01
-00
-0/
+b00 0
+b00 /
 b00 .
-b00 -
-b00 ,
+0-
+0,
 0+
 0*
 0)
@@ -203,52 +214,56 @@ b00000000000000000000000000000001 #
 1)
 1*
 1+
-b11 ,
-b11 -
+1,
+1-
 b11 .
-1/
-10
+b11 /
+b11 0
 11
 12
-b11 9
-b11 :
-1;
-1<
+13
+14
+b11 ;
+b11 <
 1=
 1>
-r0.1 ?
-r0.2 @
-r0.3 A
-b00000000000000000000000000000001 C
-b00000000000000000000000011111110 D
+1?
+1@
+r0.1 A
+r0.2 B
+r0.3 C
 b00000000000000000000000000000001 E
-b00000000000000000000000000000010 F
-b111 G
+b00000000000000000000000011111110 F
+b00000000000000000000000000000001 G
+b00000000000000000000000000000010 H
+b111 I
 #15
 0"
 #20
 1"
-b110 G
-b00000000000000000000000000000100 F
+b110 I
+b00000000000000000000000000000100 H
+b00000000000000000000000000000010 G
+b00000000000000000000000011111101 F
 b00000000000000000000000000000010 E
-b00000000000000000000000011111101 D
-b00000000000000000000000000000010 C
-r0.6 A
-r0.4 @
-r0.2 ?
+r0.6 C
+r0.4 B
+r0.2 A
+0@
+0?
 0>
 0=
-0<
-0;
-b00 :
-b00 9
+b00 <
+b00 ;
+04
+03
 02
 01
-00
-0/
+b00 0
+b00 /
 b00 .
-b00 -
-b00 ,
+0-
+0,
 0+
 0*
 0)
@@ -258,14 +273,14 @@ b00 ,
 0%
 0$
 b00000000000000000000000000000010 #
-b111 H
-b111 I
+b111 J
+b111 K
 #25
 0"
 #30
 1"
-b110 I
-b110 H
+b110 K
+b110 J
 b00000000000000000000000000000011 #
 1$
 1%
@@ -275,52 +290,56 @@ b00000000000000000000000000000011 #
 1)
 1*
 1+
-b11 ,
-b11 -
+1,
+1-
 b11 .
-1/
-10
+b11 /
+b11 0
 11
 12
-b11 9
-b11 :
-1;
-1<
+13
+14
+b11 ;
+b11 <
 1=
 1>
-r0.3 ?
-r0.6000000000000001 @
-r0.8999999999999999 A
-b00000000000000000000000000000011 C
-b00000000000000000000000011111100 D
+1?
+1@
+r0.3 A
+r0.6000000000000001 B
+r0.8999999999999999 C
 b00000000000000000000000000000011 E
-b00000000000000000000000000000110 F
-b101 G
+b00000000000000000000000011111100 F
+b00000000000000000000000000000011 G
+b00000000000000000000000000000110 H
+b101 I
 #35
 0"
 #40
 1"
-b100 G
-b00000000000000000000000000001000 F
+b100 I
+b00000000000000000000000000001000 H
+b00000000000000000000000000000100 G
+b00000000000000000000000011111011 F
 b00000000000000000000000000000100 E
-b00000000000000000000000011111011 D
-b00000000000000000000000000000100 C
-r1.2 A
-r0.8 @
-r0.4 ?
+r1.2 C
+r0.8 B
+r0.4 A
+0@
+0?
 0>
 0=
-0<
-0;
-b00 :
-b00 9
+b00 <
+b00 ;
+04
+03
 02
 01
-00
-0/
+b00 0
+b00 /
 b00 .
-b00 -
-b00 ,
+0-
+0,
 0+
 0*
 0)
@@ -330,14 +349,14 @@ b00 ,
 0%
 0$
 b00000000000000000000000000000100 #
-b101 H
-b101 I
+b101 J
+b101 K
 #45
 0"
 #50
 1"
-b100 I
-b100 H
+b100 K
+b100 J
 b00000000000000000000000000000101 #
 1$
 1%
@@ -347,52 +366,56 @@ b00000000000000000000000000000101 #
 1)
 1*
 1+
-b11 ,
-b11 -
+1,
+1-
 b11 .
-1/
-10
+b11 /
+b11 0
 11
 12
-b11 9
-b11 :
-1;
-1<
+13
+14
+b11 ;
+b11 <
 1=
 1>
-r0.5 ?
-r1 @
-r1.5 A
-b00000000000000000000000000000101 C
-b00000000000000000000000011111010 D
+1?
+1@
+r0.5 A
+r1 B
+r1.5 C
 b00000000000000000000000000000101 E
-b00000000000000000000000000001010 F
-b011 G
+b00000000000000000000000011111010 F
+b00000000000000000000000000000101 G
+b00000000000000000000000000001010 H
+b011 I
 #55
 0"
 #60
 1"
-b010 G
-b00000000000000000000000000001100 F
+b010 I
+b00000000000000000000000000001100 H
+b00000000000000000000000000000110 G
+b00000000000000000000000011111001 F
 b00000000000000000000000000000110 E
-b00000000000000000000000011111001 D
-b00000000000000000000000000000110 C
-r1.8 A
-r1.2 @
-r0.6 ?
+r1.8 C
+r1.2 B
+r0.6 A
+0@
+0?
 0>
 0=
-0<
-0;
-b00 :
-b00 9
+b00 <
+b00 ;
+04
+03
 02
 01
-00
-0/
+b00 0
+b00 /
 b00 .
-b00 -
-b00 ,
+0-
+0,
 0+
 0*
 0)
@@ -402,6 +425,6 @@ b00 ,
 0%
 0$
 b00000000000000000000000000000110 #
-b011 H
-b011 I
+b011 J
+b011 K
 #64
diff --git a/test_regress/t/t_trace_complex_structs_sc_vcd.out b/test_regress/t/t_trace_complex_structs_sc_vcd.out
index de976b476..00299b60f 100644
--- a/test_regress/t/t_trace_complex_structs_sc_vcd.out
+++ b/test_regress/t/t_trace_complex_structs_sc_vcd.out
@@ -5,80 +5,84 @@ $timescale 1ps $end
    $var wire 1 " global_bit $end
   $upscope $end
   $scope module t $end
-   $var wire 1 F clk $end
+   $var wire 1 H clk $end
    $var wire 32 # cyc [31:0] $end
    $scope module v_strp $end
     $var wire 1 $ b1 $end
     $var wire 1 % b0 $end
    $upscope $end
+   $scope module v_strp2 $end
+    $var wire 1 & b1 $end
+    $var wire 1 ' b0 $end
+   $upscope $end
    $scope module v_strp_strp $end
     $scope module x1 $end
-     $var wire 1 & b1 $end
-     $var wire 1 ' b0 $end
-    $upscope $end
-    $scope module x0 $end
      $var wire 1 ( b1 $end
      $var wire 1 ) b0 $end
     $upscope $end
+    $scope module x0 $end
+     $var wire 1 * b1 $end
+     $var wire 1 + b0 $end
+    $upscope $end
    $upscope $end
    $scope module v_unip_strp $end
     $scope module x1 $end
-     $var wire 1 * b1 $end
-     $var wire 1 + b0 $end
+     $var wire 1 , b1 $end
+     $var wire 1 - b0 $end
     $upscope $end
     $scope module x0 $end
-     $var wire 1 * b1 $end
-     $var wire 1 + b0 $end
+     $var wire 1 , b1 $end
+     $var wire 1 - b0 $end
     $upscope $end
    $upscope $end
-   $var wire 2 , v_arrp [2:1] $end
-   $var wire 2 - v_arrp_arrp[4] [2:1] $end
-   $var wire 2 . v_arrp_arrp[3] [2:1] $end
+   $var wire 2 . v_arrp [2:1] $end
+   $var wire 2 / v_arrp_arrp[4] [2:1] $end
+   $var wire 2 0 v_arrp_arrp[3] [2:1] $end
    $scope module v_arrp_strp[4] $end
-    $var wire 1 / b1 $end
-    $var wire 1 0 b0 $end
-   $upscope $end
-   $scope module v_arrp_strp[3] $end
     $var wire 1 1 b1 $end
     $var wire 1 2 b0 $end
    $upscope $end
-   $var wire 1 G v_arru[2] $end
-   $var wire 1 H v_arru[1] $end
-   $var wire 1 I v_arru_arru[4][2] $end
-   $var wire 1 J v_arru_arru[4][1] $end
-   $var wire 1 K v_arru_arru[3][2] $end
-   $var wire 1 L v_arru_arru[3][1] $end
-   $var wire 2 3 v_arru_arrp[4] [2:1] $end
-   $var wire 2 4 v_arru_arrp[3] [2:1] $end
-   $scope module v_arru_strp[4] $end
-    $var wire 1 5 b1 $end
-    $var wire 1 6 b0 $end
+   $scope module v_arrp_strp[3] $end
+    $var wire 1 3 b1 $end
+    $var wire 1 4 b0 $end
    $upscope $end
-   $scope module v_arru_strp[3] $end
+   $var wire 1 I v_arru[2] $end
+   $var wire 1 J v_arru[1] $end
+   $var wire 1 K v_arru_arru[4][2] $end
+   $var wire 1 L v_arru_arru[4][1] $end
+   $var wire 1 M v_arru_arru[3][2] $end
+   $var wire 1 N v_arru_arru[3][1] $end
+   $var wire 2 5 v_arru_arrp[4] [2:1] $end
+   $var wire 2 6 v_arru_arrp[3] [2:1] $end
+   $scope module v_arru_strp[4] $end
     $var wire 1 7 b1 $end
     $var wire 1 8 b0 $end
    $upscope $end
-   $var real 64 9 v_real $end
-   $var real 64 ; v_arr_real[0] $end
-   $var real 64 = v_arr_real[1] $end
-   $var wire 64 M v_chandle [63:0] $end
+   $scope module v_arru_strp[3] $end
+    $var wire 1 9 b1 $end
+    $var wire 1 : b0 $end
+   $upscope $end
+   $var real 64 ; v_real $end
+   $var real 64 = v_arr_real[0] $end
+   $var real 64 ? v_arr_real[1] $end
+   $var wire 64 O v_chandle [63:0] $end
    $scope module v_str32x2[1] $end
-    $var wire 32 ? data [31:0] $end
+    $var wire 32 A data [31:0] $end
    $upscope $end
    $scope module v_str32x2[0] $end
-    $var wire 32 @ data [31:0] $end
+    $var wire 32 B data [31:0] $end
    $upscope $end
-   $var wire 32 A v_enumed [31:0] $end
-   $var wire 32 B v_enumed2 [31:0] $end
-   $var wire 3 C v_enumb [2:0] $end
+   $var wire 32 C v_enumed [31:0] $end
+   $var wire 32 D v_enumed2 [31:0] $end
+   $var wire 3 E v_enumb [2:0] $end
    $scope module v_enumb2_str $end
-    $var wire 3 D a [2:0] $end
-    $var wire 3 E b [2:0] $end
+    $var wire 3 F a [2:0] $end
+    $var wire 3 G b [2:0] $end
    $upscope $end
-   $var wire 8 O unpacked_array[-2] [7:0] $end
-   $var wire 8 P unpacked_array[-1] [7:0] $end
-   $var wire 8 Q unpacked_array[0] [7:0] $end
-   $var wire 1 R LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
+   $var wire 8 Q unpacked_array[-2] [7:0] $end
+   $var wire 8 R unpacked_array[-1] [7:0] $end
+   $var wire 8 S unpacked_array[0] [7:0] $end
+   $var wire 1 T LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
   $upscope $end
  $upscope $end
 $enddefinitions $end
@@ -95,41 +99,43 @@ b00000000000000000000000000000000 #
 0)
 0*
 0+
-b00 ,
-b00 -
+0,
+0-
 b00 .
-0/
-00
+b00 /
+b00 0
 01
 02
-b00 3
-b00 4
-05
-06
+03
+04
+b00 5
+b00 6
 07
 08
-r0 9
+09
+0:
 r0 ;
 r0 =
-b00000000000000000000000000000000 ?
-b00000000000000000000000011111111 @
+r0 ?
 b00000000000000000000000000000000 A
-b00000000000000000000000000000000 B
-b000 C
-b000 D
+b00000000000000000000000011111111 B
+b00000000000000000000000000000000 C
+b00000000000000000000000000000000 D
 b000 E
-0F
-0G
+b000 F
+b000 G
 0H
 0I
 0J
 0K
 0L
-b0000000000000000000000000000000000000000000000000000000000000000 M
-b00000000 O
-b00000000 P
+0M
+0N
+b0000000000000000000000000000000000000000000000000000000000000000 O
 b00000000 Q
-0R
+b00000000 R
+b00000000 S
+0T
 #10
 b00000000000000000000000000000001 #
 1$
@@ -140,30 +146,32 @@ b00000000000000000000000000000001 #
 1)
 1*
 1+
-b11 ,
-b11 -
+1,
+1-
 b11 .
-1/
-10
+b11 /
+b11 0
 11
 12
-b11 3
-b11 4
-15
-16
+13
+14
+b11 5
+b11 6
 17
 18
-r0.1 9
-r0.2 ;
-r0.3 =
-b00000000000000000000000000000001 ?
-b00000000000000000000000011111110 @
+19
+1:
+r0.1 ;
+r0.2 =
+r0.3 ?
 b00000000000000000000000000000001 A
-b00000000000000000000000000000010 B
-b111 C
-1F
+b00000000000000000000000011111110 B
+b00000000000000000000000000000001 C
+b00000000000000000000000000000010 D
+b111 E
+1H
 #15
-0F
+0H
 #20
 b00000000000000000000000000000010 #
 0$
@@ -174,32 +182,34 @@ b00000000000000000000000000000010 #
 0)
 0*
 0+
-b00 ,
-b00 -
+0,
+0-
 b00 .
-0/
-00
+b00 /
+b00 0
 01
 02
-b00 3
-b00 4
-05
-06
+03
+04
+b00 5
+b00 6
 07
 08
-r0.2 9
-r0.4 ;
-r0.6 =
-b00000000000000000000000000000010 ?
-b00000000000000000000000011111101 @
+09
+0:
+r0.2 ;
+r0.4 =
+r0.6 ?
 b00000000000000000000000000000010 A
-b00000000000000000000000000000100 B
-b110 C
-b111 D
-b111 E
-1F
+b00000000000000000000000011111101 B
+b00000000000000000000000000000010 C
+b00000000000000000000000000000100 D
+b110 E
+b111 F
+b111 G
+1H
 #25
-0F
+0H
 #30
 b00000000000000000000000000000011 #
 1$
@@ -210,32 +220,34 @@ b00000000000000000000000000000011 #
 1)
 1*
 1+
-b11 ,
-b11 -
+1,
+1-
 b11 .
-1/
-10
+b11 /
+b11 0
 11
 12
-b11 3
-b11 4
-15
-16
+13
+14
+b11 5
+b11 6
 17
 18
-r0.3 9
-r0.6000000000000001 ;
-r0.8999999999999999 =
-b00000000000000000000000000000011 ?
-b00000000000000000000000011111100 @
+19
+1:
+r0.3 ;
+r0.6000000000000001 =
+r0.8999999999999999 ?
 b00000000000000000000000000000011 A
-b00000000000000000000000000000110 B
-b101 C
-b110 D
-b110 E
-1F
+b00000000000000000000000011111100 B
+b00000000000000000000000000000011 C
+b00000000000000000000000000000110 D
+b101 E
+b110 F
+b110 G
+1H
 #35
-0F
+0H
 #40
 b00000000000000000000000000000100 #
 0$
@@ -246,32 +258,34 @@ b00000000000000000000000000000100 #
 0)
 0*
 0+
-b00 ,
-b00 -
+0,
+0-
 b00 .
-0/
-00
+b00 /
+b00 0
 01
 02
-b00 3
-b00 4
-05
-06
+03
+04
+b00 5
+b00 6
 07
 08
-r0.4 9
-r0.8 ;
-r1.2 =
-b00000000000000000000000000000100 ?
-b00000000000000000000000011111011 @
+09
+0:
+r0.4 ;
+r0.8 =
+r1.2 ?
 b00000000000000000000000000000100 A
-b00000000000000000000000000001000 B
-b100 C
-b101 D
-b101 E
-1F
+b00000000000000000000000011111011 B
+b00000000000000000000000000000100 C
+b00000000000000000000000000001000 D
+b100 E
+b101 F
+b101 G
+1H
 #45
-0F
+0H
 #50
 b00000000000000000000000000000101 #
 1$
@@ -282,32 +296,34 @@ b00000000000000000000000000000101 #
 1)
 1*
 1+
-b11 ,
-b11 -
+1,
+1-
 b11 .
-1/
-10
+b11 /
+b11 0
 11
 12
-b11 3
-b11 4
-15
-16
+13
+14
+b11 5
+b11 6
 17
 18
-r0.5 9
-r1 ;
-r1.5 =
-b00000000000000000000000000000101 ?
-b00000000000000000000000011111010 @
+19
+1:
+r0.5 ;
+r1 =
+r1.5 ?
 b00000000000000000000000000000101 A
-b00000000000000000000000000001010 B
-b011 C
-b100 D
-b100 E
-1F
+b00000000000000000000000011111010 B
+b00000000000000000000000000000101 C
+b00000000000000000000000000001010 D
+b011 E
+b100 F
+b100 G
+1H
 #55
-0F
+0H
 #60
 b00000000000000000000000000000110 #
 0$
@@ -318,28 +334,30 @@ b00000000000000000000000000000110 #
 0)
 0*
 0+
-b00 ,
-b00 -
+0,
+0-
 b00 .
-0/
-00
+b00 /
+b00 0
 01
 02
-b00 3
-b00 4
-05
-06
+03
+04
+b00 5
+b00 6
 07
 08
-r0.6 9
-r1.2 ;
-r1.8 =
-b00000000000000000000000000000110 ?
-b00000000000000000000000011111001 @
+09
+0:
+r0.6 ;
+r1.2 =
+r1.8 ?
 b00000000000000000000000000000110 A
-b00000000000000000000000000001100 B
-b010 C
-b011 D
-b011 E
-1F
+b00000000000000000000000011111001 B
+b00000000000000000000000000000110 C
+b00000000000000000000000000001100 D
+b010 E
+b011 F
+b011 G
+1H
 #64
diff --git a/test_regress/t/t_trace_dumpvars_dyn_0_cc_fst.out b/test_regress/t/t_trace_dumpvars_dyn_0_cc_fst.out
index 90f571fd3..4ee670260 100644
--- a/test_regress/t/t_trace_dumpvars_dyn_0_cc_fst.out
+++ b/test_regress/t/t_trace_dumpvars_dyn_0_cc_fst.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 14 09:17:08 2026
+Tue Apr 14 15:20:41 2026
 
 $end
 $version
diff --git a/test_regress/t/t_trace_dumpvars_dyn_0_cc_vcd.out b/test_regress/t/t_trace_dumpvars_dyn_0_cc_vcd.out
index 48e248b3d..e93f8da09 100644
--- a/test_regress/t/t_trace_dumpvars_dyn_0_cc_vcd.out
+++ b/test_regress/t/t_trace_dumpvars_dyn_0_cc_vcd.out
@@ -1,49 +1,48 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
-
  $scope module top $end
-  $var wire 1 , clk $end
+  $var wire 1 + clk $end
   $scope module t $end
-   $var wire 1 , clk $end
-   $var wire 32 # cyc [31:0] $end
+   $var wire 1 + clk $end
+   $var wire 32 " cyc [31:0] $end
    $scope module sub1a $end
-    $var wire 32 - ADD [31:0] $end
-    $var wire 32 # cyc [31:0] $end
-    $var wire 32 $ value [31:0] $end
+    $var wire 32 , ADD [31:0] $end
+    $var wire 32 " cyc [31:0] $end
+    $var wire 32 # value [31:0] $end
     $scope module sub2a $end
-     $var wire 32 . ADD [31:0] $end
-     $var wire 32 # cyc [31:0] $end
-     $var wire 32 % value [31:0] $end
+     $var wire 32 - ADD [31:0] $end
+     $var wire 32 " cyc [31:0] $end
+     $var wire 32 $ value [31:0] $end
     $upscope $end
     $scope module sub2b $end
-     $var wire 32 / ADD [31:0] $end
-     $var wire 32 # cyc [31:0] $end
-     $var wire 32 & value [31:0] $end
+     $var wire 32 . ADD [31:0] $end
+     $var wire 32 " cyc [31:0] $end
+     $var wire 32 % value [31:0] $end
     $upscope $end
     $scope module sub2c $end
-     $var wire 32 0 ADD [31:0] $end
-     $var wire 32 # cyc [31:0] $end
-     $var wire 32 ' value [31:0] $end
+     $var wire 32 / ADD [31:0] $end
+     $var wire 32 " cyc [31:0] $end
+     $var wire 32 & value [31:0] $end
     $upscope $end
    $upscope $end
    $scope module sub1b $end
-    $var wire 32 1 ADD [31:0] $end
-    $var wire 32 # cyc [31:0] $end
-    $var wire 32 ( value [31:0] $end
+    $var wire 32 0 ADD [31:0] $end
+    $var wire 32 " cyc [31:0] $end
+    $var wire 32 ' value [31:0] $end
     $scope module sub2a $end
-     $var wire 32 2 ADD [31:0] $end
-     $var wire 32 # cyc [31:0] $end
-     $var wire 32 ) value [31:0] $end
+     $var wire 32 1 ADD [31:0] $end
+     $var wire 32 " cyc [31:0] $end
+     $var wire 32 ( value [31:0] $end
     $upscope $end
     $scope module sub2b $end
-     $var wire 32 3 ADD [31:0] $end
-     $var wire 32 # cyc [31:0] $end
-     $var wire 32 * value [31:0] $end
+     $var wire 32 2 ADD [31:0] $end
+     $var wire 32 " cyc [31:0] $end
+     $var wire 32 ) value [31:0] $end
     $upscope $end
     $scope module sub2c $end
-     $var wire 32 4 ADD [31:0] $end
-     $var wire 32 # cyc [31:0] $end
-     $var wire 32 + value [31:0] $end
+     $var wire 32 3 ADD [31:0] $end
+     $var wire 32 " cyc [31:0] $end
+     $var wire 32 * value [31:0] $end
     $upscope $end
    $upscope $end
   $upscope $end
@@ -52,151 +51,151 @@ $enddefinitions $end
 
 
 #0
-b00000000000000000000000000000000 #
-b00000000000000000000000000001010 $
-b00000000000000000000000000001011 %
-b00000000000000000000000000001100 &
-b00000000000000000000000000001101 '
-b00000000000000000000000000010100 (
-b00000000000000000000000000010101 )
-b00000000000000000000000000010110 *
-b00000000000000000000000000010111 +
-0,
-b00000000000000000000000000001010 -
-b00000000000000000000000000001011 .
-b00000000000000000000000000001100 /
-b00000000000000000000000000001101 0
-b00000000000000000000000000010100 1
-b00000000000000000000000000010101 2
-b00000000000000000000000000010110 3
-b00000000000000000000000000010111 4
-#1
-b00000000000000000000000000000001 #
+b00000000000000000000000000000000 "
+b00000000000000000000000000001010 #
 b00000000000000000000000000001011 $
 b00000000000000000000000000001100 %
 b00000000000000000000000000001101 &
-b00000000000000000000000000001110 '
+b00000000000000000000000000010100 '
 b00000000000000000000000000010101 (
 b00000000000000000000000000010110 )
 b00000000000000000000000000010111 *
-b00000000000000000000000000011000 +
-1,
-#2
-0,
-#3
-b00000000000000000000000000000010 #
+0+
+b00000000000000000000000000001010 ,
+b00000000000000000000000000001011 -
+b00000000000000000000000000001100 .
+b00000000000000000000000000001101 /
+b00000000000000000000000000010100 0
+b00000000000000000000000000010101 1
+b00000000000000000000000000010110 2
+b00000000000000000000000000010111 3
+#1
+b00000000000000000000000000000001 "
+b00000000000000000000000000001011 #
 b00000000000000000000000000001100 $
 b00000000000000000000000000001101 %
 b00000000000000000000000000001110 &
-b00000000000000000000000000001111 '
+b00000000000000000000000000010101 '
 b00000000000000000000000000010110 (
 b00000000000000000000000000010111 )
 b00000000000000000000000000011000 *
-b00000000000000000000000000011001 +
-1,
-#4
-0,
-#5
-b00000000000000000000000000000011 #
+1+
+#2
+0+
+#3
+b00000000000000000000000000000010 "
+b00000000000000000000000000001100 #
 b00000000000000000000000000001101 $
 b00000000000000000000000000001110 %
 b00000000000000000000000000001111 &
-b00000000000000000000000000010000 '
+b00000000000000000000000000010110 '
 b00000000000000000000000000010111 (
 b00000000000000000000000000011000 )
 b00000000000000000000000000011001 *
-b00000000000000000000000000011010 +
-1,
-#6
-0,
-#7
-b00000000000000000000000000000100 #
+1+
+#4
+0+
+#5
+b00000000000000000000000000000011 "
+b00000000000000000000000000001101 #
 b00000000000000000000000000001110 $
 b00000000000000000000000000001111 %
 b00000000000000000000000000010000 &
-b00000000000000000000000000010001 '
+b00000000000000000000000000010111 '
 b00000000000000000000000000011000 (
 b00000000000000000000000000011001 )
 b00000000000000000000000000011010 *
-b00000000000000000000000000011011 +
-1,
-#8
-0,
-#9
-b00000000000000000000000000000101 #
+1+
+#6
+0+
+#7
+b00000000000000000000000000000100 "
+b00000000000000000000000000001110 #
 b00000000000000000000000000001111 $
 b00000000000000000000000000010000 %
 b00000000000000000000000000010001 &
-b00000000000000000000000000010010 '
+b00000000000000000000000000011000 '
 b00000000000000000000000000011001 (
 b00000000000000000000000000011010 )
 b00000000000000000000000000011011 *
-b00000000000000000000000000011100 +
-1,
-#10
-0,
-#11
-b00000000000000000000000000000110 #
+1+
+#8
+0+
+#9
+b00000000000000000000000000000101 "
+b00000000000000000000000000001111 #
 b00000000000000000000000000010000 $
 b00000000000000000000000000010001 %
 b00000000000000000000000000010010 &
-b00000000000000000000000000010011 '
+b00000000000000000000000000011001 '
 b00000000000000000000000000011010 (
 b00000000000000000000000000011011 )
 b00000000000000000000000000011100 *
-b00000000000000000000000000011101 +
-1,
-#12
-0,
-#13
-b00000000000000000000000000000111 #
+1+
+#10
+0+
+#11
+b00000000000000000000000000000110 "
+b00000000000000000000000000010000 #
 b00000000000000000000000000010001 $
 b00000000000000000000000000010010 %
 b00000000000000000000000000010011 &
-b00000000000000000000000000010100 '
+b00000000000000000000000000011010 '
 b00000000000000000000000000011011 (
 b00000000000000000000000000011100 )
 b00000000000000000000000000011101 *
-b00000000000000000000000000011110 +
-1,
-#14
-0,
-#15
-b00000000000000000000000000001000 #
+1+
+#12
+0+
+#13
+b00000000000000000000000000000111 "
+b00000000000000000000000000010001 #
 b00000000000000000000000000010010 $
 b00000000000000000000000000010011 %
 b00000000000000000000000000010100 &
-b00000000000000000000000000010101 '
+b00000000000000000000000000011011 '
 b00000000000000000000000000011100 (
 b00000000000000000000000000011101 )
 b00000000000000000000000000011110 *
-b00000000000000000000000000011111 +
-1,
-#16
-0,
-#17
-b00000000000000000000000000001001 #
+1+
+#14
+0+
+#15
+b00000000000000000000000000001000 "
+b00000000000000000000000000010010 #
 b00000000000000000000000000010011 $
 b00000000000000000000000000010100 %
 b00000000000000000000000000010101 &
-b00000000000000000000000000010110 '
+b00000000000000000000000000011100 '
 b00000000000000000000000000011101 (
 b00000000000000000000000000011110 )
 b00000000000000000000000000011111 *
-b00000000000000000000000000100000 +
-1,
-#18
-0,
-#19
-b00000000000000000000000000001010 #
+1+
+#16
+0+
+#17
+b00000000000000000000000000001001 "
+b00000000000000000000000000010011 #
 b00000000000000000000000000010100 $
 b00000000000000000000000000010101 %
 b00000000000000000000000000010110 &
-b00000000000000000000000000010111 '
+b00000000000000000000000000011101 '
 b00000000000000000000000000011110 (
 b00000000000000000000000000011111 )
 b00000000000000000000000000100000 *
-b00000000000000000000000000100001 +
-1,
+1+
+#18
+0+
+#19
+b00000000000000000000000000001010 "
+b00000000000000000000000000010100 #
+b00000000000000000000000000010101 $
+b00000000000000000000000000010110 %
+b00000000000000000000000000010111 &
+b00000000000000000000000000011110 '
+b00000000000000000000000000011111 (
+b00000000000000000000000000100000 )
+b00000000000000000000000000100001 *
+1+
 #20
-0,
+0+
diff --git a/test_regress/t/t_trace_dumpvars_dyn_1_cc_fst.out b/test_regress/t/t_trace_dumpvars_dyn_1_cc_fst.out
index 724c2963d..f85f30bd9 100644
--- a/test_regress/t/t_trace_dumpvars_dyn_1_cc_fst.out
+++ b/test_regress/t/t_trace_dumpvars_dyn_1_cc_fst.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 14 09:17:06 2026
+Tue Apr 14 15:20:41 2026
 
 $end
 $version
diff --git a/test_regress/t/t_trace_dumpvars_dyn_1_cc_vcd.out b/test_regress/t/t_trace_dumpvars_dyn_1_cc_vcd.out
index bc3778e83..b97854e4a 100644
--- a/test_regress/t/t_trace_dumpvars_dyn_1_cc_vcd.out
+++ b/test_regress/t/t_trace_dumpvars_dyn_1_cc_vcd.out
@@ -2,11 +2,11 @@ $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module top $end
   $scope module t $end
-   $var wire 32 # cyc [31:0] $end
+   $var wire 32 " cyc [31:0] $end
    $scope module sub1a $end
-    $var wire 32 - ADD [31:0] $end
-    $var wire 32 # cyc [31:0] $end
-    $var wire 32 $ value [31:0] $end
+    $var wire 32 , ADD [31:0] $end
+    $var wire 32 " cyc [31:0] $end
+    $var wire 32 # value [31:0] $end
     $scope module sub2a $end
     $upscope $end
     $scope module sub2b $end
@@ -15,23 +15,23 @@ $timescale 1ps $end
     $upscope $end
    $upscope $end
    $scope module sub1b $end
-    $var wire 32 1 ADD [31:0] $end
-    $var wire 32 # cyc [31:0] $end
-    $var wire 32 ( value [31:0] $end
+    $var wire 32 0 ADD [31:0] $end
+    $var wire 32 " cyc [31:0] $end
+    $var wire 32 ' value [31:0] $end
     $scope module sub2a $end
-     $var wire 32 2 ADD [31:0] $end
-     $var wire 32 # cyc [31:0] $end
-     $var wire 32 ) value [31:0] $end
+     $var wire 32 1 ADD [31:0] $end
+     $var wire 32 " cyc [31:0] $end
+     $var wire 32 ( value [31:0] $end
     $upscope $end
     $scope module sub2b $end
-     $var wire 32 3 ADD [31:0] $end
-     $var wire 32 # cyc [31:0] $end
-     $var wire 32 * value [31:0] $end
+     $var wire 32 2 ADD [31:0] $end
+     $var wire 32 " cyc [31:0] $end
+     $var wire 32 ) value [31:0] $end
     $upscope $end
     $scope module sub2c $end
-     $var wire 32 4 ADD [31:0] $end
-     $var wire 32 # cyc [31:0] $end
-     $var wire 32 + value [31:0] $end
+     $var wire 32 3 ADD [31:0] $end
+     $var wire 32 " cyc [31:0] $end
+     $var wire 32 * value [31:0] $end
     $upscope $end
    $upscope $end
   $upscope $end
@@ -40,85 +40,85 @@ $enddefinitions $end
 
 
 #0
-b00000000000000000000000000000000 #
-b00000000000000000000000000001010 $
-b00000000000000000000000000010100 (
-b00000000000000000000000000010101 )
-b00000000000000000000000000010110 *
-b00000000000000000000000000010111 +
-b00000000000000000000000000001010 -
-b00000000000000000000000000010100 1
-b00000000000000000000000000010101 2
-b00000000000000000000000000010110 3
-b00000000000000000000000000010111 4
-#1
-b00000000000000000000000000000001 #
-b00000000000000000000000000001011 $
+b00000000000000000000000000000000 "
+b00000000000000000000000000001010 #
+b00000000000000000000000000010100 '
 b00000000000000000000000000010101 (
 b00000000000000000000000000010110 )
 b00000000000000000000000000010111 *
-b00000000000000000000000000011000 +
-#3
-b00000000000000000000000000000010 #
-b00000000000000000000000000001100 $
+b00000000000000000000000000001010 ,
+b00000000000000000000000000010100 0
+b00000000000000000000000000010101 1
+b00000000000000000000000000010110 2
+b00000000000000000000000000010111 3
+#1
+b00000000000000000000000000000001 "
+b00000000000000000000000000001011 #
+b00000000000000000000000000010101 '
 b00000000000000000000000000010110 (
 b00000000000000000000000000010111 )
 b00000000000000000000000000011000 *
-b00000000000000000000000000011001 +
-#5
-b00000000000000000000000000000011 #
-b00000000000000000000000000001101 $
+#3
+b00000000000000000000000000000010 "
+b00000000000000000000000000001100 #
+b00000000000000000000000000010110 '
 b00000000000000000000000000010111 (
 b00000000000000000000000000011000 )
 b00000000000000000000000000011001 *
-b00000000000000000000000000011010 +
-#7
-b00000000000000000000000000000100 #
-b00000000000000000000000000001110 $
+#5
+b00000000000000000000000000000011 "
+b00000000000000000000000000001101 #
+b00000000000000000000000000010111 '
 b00000000000000000000000000011000 (
 b00000000000000000000000000011001 )
 b00000000000000000000000000011010 *
-b00000000000000000000000000011011 +
-#9
-b00000000000000000000000000000101 #
-b00000000000000000000000000001111 $
+#7
+b00000000000000000000000000000100 "
+b00000000000000000000000000001110 #
+b00000000000000000000000000011000 '
 b00000000000000000000000000011001 (
 b00000000000000000000000000011010 )
 b00000000000000000000000000011011 *
-b00000000000000000000000000011100 +
-#11
-b00000000000000000000000000000110 #
-b00000000000000000000000000010000 $
+#9
+b00000000000000000000000000000101 "
+b00000000000000000000000000001111 #
+b00000000000000000000000000011001 '
 b00000000000000000000000000011010 (
 b00000000000000000000000000011011 )
 b00000000000000000000000000011100 *
-b00000000000000000000000000011101 +
-#13
-b00000000000000000000000000000111 #
-b00000000000000000000000000010001 $
+#11
+b00000000000000000000000000000110 "
+b00000000000000000000000000010000 #
+b00000000000000000000000000011010 '
 b00000000000000000000000000011011 (
 b00000000000000000000000000011100 )
 b00000000000000000000000000011101 *
-b00000000000000000000000000011110 +
-#15
-b00000000000000000000000000001000 #
-b00000000000000000000000000010010 $
+#13
+b00000000000000000000000000000111 "
+b00000000000000000000000000010001 #
+b00000000000000000000000000011011 '
 b00000000000000000000000000011100 (
 b00000000000000000000000000011101 )
 b00000000000000000000000000011110 *
-b00000000000000000000000000011111 +
-#17
-b00000000000000000000000000001001 #
-b00000000000000000000000000010011 $
+#15
+b00000000000000000000000000001000 "
+b00000000000000000000000000010010 #
+b00000000000000000000000000011100 '
 b00000000000000000000000000011101 (
 b00000000000000000000000000011110 )
 b00000000000000000000000000011111 *
-b00000000000000000000000000100000 +
-#19
-b00000000000000000000000000001010 #
-b00000000000000000000000000010100 $
+#17
+b00000000000000000000000000001001 "
+b00000000000000000000000000010011 #
+b00000000000000000000000000011101 '
 b00000000000000000000000000011110 (
 b00000000000000000000000000011111 )
 b00000000000000000000000000100000 *
-b00000000000000000000000000100001 +
+#19
+b00000000000000000000000000001010 "
+b00000000000000000000000000010100 #
+b00000000000000000000000000011110 '
+b00000000000000000000000000011111 (
+b00000000000000000000000000100000 )
+b00000000000000000000000000100001 *
 #20
diff --git a/test_regress/t/t_trace_ena_cc.out b/test_regress/t/t_trace_ena_cc.out
index adaccf6ff..c355255ce 100644
--- a/test_regress/t/t_trace_ena_cc.out
+++ b/test_regress/t/t_trace_ena_cc.out
@@ -1,86 +1,86 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module top $end
-  $var wire 1 # clk $end
+  $var wire 1 & clk $end
   $scope module t $end
-   $var wire 1 # clk $end
-   $var wire 32 $ cyc [31:0] $end
-   $var wire 32 % c_trace_on [31:0] $end
-   $var real 64 & r $end
+   $var wire 1 & clk $end
+   $var wire 32 " cyc [31:0] $end
+   $var wire 32 # c_trace_on [31:0] $end
+   $var real 64 $ r $end
   $upscope $end
  $upscope $end
 $enddefinitions $end
 
 
 #0
-0#
-b00000000000000000000000000000001 $
-b00000000000000000000000000000000 %
-r0 &
+b00000000000000000000000000000001 "
+b00000000000000000000000000000000 #
+r0 $
+0&
 #10
-1#
-b00000000000000000000000000000010 $
-r0.1 &
+b00000000000000000000000000000010 "
+r0.1 $
+1&
 #15
-0#
+0&
 #20
-1#
-b00000000000000000000000000000011 $
-b00000000000000000000000000000001 %
-r0.2 &
+b00000000000000000000000000000011 "
+b00000000000000000000000000000001 #
+r0.2 $
+1&
 #25
-0#
+0&
 #30
-1#
-b00000000000000000000000000000100 $
-b00000000000000000000000000000010 %
-r0.3 &
+b00000000000000000000000000000100 "
+b00000000000000000000000000000010 #
+r0.3 $
+1&
 #35
-0#
+0&
 #40
-1#
-b00000000000000000000000000000101 $
-b00000000000000000000000000000011 %
-r0.4 &
+b00000000000000000000000000000101 "
+b00000000000000000000000000000011 #
+r0.4 $
+1&
 #45
-0#
+0&
 #50
-1#
-b00000000000000000000000000000110 $
-b00000000000000000000000000000100 %
-r0.5 &
+b00000000000000000000000000000110 "
+b00000000000000000000000000000100 #
+r0.5 $
+1&
 #55
-0#
+0&
 #60
-1#
-b00000000000000000000000000000111 $
-b00000000000000000000000000000101 %
-r0.6 &
+b00000000000000000000000000000111 "
+b00000000000000000000000000000101 #
+r0.6 $
+1&
 #65
-0#
+0&
 #70
-1#
-b00000000000000000000000000001000 $
-b00000000000000000000000000000110 %
-r0.7 &
+b00000000000000000000000000001000 "
+b00000000000000000000000000000110 #
+r0.7 $
+1&
 #75
-0#
+0&
 #80
-1#
-b00000000000000000000000000001001 $
-b00000000000000000000000000000111 %
-r0.7999999999999999 &
+b00000000000000000000000000001001 "
+b00000000000000000000000000000111 #
+r0.7999999999999999 $
+1&
 #85
-0#
+0&
 #90
-1#
-b00000000000000000000000000001010 $
-b00000000000000000000000000001000 %
-r0.8999999999999999 &
+b00000000000000000000000000001010 "
+b00000000000000000000000000001000 #
+r0.8999999999999999 $
+1&
 #95
-0#
+0&
 #100
-1#
-b00000000000000000000000000001011 $
-b00000000000000000000000000001001 %
-r0.9999999999999999 &
+b00000000000000000000000000001011 "
+b00000000000000000000000000001001 #
+r0.9999999999999999 $
+1&
diff --git a/test_regress/t/t_trace_ena_sc.out b/test_regress/t/t_trace_ena_sc.out
index cb655694a..6354fa1f2 100644
--- a/test_regress/t/t_trace_ena_sc.out
+++ b/test_regress/t/t_trace_ena_sc.out
@@ -2,85 +2,85 @@ $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module top $end
   $scope module t $end
-   $var wire 1 # clk $end
-   $var wire 32 $ cyc [31:0] $end
-   $var wire 32 % c_trace_on [31:0] $end
-   $var real 64 & r $end
+   $var wire 1 & clk $end
+   $var wire 32 " cyc [31:0] $end
+   $var wire 32 # c_trace_on [31:0] $end
+   $var real 64 $ r $end
   $upscope $end
  $upscope $end
 $enddefinitions $end
 
 
 #0
-0#
-b00000000000000000000000000000001 $
-b00000000000000000000000000000000 %
-r0 &
+b00000000000000000000000000000001 "
+b00000000000000000000000000000000 #
+r0 $
+0&
 #10
-1#
-b00000000000000000000000000000010 $
-r0.1 &
+b00000000000000000000000000000010 "
+r0.1 $
+1&
 #15
-0#
+0&
 #20
-1#
-b00000000000000000000000000000011 $
-b00000000000000000000000000000001 %
-r0.2 &
+b00000000000000000000000000000011 "
+b00000000000000000000000000000001 #
+r0.2 $
+1&
 #25
-0#
+0&
 #30
-1#
-b00000000000000000000000000000100 $
-b00000000000000000000000000000010 %
-r0.3 &
+b00000000000000000000000000000100 "
+b00000000000000000000000000000010 #
+r0.3 $
+1&
 #35
-0#
+0&
 #40
-1#
-b00000000000000000000000000000101 $
-b00000000000000000000000000000011 %
-r0.4 &
+b00000000000000000000000000000101 "
+b00000000000000000000000000000011 #
+r0.4 $
+1&
 #45
-0#
+0&
 #50
-1#
-b00000000000000000000000000000110 $
-b00000000000000000000000000000100 %
-r0.5 &
+b00000000000000000000000000000110 "
+b00000000000000000000000000000100 #
+r0.5 $
+1&
 #55
-0#
+0&
 #60
-1#
-b00000000000000000000000000000111 $
-b00000000000000000000000000000101 %
-r0.6 &
+b00000000000000000000000000000111 "
+b00000000000000000000000000000101 #
+r0.6 $
+1&
 #65
-0#
+0&
 #70
-1#
-b00000000000000000000000000001000 $
-b00000000000000000000000000000110 %
-r0.7 &
+b00000000000000000000000000001000 "
+b00000000000000000000000000000110 #
+r0.7 $
+1&
 #75
-0#
+0&
 #80
-1#
-b00000000000000000000000000001001 $
-b00000000000000000000000000000111 %
-r0.7999999999999999 &
+b00000000000000000000000000001001 "
+b00000000000000000000000000000111 #
+r0.7999999999999999 $
+1&
 #85
-0#
+0&
 #90
-1#
-b00000000000000000000000000001010 $
-b00000000000000000000000000001000 %
-r0.8999999999999999 &
+b00000000000000000000000000001010 "
+b00000000000000000000000000001000 #
+r0.8999999999999999 $
+1&
 #95
-0#
+0&
 #100
-1#
-b00000000000000000000000000001011 $
-b00000000000000000000000000001001 %
-r0.9999999999999999 &
+b00000000000000000000000000001011 "
+b00000000000000000000000000001001 #
+r0.9999999999999999 $
+1&
 #104
diff --git a/test_regress/t/t_trace_enum_fst.out b/test_regress/t/t_trace_enum_fst.out
index c79b5dc2b..96a7024b8 100644
--- a/test_regress/t/t_trace_enum_fst.out
+++ b/test_regress/t/t_trace_enum_fst.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 14 09:16:43 2026
+Tue Apr 14 15:20:42 2026
 
 $end
 $version
@@ -12,8 +12,6 @@ $end
   $attrbegin misc 07 $unit::state_t 4 VAL_A VAL_B VAL_C VAL_D 00 01 10 11 1 $end
   $attrbegin misc 07 t.other_state_t 3 VAL_X VAL_Y VAL_Z 00 01 10 2 $end
   $var wire 1 ! clk $end
-  $scope module $unit $end
-  $upscope $end
   $scope module t $end
    $var wire 1 ! clk $end
    $attrbegin misc 07 "" 1 $end
diff --git a/test_regress/t/t_trace_enum_saif.out b/test_regress/t/t_trace_enum_saif.out
index 7bf7fbe33..b312c271c 100644
--- a/test_regress/t/t_trace_enum_saif.out
+++ b/test_regress/t/t_trace_enum_saif.out
@@ -10,8 +10,6 @@
   (NET
    (clk (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
   )
-  (INSTANCE $unit
-  )
   (INSTANCE t
    (NET
     (clk (T0 10) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
diff --git a/test_regress/t/t_trace_enum_vcd.out b/test_regress/t/t_trace_enum_vcd.out
index 756f1e35f..cf684b362 100644
--- a/test_regress/t/t_trace_enum_vcd.out
+++ b/test_regress/t/t_trace_enum_vcd.out
@@ -2,8 +2,6 @@ $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module top $end
   $var wire 1 " clk $end
-  $scope module $unit $end
-  $upscope $end
   $scope module t $end
    $var wire 1 " clk $end
    $var wire 2 # v_enumed [1:0] $end
diff --git a/test_regress/t/t_trace_event_fst.out b/test_regress/t/t_trace_event_fst.out
index 6bfcf4f55..685079700 100644
--- a/test_regress/t/t_trace_event_fst.out
+++ b/test_regress/t/t_trace_event_fst.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 14 09:16:50 2026
+Tue Apr 14 15:20:42 2026
 
 $end
 $version
diff --git a/test_regress/t/t_trace_event_vcd.out b/test_regress/t/t_trace_event_vcd.out
index 13b11089b..2dfe98b6f 100644
--- a/test_regress/t/t_trace_event_vcd.out
+++ b/test_regress/t/t_trace_event_vcd.out
@@ -1,69 +1,69 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module t $end
-  $var event 1 # ev_test $end
-  $var wire 32 $ i [31:0] $end
-  $var wire 1 % toggle $end
-  $var wire 1 & clk $end
+  $var event 1 " ev_test $end
+  $var wire 32 # i [31:0] $end
+  $var wire 1 $ toggle $end
+  $var wire 1 % clk $end
  $upscope $end
 $enddefinitions $end
 
 
 #0
-b00000000000000000000000000000000 $
+b00000000000000000000000000000000 #
+0$
 0%
-0&
 #10
-b00000000000000000000000000000001 $
-1&
-#20
-0&
-#30
-b00000000000000000000000000000010 $
-1&
-#40
-0&
-#50
-b00000000000000000000000000000011 $
-1&
-#60
-0&
-#70
-b00000000000000000000000000000100 $
-1&
-#80
-0&
-#90
-b00000000000000000000000000000101 $
-1&
-#100
-0&
-#110
-1#
-b00000000000000000000000000000110 $
+b00000000000000000000000000000001 #
+1%
+#20
+0%
+#30
+b00000000000000000000000000000010 #
+1%
+#40
+0%
+#50
+b00000000000000000000000000000011 #
+1%
+#60
+0%
+#70
+b00000000000000000000000000000100 #
+1%
+#80
+0%
+#90
+b00000000000000000000000000000101 #
+1%
+#100
+0%
+#110
+1"
+b00000000000000000000000000000110 #
+1$
 1%
-1&
 #120
-0&
+0%
 #130
-b00000000000000000000000000000111 $
-1&
+b00000000000000000000000000000111 #
+1%
 #140
-0&
+0%
 #150
-b00000000000000000000000000001000 $
-1&
+b00000000000000000000000000001000 #
+1%
 #160
-0&
+0%
 #170
-b00000000000000000000000000001001 $
-1&
+b00000000000000000000000000001001 #
+1%
 #180
-0&
+0%
 #190
-b00000000000000000000000000001010 $
-1&
+b00000000000000000000000000001010 #
+1%
 #200
-0&
+0%
 #210
-1&
+1%
diff --git a/test_regress/t/t_trace_hier_block_default_cc_fst.out b/test_regress/t/t_trace_hier_block_default_cc_fst.out
index db6bb7c2f..6793e5bb6 100644
--- a/test_regress/t/t_trace_hier_block_default_cc_fst.out
+++ b/test_regress/t/t_trace_hier_block_default_cc_fst.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 14 09:16:56 2026
+Tue Apr 14 17:15:24 2026
 
 $end
 $version
@@ -80,1192 +80,1192 @@ $end
      $var wire 1 4 clk $end
      $var wire 8 5 in [7:0] $end
      $var wire 8 6 out [7:0] $end
-     $var logic 8 6 ff [7:0] $end
+     $var logic 8 7 ff [7:0] $end
     $upscope $end
    $upscope $end
    $scope module i_sub1 $end
     $attrbegin misc 07 $unit::enum_t 4 enum_val_0 enum_val_1 enum_val_2 enum_val_3 00 01 10 11 2 $end
-    $var wire 1 7 clk $end
-    $var wire 8 8 in [11:4] $end
-    $var wire 8 9 out [7:0] $end
-    $var logic 8 9 ff [7:0] $end
+    $var wire 1 8 clk $end
+    $var wire 8 9 in [11:4] $end
+    $var wire 8 : out [7:0] $end
+    $var logic 8 ; ff [7:0] $end
     $attrbegin misc 07 "" 2 $end
-    $var logic 2 : enum_v [1:0] $end
+    $var logic 2 < enum_v [1:0] $end
    $upscope $end
    $scope module i_sub2 $end
     $attrbegin misc 07 $unit::alt_enum_t 4 alt_enum_0 alt_enum_1 alt_enum_2 alt_enum_3 00 01 10 11 3 $end
     $attrbegin misc 07 $unit::enum_t 4 enum_val_0 enum_val_1 enum_val_2 enum_val_3 00 01 10 11 4 $end
-    $var wire 1 ; clk $end
-    $var wire 8 < in [7:0] $end
-    $var wire 8 = out [7:0] $end
-    $var logic 8 > ff [7:0] $end
+    $var wire 1 = clk $end
+    $var wire 8 > in [7:0] $end
+    $var wire 8 ? out [7:0] $end
+    $var logic 8 @ ff [7:0] $end
     $attrbegin misc 07 "" 3 $end
-    $var logic 2 ? alt_enum_v [1:0] $end
+    $var logic 2 A alt_enum_v [1:0] $end
     $scope module i_sub3 $end
-     $var wire 8 > in_wire [7:0] $end
-     $var wire 8 @ out_1 [7:0] $end
-     $var wire 8 A out_2 [7:0] $end
+     $var wire 8 @ in_wire [7:0] $end
+     $var wire 8 B out_1 [7:0] $end
+     $var wire 8 C out_2 [7:0] $end
      $scope module i_sub3 $end
-      $var parameter 8 B P0 [7:0] $end
+      $var parameter 8 D P0 [7:0] $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array UNPACKED_ARRAY $end
-       $var parameter 32 C UNPACKED_ARRAY[0] [31:0] $end
-       $var parameter 32 D UNPACKED_ARRAY[1] [31:0] $end
+       $var parameter 32 E UNPACKED_ARRAY[0] [31:0] $end
+       $var parameter 32 F UNPACKED_ARRAY[1] [31:0] $end
       $upscope $end
-      $var parameter 16 E UNUSED [15:0] $end
+      $var parameter 16 G UNUSED [15:0] $end
       $attrbegin misc 07 "" 4 $end
-      $var parameter 2 F ENUM [1:0] $end
-      $var wire 1 ; clk $end
-      $var wire 8 > in [7:0] $end
-      $var wire 8 @ out [7:0] $end
-      $var logic 8 G ff [7:0] $end
-      $var wire 8 @ out4 [7:0] $end
-      $var wire 8 H out4_2 [7:0] $end
+      $var parameter 2 H ENUM [1:0] $end
+      $var wire 1 = clk $end
+      $var wire 8 @ in [7:0] $end
+      $var wire 8 B out [7:0] $end
+      $var logic 8 I ff [7:0] $end
+      $var wire 8 B out4 [7:0] $end
+      $var wire 8 J out4_2 [7:0] $end
       $scope module i_sub4_0 $end
-       $var parameter 32 I P0 [31:0] $end
-       $var real_parameter 64 J P1 $end
-       $var real_parameter 64 K P3 $end
-       $var wire 1 ; clk $end
-       $var wire 8 G in [7:0] $end
-       $var wire 8 @ out [7:0] $end
-       $var logic 8 @ ff [7:0] $end
+       $var parameter 32 K P0 [31:0] $end
+       $var real_parameter 64 L P1 $end
+       $var real_parameter 64 M P3 $end
+       $var wire 1 = clk $end
+       $var wire 8 N in [7:0] $end
+       $var wire 8 B out [7:0] $end
+       $var logic 8 B ff [7:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array sub5_in $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [0] $end
-         $var logic 128 L sub5_in[0][0] [127:0] $end
-         $var logic 128 M sub5_in[0][1] [127:0] $end
-         $var logic 128 N sub5_in[0][2] [127:0] $end
+         $var logic 128 O sub5_in[0][0] [127:0] $end
+         $var logic 128 P sub5_in[0][1] [127:0] $end
+         $var logic 128 Q sub5_in[0][2] [127:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [1] $end
-         $var logic 128 O sub5_in[1][0] [127:0] $end
-         $var logic 128 P sub5_in[1][1] [127:0] $end
-         $var logic 128 Q sub5_in[1][2] [127:0] $end
+         $var logic 128 R sub5_in[1][0] [127:0] $end
+         $var logic 128 S sub5_in[1][1] [127:0] $end
+         $var logic 128 T sub5_in[1][2] [127:0] $end
         $upscope $end
        $upscope $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array sub5_out $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [0] $end
-         $var wire 8 R sub5_out[0][0] [7:0] $end
-         $var wire 8 S sub5_out[0][1] [7:0] $end
-         $var wire 8 T sub5_out[0][2] [7:0] $end
+         $var wire 8 U sub5_out[0][0] [7:0] $end
+         $var wire 8 V sub5_out[0][1] [7:0] $end
+         $var wire 8 W sub5_out[0][2] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [1] $end
-         $var wire 8 U sub5_out[1][0] [7:0] $end
-         $var wire 8 V sub5_out[1][1] [7:0] $end
-         $var wire 8 W sub5_out[1][2] [7:0] $end
+         $var wire 8 X sub5_out[1][0] [7:0] $end
+         $var wire 8 Y sub5_out[1][1] [7:0] $end
+         $var wire 8 Z sub5_out[1][2] [7:0] $end
         $upscope $end
        $upscope $end
-       $var int 32 X count [31:0] $end
-       $var int 32 Y driven_from_bind [31:0] $end
+       $var int 32 [ count [31:0] $end
+       $var int 32 \ driven_from_bind [31:0] $end
        $scope module i_sub4_bound $end
-        $var real_parameter 64 J P1 $end
-        $var wire 32 Y driven_from_bind [31:0] $end
+        $var real_parameter 64 L P1 $end
+        $var wire 32 \ driven_from_bind [31:0] $end
        $upscope $end
        $scope module i_sub5 $end
-        $var wire 1 ; clk $end
+        $var wire 1 = clk $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array in $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [0] $end
-          $var wire 128 Z in[0][0] [127:0] $end
-          $var wire 128 [ in[0][1] [127:0] $end
-          $var wire 128 \ in[0][2] [127:0] $end
+          $var wire 128 ] in[0][0] [127:0] $end
+          $var wire 128 ^ in[0][1] [127:0] $end
+          $var wire 128 _ in[0][2] [127:0] $end
          $upscope $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [1] $end
-          $var wire 128 ] in[1][0] [127:0] $end
-          $var wire 128 ^ in[1][1] [127:0] $end
-          $var wire 128 _ in[1][2] [127:0] $end
+          $var wire 128 ` in[1][0] [127:0] $end
+          $var wire 128 a in[1][1] [127:0] $end
+          $var wire 128 b in[1][2] [127:0] $end
          $upscope $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array out $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [0] $end
-          $var wire 8 ` out[0][0] [7:0] $end
-          $var wire 8 a out[0][1] [7:0] $end
-          $var wire 8 b out[0][2] [7:0] $end
+          $var wire 8 c out[0][0] [7:0] $end
+          $var wire 8 d out[0][1] [7:0] $end
+          $var wire 8 e out[0][2] [7:0] $end
          $upscope $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [1] $end
-          $var wire 8 c out[1][0] [7:0] $end
-          $var wire 8 d out[1][1] [7:0] $end
-          $var wire 8 e out[1][2] [7:0] $end
+          $var wire 8 f out[1][0] [7:0] $end
+          $var wire 8 g out[1][1] [7:0] $end
+          $var wire 8 h out[1][2] [7:0] $end
          $upscope $end
         $upscope $end
-        $var int 32 f count [31:0] $end
+        $var int 32 i count [31:0] $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val0 $end
-         $var wire 8 g val0[0] [7:0] $end
-         $var wire 8 h val0[1] [7:0] $end
+         $var wire 8 j val0[0] [7:0] $end
+         $var wire 8 k val0[1] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val1 $end
-         $var wire 8 i val1[0] [7:0] $end
-         $var wire 8 j val1[1] [7:0] $end
+         $var wire 8 l val1[0] [7:0] $end
+         $var wire 8 m val1[1] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val2 $end
-         $var wire 8 k val2[0] [7:0] $end
-         $var wire 8 l val2[1] [7:0] $end
+         $var wire 8 n val2[0] [7:0] $end
+         $var wire 8 o val2[1] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val3 $end
-         $var wire 8 m val3[0] [7:0] $end
-         $var wire 8 n val3[1] [7:0] $end
+         $var wire 8 p val3[0] [7:0] $end
+         $var wire 8 q val3[1] [7:0] $end
         $upscope $end
         $scope module i_sub0 $end
-         $var parameter 32 o P0 [31:0] $end
-         $var parameter 32 p P1 [31:0] $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 s P1 [31:0] $end
          $attrbegin array unpacked bounds 1 $end
          $scope sv_array out $end
-          $var wire 8 q out[0] [7:0] $end
-          $var wire 8 r out[1] [7:0] $end
+          $var wire 8 t out[0] [7:0] $end
+          $var wire 8 u out[1] [7:0] $end
          $upscope $end
         $upscope $end
         $scope module i_sub1 $end
-         $var parameter 32 o P0 [31:0] $end
-         $var parameter 32 p P1 [31:0] $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 s P1 [31:0] $end
          $attrbegin array unpacked bounds 1 $end
          $scope sv_array out $end
-          $var wire 8 s out[0] [7:0] $end
-          $var wire 8 t out[1] [7:0] $end
+          $var wire 8 v out[0] [7:0] $end
+          $var wire 8 w out[1] [7:0] $end
          $upscope $end
         $upscope $end
         $scope module i_sub2 $end
-         $var parameter 32 o P0 [31:0] $end
-         $var parameter 32 p P1 [31:0] $end
-         $attrbegin array unpacked bounds 1 $end
-         $scope sv_array out $end
-          $var wire 8 u out[0] [7:0] $end
-          $var wire 8 v out[1] [7:0] $end
-         $upscope $end
-        $upscope $end
-        $scope module i_sub3 $end
-         $var parameter 32 o P0 [31:0] $end
-         $var parameter 32 w P1 [31:0] $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 s P1 [31:0] $end
          $attrbegin array unpacked bounds 1 $end
          $scope sv_array out $end
           $var wire 8 x out[0] [7:0] $end
           $var wire 8 y out[1] [7:0] $end
          $upscope $end
         $upscope $end
+        $scope module i_sub3 $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 z P1 [31:0] $end
+         $attrbegin array unpacked bounds 1 $end
+         $scope sv_array out $end
+          $var wire 8 { out[0] [7:0] $end
+          $var wire 8 | out[1] [7:0] $end
+         $upscope $end
+        $upscope $end
        $upscope $end
       $upscope $end
       $scope module i_sub4_1 $end
-       $var parameter 32 I P0 [31:0] $end
-       $var real_parameter 64 J P1 $end
-       $var real_parameter 64 z P3 $end
-       $var wire 1 ; clk $end
-       $var wire 8 G in [7:0] $end
-       $var wire 8 H out [7:0] $end
-       $var logic 8 H ff [7:0] $end
+       $var parameter 32 K P0 [31:0] $end
+       $var real_parameter 64 L P1 $end
+       $var real_parameter 64 } P3 $end
+       $var wire 1 = clk $end
+       $var wire 8 N in [7:0] $end
+       $var wire 8 J out [7:0] $end
+       $var logic 8 J ff [7:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array sub5_in $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [0] $end
-         $var logic 128 { sub5_in[0][0] [127:0] $end
-         $var logic 128 | sub5_in[0][1] [127:0] $end
-         $var logic 128 } sub5_in[0][2] [127:0] $end
+         $var logic 128 ~ sub5_in[0][0] [127:0] $end
+         $var logic 128 !! sub5_in[0][1] [127:0] $end
+         $var logic 128 "! sub5_in[0][2] [127:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [1] $end
-         $var logic 128 ~ sub5_in[1][0] [127:0] $end
-         $var logic 128 !! sub5_in[1][1] [127:0] $end
-         $var logic 128 "! sub5_in[1][2] [127:0] $end
+         $var logic 128 #! sub5_in[1][0] [127:0] $end
+         $var logic 128 $! sub5_in[1][1] [127:0] $end
+         $var logic 128 %! sub5_in[1][2] [127:0] $end
         $upscope $end
        $upscope $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array sub5_out $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [0] $end
-         $var wire 8 #! sub5_out[0][0] [7:0] $end
-         $var wire 8 $! sub5_out[0][1] [7:0] $end
-         $var wire 8 %! sub5_out[0][2] [7:0] $end
+         $var wire 8 &! sub5_out[0][0] [7:0] $end
+         $var wire 8 '! sub5_out[0][1] [7:0] $end
+         $var wire 8 (! sub5_out[0][2] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [1] $end
-         $var wire 8 &! sub5_out[1][0] [7:0] $end
-         $var wire 8 '! sub5_out[1][1] [7:0] $end
-         $var wire 8 (! sub5_out[1][2] [7:0] $end
+         $var wire 8 )! sub5_out[1][0] [7:0] $end
+         $var wire 8 *! sub5_out[1][1] [7:0] $end
+         $var wire 8 +! sub5_out[1][2] [7:0] $end
         $upscope $end
        $upscope $end
-       $var int 32 )! count [31:0] $end
-       $var int 32 *! driven_from_bind [31:0] $end
+       $var int 32 ,! count [31:0] $end
+       $var int 32 -! driven_from_bind [31:0] $end
        $scope module i_sub4_bound $end
-        $var real_parameter 64 J P1 $end
-        $var wire 32 *! driven_from_bind [31:0] $end
+        $var real_parameter 64 L P1 $end
+        $var wire 32 -! driven_from_bind [31:0] $end
        $upscope $end
        $scope module i_sub5 $end
-        $var wire 1 ; clk $end
+        $var wire 1 = clk $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array in $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [0] $end
-          $var wire 128 +! in[0][0] [127:0] $end
-          $var wire 128 ,! in[0][1] [127:0] $end
-          $var wire 128 -! in[0][2] [127:0] $end
+          $var wire 128 .! in[0][0] [127:0] $end
+          $var wire 128 /! in[0][1] [127:0] $end
+          $var wire 128 0! in[0][2] [127:0] $end
          $upscope $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [1] $end
-          $var wire 128 .! in[1][0] [127:0] $end
-          $var wire 128 /! in[1][1] [127:0] $end
-          $var wire 128 0! in[1][2] [127:0] $end
+          $var wire 128 1! in[1][0] [127:0] $end
+          $var wire 128 2! in[1][1] [127:0] $end
+          $var wire 128 3! in[1][2] [127:0] $end
          $upscope $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array out $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [0] $end
-          $var wire 8 1! out[0][0] [7:0] $end
-          $var wire 8 2! out[0][1] [7:0] $end
-          $var wire 8 3! out[0][2] [7:0] $end
+          $var wire 8 4! out[0][0] [7:0] $end
+          $var wire 8 5! out[0][1] [7:0] $end
+          $var wire 8 6! out[0][2] [7:0] $end
          $upscope $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [1] $end
-          $var wire 8 4! out[1][0] [7:0] $end
-          $var wire 8 5! out[1][1] [7:0] $end
-          $var wire 8 6! out[1][2] [7:0] $end
+          $var wire 8 7! out[1][0] [7:0] $end
+          $var wire 8 8! out[1][1] [7:0] $end
+          $var wire 8 9! out[1][2] [7:0] $end
          $upscope $end
         $upscope $end
-        $var int 32 7! count [31:0] $end
+        $var int 32 :! count [31:0] $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val0 $end
-         $var wire 8 8! val0[0] [7:0] $end
-         $var wire 8 9! val0[1] [7:0] $end
+         $var wire 8 ;! val0[0] [7:0] $end
+         $var wire 8 <! val0[1] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val1 $end
-         $var wire 8 :! val1[0] [7:0] $end
-         $var wire 8 ;! val1[1] [7:0] $end
+         $var wire 8 =! val1[0] [7:0] $end
+         $var wire 8 >! val1[1] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val2 $end
-         $var wire 8 <! val2[0] [7:0] $end
-         $var wire 8 =! val2[1] [7:0] $end
+         $var wire 8 ?! val2[0] [7:0] $end
+         $var wire 8 @! val2[1] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val3 $end
-         $var wire 8 >! val3[0] [7:0] $end
-         $var wire 8 ?! val3[1] [7:0] $end
+         $var wire 8 A! val3[0] [7:0] $end
+         $var wire 8 B! val3[1] [7:0] $end
         $upscope $end
         $scope module i_sub0 $end
-         $var parameter 32 o P0 [31:0] $end
-         $var parameter 32 p P1 [31:0] $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 s P1 [31:0] $end
          $attrbegin array unpacked bounds 1 $end
          $scope sv_array out $end
-          $var wire 8 @! out[0] [7:0] $end
-          $var wire 8 A! out[1] [7:0] $end
+          $var wire 8 C! out[0] [7:0] $end
+          $var wire 8 D! out[1] [7:0] $end
          $upscope $end
         $upscope $end
         $scope module i_sub1 $end
-         $var parameter 32 o P0 [31:0] $end
-         $var parameter 32 p P1 [31:0] $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 s P1 [31:0] $end
          $attrbegin array unpacked bounds 1 $end
          $scope sv_array out $end
-          $var wire 8 B! out[0] [7:0] $end
-          $var wire 8 C! out[1] [7:0] $end
+          $var wire 8 E! out[0] [7:0] $end
+          $var wire 8 F! out[1] [7:0] $end
          $upscope $end
         $upscope $end
         $scope module i_sub2 $end
-         $var parameter 32 o P0 [31:0] $end
-         $var parameter 32 p P1 [31:0] $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 s P1 [31:0] $end
          $attrbegin array unpacked bounds 1 $end
          $scope sv_array out $end
-          $var wire 8 D! out[0] [7:0] $end
-          $var wire 8 E! out[1] [7:0] $end
+          $var wire 8 G! out[0] [7:0] $end
+          $var wire 8 H! out[1] [7:0] $end
          $upscope $end
         $upscope $end
         $scope module i_sub3 $end
-         $var parameter 32 o P0 [31:0] $end
-         $var parameter 32 w P1 [31:0] $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 z P1 [31:0] $end
          $attrbegin array unpacked bounds 1 $end
          $scope sv_array out $end
-          $var wire 8 F! out[0] [7:0] $end
-          $var wire 8 G! out[1] [7:0] $end
+          $var wire 8 I! out[0] [7:0] $end
+          $var wire 8 J! out[1] [7:0] $end
          $upscope $end
         $upscope $end
        $upscope $end
       $upscope $end
      $upscope $end
      $scope module i_sub3_2 $end
-      $var parameter 8 B P0 [7:0] $end
+      $var parameter 8 D P0 [7:0] $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array UNPACKED_ARRAY $end
-       $var parameter 32 H! UNPACKED_ARRAY[0] [31:0] $end
-       $var parameter 32 I! UNPACKED_ARRAY[1] [31:0] $end
+       $var parameter 32 K! UNPACKED_ARRAY[0] [31:0] $end
+       $var parameter 32 L! UNPACKED_ARRAY[1] [31:0] $end
       $upscope $end
-      $var parameter 16 E UNUSED [15:0] $end
+      $var parameter 16 G UNUSED [15:0] $end
       $attrbegin misc 07 "" 4 $end
-      $var parameter 2 F ENUM [1:0] $end
-      $var wire 1 ; clk $end
-      $var wire 8 > in [7:0] $end
-      $var wire 8 A out [7:0] $end
-      $var logic 8 J! ff [7:0] $end
-      $var wire 8 A out4 [7:0] $end
-      $var wire 8 K! out4_2 [7:0] $end
+      $var parameter 2 H ENUM [1:0] $end
+      $var wire 1 = clk $end
+      $var wire 8 @ in [7:0] $end
+      $var wire 8 C out [7:0] $end
+      $var logic 8 M! ff [7:0] $end
+      $var wire 8 C out4 [7:0] $end
+      $var wire 8 N! out4_2 [7:0] $end
       $scope module i_sub4_0 $end
-       $var parameter 32 I P0 [31:0] $end
-       $var real_parameter 64 J P1 $end
-       $var real_parameter 64 K P3 $end
-       $var wire 1 ; clk $end
-       $var wire 8 J! in [7:0] $end
-       $var wire 8 A out [7:0] $end
-       $var logic 8 A ff [7:0] $end
+       $var parameter 32 K P0 [31:0] $end
+       $var real_parameter 64 L P1 $end
+       $var real_parameter 64 M P3 $end
+       $var wire 1 = clk $end
+       $var wire 8 O! in [7:0] $end
+       $var wire 8 C out [7:0] $end
+       $var logic 8 C ff [7:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array sub5_in $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [0] $end
-         $var logic 128 L! sub5_in[0][0] [127:0] $end
-         $var logic 128 M! sub5_in[0][1] [127:0] $end
-         $var logic 128 N! sub5_in[0][2] [127:0] $end
+         $var logic 128 P! sub5_in[0][0] [127:0] $end
+         $var logic 128 Q! sub5_in[0][1] [127:0] $end
+         $var logic 128 R! sub5_in[0][2] [127:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [1] $end
-         $var logic 128 O! sub5_in[1][0] [127:0] $end
-         $var logic 128 P! sub5_in[1][1] [127:0] $end
-         $var logic 128 Q! sub5_in[1][2] [127:0] $end
+         $var logic 128 S! sub5_in[1][0] [127:0] $end
+         $var logic 128 T! sub5_in[1][1] [127:0] $end
+         $var logic 128 U! sub5_in[1][2] [127:0] $end
         $upscope $end
        $upscope $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array sub5_out $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [0] $end
-         $var wire 8 R! sub5_out[0][0] [7:0] $end
-         $var wire 8 S! sub5_out[0][1] [7:0] $end
-         $var wire 8 T! sub5_out[0][2] [7:0] $end
+         $var wire 8 V! sub5_out[0][0] [7:0] $end
+         $var wire 8 W! sub5_out[0][1] [7:0] $end
+         $var wire 8 X! sub5_out[0][2] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [1] $end
-         $var wire 8 U! sub5_out[1][0] [7:0] $end
-         $var wire 8 V! sub5_out[1][1] [7:0] $end
-         $var wire 8 W! sub5_out[1][2] [7:0] $end
+         $var wire 8 Y! sub5_out[1][0] [7:0] $end
+         $var wire 8 Z! sub5_out[1][1] [7:0] $end
+         $var wire 8 [! sub5_out[1][2] [7:0] $end
         $upscope $end
        $upscope $end
-       $var int 32 X! count [31:0] $end
-       $var int 32 Y! driven_from_bind [31:0] $end
+       $var int 32 \! count [31:0] $end
+       $var int 32 ]! driven_from_bind [31:0] $end
        $scope module i_sub4_bound $end
-        $var real_parameter 64 J P1 $end
-        $var wire 32 Y! driven_from_bind [31:0] $end
+        $var real_parameter 64 L P1 $end
+        $var wire 32 ]! driven_from_bind [31:0] $end
        $upscope $end
        $scope module i_sub5 $end
-        $var wire 1 ; clk $end
+        $var wire 1 = clk $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array in $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [0] $end
-          $var wire 128 Z! in[0][0] [127:0] $end
-          $var wire 128 [! in[0][1] [127:0] $end
-          $var wire 128 \! in[0][2] [127:0] $end
+          $var wire 128 ^! in[0][0] [127:0] $end
+          $var wire 128 _! in[0][1] [127:0] $end
+          $var wire 128 `! in[0][2] [127:0] $end
          $upscope $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [1] $end
-          $var wire 128 ]! in[1][0] [127:0] $end
-          $var wire 128 ^! in[1][1] [127:0] $end
-          $var wire 128 _! in[1][2] [127:0] $end
+          $var wire 128 a! in[1][0] [127:0] $end
+          $var wire 128 b! in[1][1] [127:0] $end
+          $var wire 128 c! in[1][2] [127:0] $end
          $upscope $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array out $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [0] $end
-          $var wire 8 `! out[0][0] [7:0] $end
-          $var wire 8 a! out[0][1] [7:0] $end
-          $var wire 8 b! out[0][2] [7:0] $end
+          $var wire 8 d! out[0][0] [7:0] $end
+          $var wire 8 e! out[0][1] [7:0] $end
+          $var wire 8 f! out[0][2] [7:0] $end
          $upscope $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [1] $end
-          $var wire 8 c! out[1][0] [7:0] $end
-          $var wire 8 d! out[1][1] [7:0] $end
-          $var wire 8 e! out[1][2] [7:0] $end
+          $var wire 8 g! out[1][0] [7:0] $end
+          $var wire 8 h! out[1][1] [7:0] $end
+          $var wire 8 i! out[1][2] [7:0] $end
          $upscope $end
         $upscope $end
-        $var int 32 f! count [31:0] $end
+        $var int 32 j! count [31:0] $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val0 $end
-         $var wire 8 g! val0[0] [7:0] $end
-         $var wire 8 h! val0[1] [7:0] $end
+         $var wire 8 k! val0[0] [7:0] $end
+         $var wire 8 l! val0[1] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val1 $end
-         $var wire 8 i! val1[0] [7:0] $end
-         $var wire 8 j! val1[1] [7:0] $end
+         $var wire 8 m! val1[0] [7:0] $end
+         $var wire 8 n! val1[1] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val2 $end
-         $var wire 8 k! val2[0] [7:0] $end
-         $var wire 8 l! val2[1] [7:0] $end
+         $var wire 8 o! val2[0] [7:0] $end
+         $var wire 8 p! val2[1] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val3 $end
-         $var wire 8 m! val3[0] [7:0] $end
-         $var wire 8 n! val3[1] [7:0] $end
+         $var wire 8 q! val3[0] [7:0] $end
+         $var wire 8 r! val3[1] [7:0] $end
         $upscope $end
         $scope module i_sub0 $end
-         $var parameter 32 o P0 [31:0] $end
-         $var parameter 32 p P1 [31:0] $end
-         $attrbegin array unpacked bounds 1 $end
-         $scope sv_array out $end
-          $var wire 8 o! out[0] [7:0] $end
-          $var wire 8 p! out[1] [7:0] $end
-         $upscope $end
-        $upscope $end
-        $scope module i_sub1 $end
-         $var parameter 32 o P0 [31:0] $end
-         $var parameter 32 p P1 [31:0] $end
-         $attrbegin array unpacked bounds 1 $end
-         $scope sv_array out $end
-          $var wire 8 q! out[0] [7:0] $end
-          $var wire 8 r! out[1] [7:0] $end
-         $upscope $end
-        $upscope $end
-        $scope module i_sub2 $end
-         $var parameter 32 o P0 [31:0] $end
-         $var parameter 32 p P1 [31:0] $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 s P1 [31:0] $end
          $attrbegin array unpacked bounds 1 $end
          $scope sv_array out $end
           $var wire 8 s! out[0] [7:0] $end
           $var wire 8 t! out[1] [7:0] $end
          $upscope $end
         $upscope $end
-        $scope module i_sub3 $end
-         $var parameter 32 o P0 [31:0] $end
-         $var parameter 32 w P1 [31:0] $end
+        $scope module i_sub1 $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 s P1 [31:0] $end
          $attrbegin array unpacked bounds 1 $end
          $scope sv_array out $end
           $var wire 8 u! out[0] [7:0] $end
           $var wire 8 v! out[1] [7:0] $end
          $upscope $end
         $upscope $end
+        $scope module i_sub2 $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 s P1 [31:0] $end
+         $attrbegin array unpacked bounds 1 $end
+         $scope sv_array out $end
+          $var wire 8 w! out[0] [7:0] $end
+          $var wire 8 x! out[1] [7:0] $end
+         $upscope $end
+        $upscope $end
+        $scope module i_sub3 $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 z P1 [31:0] $end
+         $attrbegin array unpacked bounds 1 $end
+         $scope sv_array out $end
+          $var wire 8 y! out[0] [7:0] $end
+          $var wire 8 z! out[1] [7:0] $end
+         $upscope $end
+        $upscope $end
        $upscope $end
       $upscope $end
       $scope module i_sub4_1 $end
-       $var parameter 32 I P0 [31:0] $end
-       $var real_parameter 64 J P1 $end
-       $var real_parameter 64 z P3 $end
-       $var wire 1 ; clk $end
-       $var wire 8 J! in [7:0] $end
-       $var wire 8 K! out [7:0] $end
-       $var logic 8 K! ff [7:0] $end
+       $var parameter 32 K P0 [31:0] $end
+       $var real_parameter 64 L P1 $end
+       $var real_parameter 64 } P3 $end
+       $var wire 1 = clk $end
+       $var wire 8 O! in [7:0] $end
+       $var wire 8 N! out [7:0] $end
+       $var logic 8 N! ff [7:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array sub5_in $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [0] $end
-         $var logic 128 w! sub5_in[0][0] [127:0] $end
-         $var logic 128 x! sub5_in[0][1] [127:0] $end
-         $var logic 128 y! sub5_in[0][2] [127:0] $end
+         $var logic 128 {! sub5_in[0][0] [127:0] $end
+         $var logic 128 |! sub5_in[0][1] [127:0] $end
+         $var logic 128 }! sub5_in[0][2] [127:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [1] $end
-         $var logic 128 z! sub5_in[1][0] [127:0] $end
-         $var logic 128 {! sub5_in[1][1] [127:0] $end
-         $var logic 128 |! sub5_in[1][2] [127:0] $end
+         $var logic 128 ~! sub5_in[1][0] [127:0] $end
+         $var logic 128 !" sub5_in[1][1] [127:0] $end
+         $var logic 128 "" sub5_in[1][2] [127:0] $end
         $upscope $end
        $upscope $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array sub5_out $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [0] $end
-         $var wire 8 }! sub5_out[0][0] [7:0] $end
-         $var wire 8 ~! sub5_out[0][1] [7:0] $end
-         $var wire 8 !" sub5_out[0][2] [7:0] $end
+         $var wire 8 #" sub5_out[0][0] [7:0] $end
+         $var wire 8 $" sub5_out[0][1] [7:0] $end
+         $var wire 8 %" sub5_out[0][2] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [1] $end
-         $var wire 8 "" sub5_out[1][0] [7:0] $end
-         $var wire 8 #" sub5_out[1][1] [7:0] $end
-         $var wire 8 $" sub5_out[1][2] [7:0] $end
+         $var wire 8 &" sub5_out[1][0] [7:0] $end
+         $var wire 8 '" sub5_out[1][1] [7:0] $end
+         $var wire 8 (" sub5_out[1][2] [7:0] $end
         $upscope $end
        $upscope $end
-       $var int 32 %" count [31:0] $end
-       $var int 32 &" driven_from_bind [31:0] $end
+       $var int 32 )" count [31:0] $end
+       $var int 32 *" driven_from_bind [31:0] $end
        $scope module i_sub4_bound $end
-        $var real_parameter 64 J P1 $end
-        $var wire 32 &" driven_from_bind [31:0] $end
+        $var real_parameter 64 L P1 $end
+        $var wire 32 *" driven_from_bind [31:0] $end
        $upscope $end
        $scope module i_sub5 $end
-        $var wire 1 ; clk $end
+        $var wire 1 = clk $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array in $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [0] $end
-          $var wire 128 '" in[0][0] [127:0] $end
-          $var wire 128 (" in[0][1] [127:0] $end
-          $var wire 128 )" in[0][2] [127:0] $end
+          $var wire 128 +" in[0][0] [127:0] $end
+          $var wire 128 ," in[0][1] [127:0] $end
+          $var wire 128 -" in[0][2] [127:0] $end
          $upscope $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [1] $end
-          $var wire 128 *" in[1][0] [127:0] $end
-          $var wire 128 +" in[1][1] [127:0] $end
-          $var wire 128 ," in[1][2] [127:0] $end
+          $var wire 128 ." in[1][0] [127:0] $end
+          $var wire 128 /" in[1][1] [127:0] $end
+          $var wire 128 0" in[1][2] [127:0] $end
          $upscope $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array out $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [0] $end
-          $var wire 8 -" out[0][0] [7:0] $end
-          $var wire 8 ." out[0][1] [7:0] $end
-          $var wire 8 /" out[0][2] [7:0] $end
+          $var wire 8 1" out[0][0] [7:0] $end
+          $var wire 8 2" out[0][1] [7:0] $end
+          $var wire 8 3" out[0][2] [7:0] $end
          $upscope $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [1] $end
-          $var wire 8 0" out[1][0] [7:0] $end
-          $var wire 8 1" out[1][1] [7:0] $end
-          $var wire 8 2" out[1][2] [7:0] $end
+          $var wire 8 4" out[1][0] [7:0] $end
+          $var wire 8 5" out[1][1] [7:0] $end
+          $var wire 8 6" out[1][2] [7:0] $end
          $upscope $end
         $upscope $end
-        $var int 32 3" count [31:0] $end
+        $var int 32 7" count [31:0] $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val0 $end
-         $var wire 8 4" val0[0] [7:0] $end
-         $var wire 8 5" val0[1] [7:0] $end
+         $var wire 8 8" val0[0] [7:0] $end
+         $var wire 8 9" val0[1] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val1 $end
-         $var wire 8 6" val1[0] [7:0] $end
-         $var wire 8 7" val1[1] [7:0] $end
+         $var wire 8 :" val1[0] [7:0] $end
+         $var wire 8 ;" val1[1] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val2 $end
-         $var wire 8 8" val2[0] [7:0] $end
-         $var wire 8 9" val2[1] [7:0] $end
+         $var wire 8 <" val2[0] [7:0] $end
+         $var wire 8 =" val2[1] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val3 $end
-         $var wire 8 :" val3[0] [7:0] $end
-         $var wire 8 ;" val3[1] [7:0] $end
+         $var wire 8 >" val3[0] [7:0] $end
+         $var wire 8 ?" val3[1] [7:0] $end
         $upscope $end
         $scope module i_sub0 $end
-         $var parameter 32 o P0 [31:0] $end
-         $var parameter 32 p P1 [31:0] $end
-         $attrbegin array unpacked bounds 1 $end
-         $scope sv_array out $end
-          $var wire 8 <" out[0] [7:0] $end
-          $var wire 8 =" out[1] [7:0] $end
-         $upscope $end
-        $upscope $end
-        $scope module i_sub1 $end
-         $var parameter 32 o P0 [31:0] $end
-         $var parameter 32 p P1 [31:0] $end
-         $attrbegin array unpacked bounds 1 $end
-         $scope sv_array out $end
-          $var wire 8 >" out[0] [7:0] $end
-          $var wire 8 ?" out[1] [7:0] $end
-         $upscope $end
-        $upscope $end
-        $scope module i_sub2 $end
-         $var parameter 32 o P0 [31:0] $end
-         $var parameter 32 p P1 [31:0] $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 s P1 [31:0] $end
          $attrbegin array unpacked bounds 1 $end
          $scope sv_array out $end
           $var wire 8 @" out[0] [7:0] $end
           $var wire 8 A" out[1] [7:0] $end
          $upscope $end
         $upscope $end
-        $scope module i_sub3 $end
-         $var parameter 32 o P0 [31:0] $end
-         $var parameter 32 w P1 [31:0] $end
+        $scope module i_sub1 $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 s P1 [31:0] $end
          $attrbegin array unpacked bounds 1 $end
          $scope sv_array out $end
           $var wire 8 B" out[0] [7:0] $end
           $var wire 8 C" out[1] [7:0] $end
          $upscope $end
         $upscope $end
+        $scope module i_sub2 $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 s P1 [31:0] $end
+         $attrbegin array unpacked bounds 1 $end
+         $scope sv_array out $end
+          $var wire 8 D" out[0] [7:0] $end
+          $var wire 8 E" out[1] [7:0] $end
+         $upscope $end
+        $upscope $end
+        $scope module i_sub3 $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 z P1 [31:0] $end
+         $attrbegin array unpacked bounds 1 $end
+         $scope sv_array out $end
+          $var wire 8 F" out[0] [7:0] $end
+          $var wire 8 G" out[1] [7:0] $end
+         $upscope $end
+        $upscope $end
        $upscope $end
       $upscope $end
      $upscope $end
      $scope interface in $end
-      $var wire 1 ; clk $end
-      $var logic 8 > data [7:0] $end
+      $var wire 1 = clk $end
+      $var logic 8 @ data [7:0] $end
      $upscope $end
      $scope interface out $end
-      $var wire 1 ; clk $end
-      $var logic 8 @ data [7:0] $end
+      $var wire 1 = clk $end
+      $var logic 8 B data [7:0] $end
      $upscope $end
     $upscope $end
     $scope interface in_ifs $end
-     $var wire 1 ; clk $end
-     $var logic 8 > data [7:0] $end
+     $var wire 1 = clk $end
+     $var logic 8 @ data [7:0] $end
     $upscope $end
     $scope interface out_ifs $end
-     $var wire 1 ; clk $end
-     $var logic 8 @ data [7:0] $end
+     $var wire 1 = clk $end
+     $var logic 8 B data [7:0] $end
     $upscope $end
    $upscope $end
    $scope module i_sub3 $end
-    $var parameter 8 D" P0 [7:0] $end
+    $var parameter 8 H" P0 [7:0] $end
     $attrbegin array unpacked bounds 1 $end
     $scope sv_array UNPACKED_ARRAY $end
-     $var parameter 32 E" UNPACKED_ARRAY[0] [31:0] $end
-     $var parameter 32 F" UNPACKED_ARRAY[1] [31:0] $end
+     $var parameter 32 I" UNPACKED_ARRAY[0] [31:0] $end
+     $var parameter 32 J" UNPACKED_ARRAY[1] [31:0] $end
     $upscope $end
-    $var parameter 16 G" UNUSED [15:0] $end
+    $var parameter 16 K" UNUSED [15:0] $end
     $attrbegin misc 07 "" 1 $end
-    $var parameter 2 H" ENUM [1:0] $end
+    $var parameter 2 L" ENUM [1:0] $end
     $var wire 1 ! clk $end
     $var wire 8 ' in [7:0] $end
     $var wire 8 ( out [7:0] $end
-    $var logic 8 I" ff [7:0] $end
+    $var logic 8 M" ff [7:0] $end
     $var wire 8 ( out4 [7:0] $end
-    $var wire 8 J" out4_2 [7:0] $end
+    $var wire 8 N" out4_2 [7:0] $end
     $scope module i_sub4_0 $end
-     $var parameter 32 K" P0 [31:0] $end
-     $var real_parameter 64 L" P1 $end
-     $var real_parameter 64 M" P3 $end
+     $var parameter 32 O" P0 [31:0] $end
+     $var real_parameter 64 P" P1 $end
+     $var real_parameter 64 Q" P3 $end
      $var wire 1 ! clk $end
-     $var wire 8 I" in [7:0] $end
+     $var wire 8 R" in [7:0] $end
      $var wire 8 ( out [7:0] $end
      $var logic 8 ( ff [7:0] $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array sub5_in $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [0] $end
-       $var logic 128 N" sub5_in[0][0] [127:0] $end
-       $var logic 128 O" sub5_in[0][1] [127:0] $end
-       $var logic 128 P" sub5_in[0][2] [127:0] $end
+       $var logic 128 S" sub5_in[0][0] [127:0] $end
+       $var logic 128 T" sub5_in[0][1] [127:0] $end
+       $var logic 128 U" sub5_in[0][2] [127:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [1] $end
-       $var logic 128 Q" sub5_in[1][0] [127:0] $end
-       $var logic 128 R" sub5_in[1][1] [127:0] $end
-       $var logic 128 S" sub5_in[1][2] [127:0] $end
+       $var logic 128 V" sub5_in[1][0] [127:0] $end
+       $var logic 128 W" sub5_in[1][1] [127:0] $end
+       $var logic 128 X" sub5_in[1][2] [127:0] $end
       $upscope $end
      $upscope $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array sub5_out $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [0] $end
-       $var wire 8 T" sub5_out[0][0] [7:0] $end
-       $var wire 8 U" sub5_out[0][1] [7:0] $end
-       $var wire 8 V" sub5_out[0][2] [7:0] $end
+       $var wire 8 Y" sub5_out[0][0] [7:0] $end
+       $var wire 8 Z" sub5_out[0][1] [7:0] $end
+       $var wire 8 [" sub5_out[0][2] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [1] $end
-       $var wire 8 W" sub5_out[1][0] [7:0] $end
-       $var wire 8 X" sub5_out[1][1] [7:0] $end
-       $var wire 8 Y" sub5_out[1][2] [7:0] $end
+       $var wire 8 \" sub5_out[1][0] [7:0] $end
+       $var wire 8 ]" sub5_out[1][1] [7:0] $end
+       $var wire 8 ^" sub5_out[1][2] [7:0] $end
       $upscope $end
      $upscope $end
-     $var int 32 Z" count [31:0] $end
-     $var int 32 [" driven_from_bind [31:0] $end
+     $var int 32 _" count [31:0] $end
+     $var int 32 `" driven_from_bind [31:0] $end
      $scope module i_sub4_bound $end
-      $var real_parameter 64 L" P1 $end
-      $var wire 32 [" driven_from_bind [31:0] $end
+      $var real_parameter 64 P" P1 $end
+      $var wire 32 `" driven_from_bind [31:0] $end
      $upscope $end
      $scope module i_sub5 $end
-      $var wire 1 \" clk $end
+      $var wire 1 a" clk $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array in $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [0] $end
-        $var wire 128 ]" in[0][0] [127:0] $end
-        $var wire 128 ^" in[0][1] [127:0] $end
-        $var wire 128 _" in[0][2] [127:0] $end
+        $var wire 128 b" in[0][0] [127:0] $end
+        $var wire 128 c" in[0][1] [127:0] $end
+        $var wire 128 d" in[0][2] [127:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [1] $end
-        $var wire 128 `" in[1][0] [127:0] $end
-        $var wire 128 a" in[1][1] [127:0] $end
-        $var wire 128 b" in[1][2] [127:0] $end
+        $var wire 128 e" in[1][0] [127:0] $end
+        $var wire 128 f" in[1][1] [127:0] $end
+        $var wire 128 g" in[1][2] [127:0] $end
        $upscope $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array out $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [0] $end
-        $var wire 8 c" out[0][0] [7:0] $end
-        $var wire 8 d" out[0][1] [7:0] $end
-        $var wire 8 e" out[0][2] [7:0] $end
+        $var wire 8 h" out[0][0] [7:0] $end
+        $var wire 8 i" out[0][1] [7:0] $end
+        $var wire 8 j" out[0][2] [7:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [1] $end
-        $var wire 8 f" out[1][0] [7:0] $end
-        $var wire 8 g" out[1][1] [7:0] $end
-        $var wire 8 h" out[1][2] [7:0] $end
+        $var wire 8 k" out[1][0] [7:0] $end
+        $var wire 8 l" out[1][1] [7:0] $end
+        $var wire 8 m" out[1][2] [7:0] $end
        $upscope $end
       $upscope $end
-      $var int 32 i" count [31:0] $end
+      $var int 32 n" count [31:0] $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array val0 $end
-       $var wire 8 j" val0[0] [7:0] $end
-       $var wire 8 k" val0[1] [7:0] $end
+       $var wire 8 o" val0[0] [7:0] $end
+       $var wire 8 p" val0[1] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array val1 $end
-       $var wire 8 l" val1[0] [7:0] $end
-       $var wire 8 m" val1[1] [7:0] $end
+       $var wire 8 q" val1[0] [7:0] $end
+       $var wire 8 r" val1[1] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array val2 $end
-       $var wire 8 n" val2[0] [7:0] $end
-       $var wire 8 o" val2[1] [7:0] $end
+       $var wire 8 s" val2[0] [7:0] $end
+       $var wire 8 t" val2[1] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array val3 $end
-       $var wire 8 p" val3[0] [7:0] $end
-       $var wire 8 q" val3[1] [7:0] $end
+       $var wire 8 u" val3[0] [7:0] $end
+       $var wire 8 v" val3[1] [7:0] $end
       $upscope $end
       $scope module i_sub0 $end
-       $var parameter 32 r" P0 [31:0] $end
-       $var parameter 32 s" P1 [31:0] $end
+       $var parameter 32 w" P0 [31:0] $end
+       $var parameter 32 x" P1 [31:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array out $end
-        $var wire 8 t" out[0] [7:0] $end
-        $var wire 8 u" out[1] [7:0] $end
+        $var wire 8 y" out[0] [7:0] $end
+        $var wire 8 z" out[1] [7:0] $end
        $upscope $end
       $upscope $end
       $scope module i_sub1 $end
-       $var parameter 32 r" P0 [31:0] $end
-       $var parameter 32 s" P1 [31:0] $end
-       $attrbegin array unpacked bounds 1 $end
-       $scope sv_array out $end
-        $var wire 8 v" out[0] [7:0] $end
-        $var wire 8 w" out[1] [7:0] $end
-       $upscope $end
-      $upscope $end
-      $scope module i_sub2 $end
-       $var parameter 32 r" P0 [31:0] $end
-       $var parameter 32 s" P1 [31:0] $end
-       $attrbegin array unpacked bounds 1 $end
-       $scope sv_array out $end
-        $var wire 8 x" out[0] [7:0] $end
-        $var wire 8 y" out[1] [7:0] $end
-       $upscope $end
-      $upscope $end
-      $scope module i_sub3 $end
-       $var parameter 32 r" P0 [31:0] $end
-       $var parameter 32 z" P1 [31:0] $end
+       $var parameter 32 w" P0 [31:0] $end
+       $var parameter 32 x" P1 [31:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array out $end
         $var wire 8 {" out[0] [7:0] $end
         $var wire 8 |" out[1] [7:0] $end
        $upscope $end
       $upscope $end
+      $scope module i_sub2 $end
+       $var parameter 32 w" P0 [31:0] $end
+       $var parameter 32 x" P1 [31:0] $end
+       $attrbegin array unpacked bounds 1 $end
+       $scope sv_array out $end
+        $var wire 8 }" out[0] [7:0] $end
+        $var wire 8 ~" out[1] [7:0] $end
+       $upscope $end
+      $upscope $end
+      $scope module i_sub3 $end
+       $var parameter 32 w" P0 [31:0] $end
+       $var parameter 32 !# P1 [31:0] $end
+       $attrbegin array unpacked bounds 1 $end
+       $scope sv_array out $end
+        $var wire 8 "# out[0] [7:0] $end
+        $var wire 8 ## out[1] [7:0] $end
+       $upscope $end
+      $upscope $end
      $upscope $end
     $upscope $end
     $scope module i_sub4_1 $end
-     $var parameter 32 K" P0 [31:0] $end
-     $var real_parameter 64 L" P1 $end
-     $var real_parameter 64 }" P3 $end
+     $var parameter 32 O" P0 [31:0] $end
+     $var real_parameter 64 P" P1 $end
+     $var real_parameter 64 $# P3 $end
      $var wire 1 ! clk $end
-     $var wire 8 I" in [7:0] $end
-     $var wire 8 J" out [7:0] $end
-     $var logic 8 J" ff [7:0] $end
+     $var wire 8 R" in [7:0] $end
+     $var wire 8 N" out [7:0] $end
+     $var logic 8 N" ff [7:0] $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array sub5_in $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [0] $end
-       $var logic 128 ~" sub5_in[0][0] [127:0] $end
-       $var logic 128 !# sub5_in[0][1] [127:0] $end
-       $var logic 128 "# sub5_in[0][2] [127:0] $end
+       $var logic 128 %# sub5_in[0][0] [127:0] $end
+       $var logic 128 &# sub5_in[0][1] [127:0] $end
+       $var logic 128 '# sub5_in[0][2] [127:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [1] $end
-       $var logic 128 ## sub5_in[1][0] [127:0] $end
-       $var logic 128 $# sub5_in[1][1] [127:0] $end
-       $var logic 128 %# sub5_in[1][2] [127:0] $end
+       $var logic 128 (# sub5_in[1][0] [127:0] $end
+       $var logic 128 )# sub5_in[1][1] [127:0] $end
+       $var logic 128 *# sub5_in[1][2] [127:0] $end
       $upscope $end
      $upscope $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array sub5_out $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [0] $end
-       $var wire 8 &# sub5_out[0][0] [7:0] $end
-       $var wire 8 '# sub5_out[0][1] [7:0] $end
-       $var wire 8 (# sub5_out[0][2] [7:0] $end
+       $var wire 8 +# sub5_out[0][0] [7:0] $end
+       $var wire 8 ,# sub5_out[0][1] [7:0] $end
+       $var wire 8 -# sub5_out[0][2] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [1] $end
-       $var wire 8 )# sub5_out[1][0] [7:0] $end
-       $var wire 8 *# sub5_out[1][1] [7:0] $end
-       $var wire 8 +# sub5_out[1][2] [7:0] $end
+       $var wire 8 .# sub5_out[1][0] [7:0] $end
+       $var wire 8 /# sub5_out[1][1] [7:0] $end
+       $var wire 8 0# sub5_out[1][2] [7:0] $end
       $upscope $end
      $upscope $end
-     $var int 32 ,# count [31:0] $end
-     $var int 32 -# driven_from_bind [31:0] $end
+     $var int 32 1# count [31:0] $end
+     $var int 32 2# driven_from_bind [31:0] $end
      $scope module i_sub4_bound $end
-      $var real_parameter 64 L" P1 $end
-      $var wire 32 -# driven_from_bind [31:0] $end
+      $var real_parameter 64 P" P1 $end
+      $var wire 32 2# driven_from_bind [31:0] $end
      $upscope $end
      $scope module i_sub5 $end
-      $var wire 1 .# clk $end
+      $var wire 1 3# clk $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array in $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [0] $end
-        $var wire 128 /# in[0][0] [127:0] $end
-        $var wire 128 0# in[0][1] [127:0] $end
-        $var wire 128 1# in[0][2] [127:0] $end
+        $var wire 128 4# in[0][0] [127:0] $end
+        $var wire 128 5# in[0][1] [127:0] $end
+        $var wire 128 6# in[0][2] [127:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [1] $end
-        $var wire 128 2# in[1][0] [127:0] $end
-        $var wire 128 3# in[1][1] [127:0] $end
-        $var wire 128 4# in[1][2] [127:0] $end
+        $var wire 128 7# in[1][0] [127:0] $end
+        $var wire 128 8# in[1][1] [127:0] $end
+        $var wire 128 9# in[1][2] [127:0] $end
        $upscope $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array out $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [0] $end
-        $var wire 8 5# out[0][0] [7:0] $end
-        $var wire 8 6# out[0][1] [7:0] $end
-        $var wire 8 7# out[0][2] [7:0] $end
+        $var wire 8 :# out[0][0] [7:0] $end
+        $var wire 8 ;# out[0][1] [7:0] $end
+        $var wire 8 <# out[0][2] [7:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [1] $end
-        $var wire 8 8# out[1][0] [7:0] $end
-        $var wire 8 9# out[1][1] [7:0] $end
-        $var wire 8 :# out[1][2] [7:0] $end
+        $var wire 8 =# out[1][0] [7:0] $end
+        $var wire 8 ># out[1][1] [7:0] $end
+        $var wire 8 ?# out[1][2] [7:0] $end
        $upscope $end
       $upscope $end
-      $var int 32 ;# count [31:0] $end
+      $var int 32 @# count [31:0] $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array val0 $end
-       $var wire 8 <# val0[0] [7:0] $end
-       $var wire 8 =# val0[1] [7:0] $end
+       $var wire 8 A# val0[0] [7:0] $end
+       $var wire 8 B# val0[1] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array val1 $end
-       $var wire 8 ># val1[0] [7:0] $end
-       $var wire 8 ?# val1[1] [7:0] $end
+       $var wire 8 C# val1[0] [7:0] $end
+       $var wire 8 D# val1[1] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array val2 $end
-       $var wire 8 @# val2[0] [7:0] $end
-       $var wire 8 A# val2[1] [7:0] $end
+       $var wire 8 E# val2[0] [7:0] $end
+       $var wire 8 F# val2[1] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array val3 $end
-       $var wire 8 B# val3[0] [7:0] $end
-       $var wire 8 C# val3[1] [7:0] $end
+       $var wire 8 G# val3[0] [7:0] $end
+       $var wire 8 H# val3[1] [7:0] $end
       $upscope $end
       $scope module i_sub0 $end
-       $var parameter 32 D# P0 [31:0] $end
-       $var parameter 32 E# P1 [31:0] $end
+       $var parameter 32 I# P0 [31:0] $end
+       $var parameter 32 J# P1 [31:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array out $end
-        $var wire 8 F# out[0] [7:0] $end
-        $var wire 8 G# out[1] [7:0] $end
+        $var wire 8 K# out[0] [7:0] $end
+        $var wire 8 L# out[1] [7:0] $end
        $upscope $end
       $upscope $end
       $scope module i_sub1 $end
-       $var parameter 32 D# P0 [31:0] $end
-       $var parameter 32 E# P1 [31:0] $end
-       $attrbegin array unpacked bounds 1 $end
-       $scope sv_array out $end
-        $var wire 8 H# out[0] [7:0] $end
-        $var wire 8 I# out[1] [7:0] $end
-       $upscope $end
-      $upscope $end
-      $scope module i_sub2 $end
-       $var parameter 32 D# P0 [31:0] $end
-       $var parameter 32 E# P1 [31:0] $end
-       $attrbegin array unpacked bounds 1 $end
-       $scope sv_array out $end
-        $var wire 8 J# out[0] [7:0] $end
-        $var wire 8 K# out[1] [7:0] $end
-       $upscope $end
-      $upscope $end
-      $scope module i_sub3 $end
-       $var parameter 32 D# P0 [31:0] $end
-       $var parameter 32 L# P1 [31:0] $end
+       $var parameter 32 I# P0 [31:0] $end
+       $var parameter 32 J# P1 [31:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array out $end
         $var wire 8 M# out[0] [7:0] $end
         $var wire 8 N# out[1] [7:0] $end
        $upscope $end
       $upscope $end
+      $scope module i_sub2 $end
+       $var parameter 32 I# P0 [31:0] $end
+       $var parameter 32 J# P1 [31:0] $end
+       $attrbegin array unpacked bounds 1 $end
+       $scope sv_array out $end
+        $var wire 8 O# out[0] [7:0] $end
+        $var wire 8 P# out[1] [7:0] $end
+       $upscope $end
+      $upscope $end
+      $scope module i_sub3 $end
+       $var parameter 32 I# P0 [31:0] $end
+       $var parameter 32 Q# P1 [31:0] $end
+       $attrbegin array unpacked bounds 1 $end
+       $scope sv_array out $end
+        $var wire 8 R# out[0] [7:0] $end
+        $var wire 8 S# out[1] [7:0] $end
+       $upscope $end
+      $upscope $end
      $upscope $end
     $upscope $end
    $upscope $end
    $scope module i_sub3_2 $end
-    $var parameter 8 D" P0 [7:0] $end
+    $var parameter 8 H" P0 [7:0] $end
     $attrbegin array unpacked bounds 1 $end
     $scope sv_array UNPACKED_ARRAY $end
-     $var parameter 32 O# UNPACKED_ARRAY[0] [31:0] $end
-     $var parameter 32 P# UNPACKED_ARRAY[1] [31:0] $end
+     $var parameter 32 T# UNPACKED_ARRAY[0] [31:0] $end
+     $var parameter 32 U# UNPACKED_ARRAY[1] [31:0] $end
     $upscope $end
-    $var parameter 16 G" UNUSED [15:0] $end
+    $var parameter 16 K" UNUSED [15:0] $end
     $attrbegin misc 07 "" 1 $end
-    $var parameter 2 H" ENUM [1:0] $end
+    $var parameter 2 L" ENUM [1:0] $end
     $var wire 1 ! clk $end
     $var wire 8 ' in [7:0] $end
     $var wire 8 ) out [7:0] $end
-    $var logic 8 Q# ff [7:0] $end
+    $var logic 8 V# ff [7:0] $end
     $var wire 8 ) out4 [7:0] $end
-    $var wire 8 R# out4_2 [7:0] $end
+    $var wire 8 W# out4_2 [7:0] $end
     $scope module i_sub4_0 $end
-     $var parameter 32 K" P0 [31:0] $end
-     $var real_parameter 64 L" P1 $end
-     $var real_parameter 64 M" P3 $end
+     $var parameter 32 O" P0 [31:0] $end
+     $var real_parameter 64 P" P1 $end
+     $var real_parameter 64 Q" P3 $end
      $var wire 1 ! clk $end
-     $var wire 8 Q# in [7:0] $end
+     $var wire 8 X# in [7:0] $end
      $var wire 8 ) out [7:0] $end
      $var logic 8 ) ff [7:0] $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array sub5_in $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [0] $end
-       $var logic 128 S# sub5_in[0][0] [127:0] $end
-       $var logic 128 T# sub5_in[0][1] [127:0] $end
-       $var logic 128 U# sub5_in[0][2] [127:0] $end
+       $var logic 128 Y# sub5_in[0][0] [127:0] $end
+       $var logic 128 Z# sub5_in[0][1] [127:0] $end
+       $var logic 128 [# sub5_in[0][2] [127:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [1] $end
-       $var logic 128 V# sub5_in[1][0] [127:0] $end
-       $var logic 128 W# sub5_in[1][1] [127:0] $end
-       $var logic 128 X# sub5_in[1][2] [127:0] $end
+       $var logic 128 \# sub5_in[1][0] [127:0] $end
+       $var logic 128 ]# sub5_in[1][1] [127:0] $end
+       $var logic 128 ^# sub5_in[1][2] [127:0] $end
       $upscope $end
      $upscope $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array sub5_out $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [0] $end
-       $var wire 8 Y# sub5_out[0][0] [7:0] $end
-       $var wire 8 Z# sub5_out[0][1] [7:0] $end
-       $var wire 8 [# sub5_out[0][2] [7:0] $end
+       $var wire 8 _# sub5_out[0][0] [7:0] $end
+       $var wire 8 `# sub5_out[0][1] [7:0] $end
+       $var wire 8 a# sub5_out[0][2] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [1] $end
-       $var wire 8 \# sub5_out[1][0] [7:0] $end
-       $var wire 8 ]# sub5_out[1][1] [7:0] $end
-       $var wire 8 ^# sub5_out[1][2] [7:0] $end
+       $var wire 8 b# sub5_out[1][0] [7:0] $end
+       $var wire 8 c# sub5_out[1][1] [7:0] $end
+       $var wire 8 d# sub5_out[1][2] [7:0] $end
       $upscope $end
      $upscope $end
-     $var int 32 _# count [31:0] $end
-     $var int 32 `# driven_from_bind [31:0] $end
+     $var int 32 e# count [31:0] $end
+     $var int 32 f# driven_from_bind [31:0] $end
      $scope module i_sub4_bound $end
-      $var real_parameter 64 L" P1 $end
-      $var wire 32 `# driven_from_bind [31:0] $end
+      $var real_parameter 64 P" P1 $end
+      $var wire 32 f# driven_from_bind [31:0] $end
      $upscope $end
      $scope module i_sub5 $end
-      $var wire 1 a# clk $end
+      $var wire 1 g# clk $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array in $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [0] $end
-        $var wire 128 b# in[0][0] [127:0] $end
-        $var wire 128 c# in[0][1] [127:0] $end
-        $var wire 128 d# in[0][2] [127:0] $end
+        $var wire 128 h# in[0][0] [127:0] $end
+        $var wire 128 i# in[0][1] [127:0] $end
+        $var wire 128 j# in[0][2] [127:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [1] $end
-        $var wire 128 e# in[1][0] [127:0] $end
-        $var wire 128 f# in[1][1] [127:0] $end
-        $var wire 128 g# in[1][2] [127:0] $end
+        $var wire 128 k# in[1][0] [127:0] $end
+        $var wire 128 l# in[1][1] [127:0] $end
+        $var wire 128 m# in[1][2] [127:0] $end
        $upscope $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array out $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [0] $end
-        $var wire 8 h# out[0][0] [7:0] $end
-        $var wire 8 i# out[0][1] [7:0] $end
-        $var wire 8 j# out[0][2] [7:0] $end
+        $var wire 8 n# out[0][0] [7:0] $end
+        $var wire 8 o# out[0][1] [7:0] $end
+        $var wire 8 p# out[0][2] [7:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [1] $end
-        $var wire 8 k# out[1][0] [7:0] $end
-        $var wire 8 l# out[1][1] [7:0] $end
-        $var wire 8 m# out[1][2] [7:0] $end
+        $var wire 8 q# out[1][0] [7:0] $end
+        $var wire 8 r# out[1][1] [7:0] $end
+        $var wire 8 s# out[1][2] [7:0] $end
        $upscope $end
       $upscope $end
-      $var int 32 n# count [31:0] $end
+      $var int 32 t# count [31:0] $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array val0 $end
-       $var wire 8 o# val0[0] [7:0] $end
-       $var wire 8 p# val0[1] [7:0] $end
+       $var wire 8 u# val0[0] [7:0] $end
+       $var wire 8 v# val0[1] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array val1 $end
-       $var wire 8 q# val1[0] [7:0] $end
-       $var wire 8 r# val1[1] [7:0] $end
+       $var wire 8 w# val1[0] [7:0] $end
+       $var wire 8 x# val1[1] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array val2 $end
-       $var wire 8 s# val2[0] [7:0] $end
-       $var wire 8 t# val2[1] [7:0] $end
+       $var wire 8 y# val2[0] [7:0] $end
+       $var wire 8 z# val2[1] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array val3 $end
-       $var wire 8 u# val3[0] [7:0] $end
-       $var wire 8 v# val3[1] [7:0] $end
+       $var wire 8 {# val3[0] [7:0] $end
+       $var wire 8 |# val3[1] [7:0] $end
       $upscope $end
       $scope module i_sub0 $end
-       $var parameter 32 w# P0 [31:0] $end
-       $var parameter 32 x# P1 [31:0] $end
+       $var parameter 32 }# P0 [31:0] $end
+       $var parameter 32 ~# P1 [31:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array out $end
-        $var wire 8 y# out[0] [7:0] $end
-        $var wire 8 z# out[1] [7:0] $end
+        $var wire 8 !$ out[0] [7:0] $end
+        $var wire 8 "$ out[1] [7:0] $end
        $upscope $end
       $upscope $end
       $scope module i_sub1 $end
-       $var parameter 32 w# P0 [31:0] $end
-       $var parameter 32 x# P1 [31:0] $end
+       $var parameter 32 }# P0 [31:0] $end
+       $var parameter 32 ~# P1 [31:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array out $end
-        $var wire 8 {# out[0] [7:0] $end
-        $var wire 8 |# out[1] [7:0] $end
+        $var wire 8 #$ out[0] [7:0] $end
+        $var wire 8 $$ out[1] [7:0] $end
        $upscope $end
       $upscope $end
       $scope module i_sub2 $end
-       $var parameter 32 w# P0 [31:0] $end
-       $var parameter 32 x# P1 [31:0] $end
+       $var parameter 32 }# P0 [31:0] $end
+       $var parameter 32 ~# P1 [31:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array out $end
-        $var wire 8 }# out[0] [7:0] $end
-        $var wire 8 ~# out[1] [7:0] $end
+        $var wire 8 %$ out[0] [7:0] $end
+        $var wire 8 &$ out[1] [7:0] $end
        $upscope $end
       $upscope $end
       $scope module i_sub3 $end
-       $var parameter 32 w# P0 [31:0] $end
-       $var parameter 32 !$ P1 [31:0] $end
+       $var parameter 32 }# P0 [31:0] $end
+       $var parameter 32 '$ P1 [31:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array out $end
-        $var wire 8 "$ out[0] [7:0] $end
-        $var wire 8 #$ out[1] [7:0] $end
+        $var wire 8 ($ out[0] [7:0] $end
+        $var wire 8 )$ out[1] [7:0] $end
        $upscope $end
       $upscope $end
      $upscope $end
     $upscope $end
     $scope module i_sub4_1 $end
-     $var parameter 32 K" P0 [31:0] $end
-     $var real_parameter 64 L" P1 $end
-     $var real_parameter 64 }" P3 $end
+     $var parameter 32 O" P0 [31:0] $end
+     $var real_parameter 64 P" P1 $end
+     $var real_parameter 64 $# P3 $end
      $var wire 1 ! clk $end
-     $var wire 8 Q# in [7:0] $end
-     $var wire 8 R# out [7:0] $end
-     $var logic 8 R# ff [7:0] $end
+     $var wire 8 X# in [7:0] $end
+     $var wire 8 W# out [7:0] $end
+     $var logic 8 W# ff [7:0] $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array sub5_in $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [0] $end
-       $var logic 128 $$ sub5_in[0][0] [127:0] $end
-       $var logic 128 %$ sub5_in[0][1] [127:0] $end
-       $var logic 128 &$ sub5_in[0][2] [127:0] $end
+       $var logic 128 *$ sub5_in[0][0] [127:0] $end
+       $var logic 128 +$ sub5_in[0][1] [127:0] $end
+       $var logic 128 ,$ sub5_in[0][2] [127:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [1] $end
-       $var logic 128 '$ sub5_in[1][0] [127:0] $end
-       $var logic 128 ($ sub5_in[1][1] [127:0] $end
-       $var logic 128 )$ sub5_in[1][2] [127:0] $end
+       $var logic 128 -$ sub5_in[1][0] [127:0] $end
+       $var logic 128 .$ sub5_in[1][1] [127:0] $end
+       $var logic 128 /$ sub5_in[1][2] [127:0] $end
       $upscope $end
      $upscope $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array sub5_out $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [0] $end
-       $var wire 8 *$ sub5_out[0][0] [7:0] $end
-       $var wire 8 +$ sub5_out[0][1] [7:0] $end
-       $var wire 8 ,$ sub5_out[0][2] [7:0] $end
+       $var wire 8 0$ sub5_out[0][0] [7:0] $end
+       $var wire 8 1$ sub5_out[0][1] [7:0] $end
+       $var wire 8 2$ sub5_out[0][2] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [1] $end
-       $var wire 8 -$ sub5_out[1][0] [7:0] $end
-       $var wire 8 .$ sub5_out[1][1] [7:0] $end
-       $var wire 8 /$ sub5_out[1][2] [7:0] $end
+       $var wire 8 3$ sub5_out[1][0] [7:0] $end
+       $var wire 8 4$ sub5_out[1][1] [7:0] $end
+       $var wire 8 5$ sub5_out[1][2] [7:0] $end
       $upscope $end
      $upscope $end
-     $var int 32 0$ count [31:0] $end
-     $var int 32 1$ driven_from_bind [31:0] $end
+     $var int 32 6$ count [31:0] $end
+     $var int 32 7$ driven_from_bind [31:0] $end
      $scope module i_sub4_bound $end
-      $var real_parameter 64 L" P1 $end
-      $var wire 32 1$ driven_from_bind [31:0] $end
+      $var real_parameter 64 P" P1 $end
+      $var wire 32 7$ driven_from_bind [31:0] $end
      $upscope $end
      $scope module i_sub5 $end
-      $var wire 1 2$ clk $end
+      $var wire 1 8$ clk $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array in $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [0] $end
-        $var wire 128 3$ in[0][0] [127:0] $end
-        $var wire 128 4$ in[0][1] [127:0] $end
-        $var wire 128 5$ in[0][2] [127:0] $end
+        $var wire 128 9$ in[0][0] [127:0] $end
+        $var wire 128 :$ in[0][1] [127:0] $end
+        $var wire 128 ;$ in[0][2] [127:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [1] $end
-        $var wire 128 6$ in[1][0] [127:0] $end
-        $var wire 128 7$ in[1][1] [127:0] $end
-        $var wire 128 8$ in[1][2] [127:0] $end
+        $var wire 128 <$ in[1][0] [127:0] $end
+        $var wire 128 =$ in[1][1] [127:0] $end
+        $var wire 128 >$ in[1][2] [127:0] $end
        $upscope $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array out $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [0] $end
-        $var wire 8 9$ out[0][0] [7:0] $end
-        $var wire 8 :$ out[0][1] [7:0] $end
-        $var wire 8 ;$ out[0][2] [7:0] $end
+        $var wire 8 ?$ out[0][0] [7:0] $end
+        $var wire 8 @$ out[0][1] [7:0] $end
+        $var wire 8 A$ out[0][2] [7:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [1] $end
-        $var wire 8 <$ out[1][0] [7:0] $end
-        $var wire 8 =$ out[1][1] [7:0] $end
-        $var wire 8 >$ out[1][2] [7:0] $end
+        $var wire 8 B$ out[1][0] [7:0] $end
+        $var wire 8 C$ out[1][1] [7:0] $end
+        $var wire 8 D$ out[1][2] [7:0] $end
        $upscope $end
       $upscope $end
-      $var int 32 ?$ count [31:0] $end
+      $var int 32 E$ count [31:0] $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array val0 $end
-       $var wire 8 @$ val0[0] [7:0] $end
-       $var wire 8 A$ val0[1] [7:0] $end
+       $var wire 8 F$ val0[0] [7:0] $end
+       $var wire 8 G$ val0[1] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array val1 $end
-       $var wire 8 B$ val1[0] [7:0] $end
-       $var wire 8 C$ val1[1] [7:0] $end
+       $var wire 8 H$ val1[0] [7:0] $end
+       $var wire 8 I$ val1[1] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array val2 $end
-       $var wire 8 D$ val2[0] [7:0] $end
-       $var wire 8 E$ val2[1] [7:0] $end
+       $var wire 8 J$ val2[0] [7:0] $end
+       $var wire 8 K$ val2[1] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
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-       $var wire 8 F$ val3[0] [7:0] $end
-       $var wire 8 G$ val3[1] [7:0] $end
+       $var wire 8 L$ val3[0] [7:0] $end
+       $var wire 8 M$ val3[1] [7:0] $end
       $upscope $end
       $scope module i_sub0 $end
-       $var parameter 32 H$ P0 [31:0] $end
-       $var parameter 32 I$ P1 [31:0] $end
+       $var parameter 32 N$ P0 [31:0] $end
+       $var parameter 32 O$ P1 [31:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array out $end
-        $var wire 8 J$ out[0] [7:0] $end
-        $var wire 8 K$ out[1] [7:0] $end
+        $var wire 8 P$ out[0] [7:0] $end
+        $var wire 8 Q$ out[1] [7:0] $end
        $upscope $end
       $upscope $end
       $scope module i_sub1 $end
-       $var parameter 32 H$ P0 [31:0] $end
-       $var parameter 32 I$ P1 [31:0] $end
+       $var parameter 32 N$ P0 [31:0] $end
+       $var parameter 32 O$ P1 [31:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array out $end
-        $var wire 8 L$ out[0] [7:0] $end
-        $var wire 8 M$ out[1] [7:0] $end
+        $var wire 8 R$ out[0] [7:0] $end
+        $var wire 8 S$ out[1] [7:0] $end
        $upscope $end
       $upscope $end
       $scope module i_sub2 $end
-       $var parameter 32 H$ P0 [31:0] $end
-       $var parameter 32 I$ P1 [31:0] $end
+       $var parameter 32 N$ P0 [31:0] $end
+       $var parameter 32 O$ P1 [31:0] $end
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        $scope sv_array out $end
-        $var wire 8 N$ out[0] [7:0] $end
-        $var wire 8 O$ out[1] [7:0] $end
+        $var wire 8 T$ out[0] [7:0] $end
+        $var wire 8 U$ out[1] [7:0] $end
        $upscope $end
       $upscope $end
       $scope module i_sub3 $end
-       $var parameter 32 H$ P0 [31:0] $end
-       $var parameter 32 P$ P1 [31:0] $end
+       $var parameter 32 N$ P0 [31:0] $end
+       $var parameter 32 V$ P1 [31:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array out $end
-        $var wire 8 Q$ out[0] [7:0] $end
-        $var wire 8 R$ out[1] [7:0] $end
+        $var wire 8 W$ out[0] [7:0] $end
+        $var wire 8 X$ out[1] [7:0] $end
        $upscope $end
       $upscope $end
      $upscope $end
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diff --git a/test_regress/t/t_trace_hier_block_default_cc_vcd.out b/test_regress/t/t_trace_hier_block_default_cc_vcd.out
index a4fb88d91..5e754ef6b 100644
--- a/test_regress/t/t_trace_hier_block_default_cc_vcd.out
+++ b/test_regress/t/t_trace_hier_block_default_cc_vcd.out
@@ -1,34 +1,34 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module top $end
-  $var wire 1 Q! clk $end
+  $var wire 1 U! clk $end
   $scope module stateless_pkg $end
-   $var wire 32 h! ONE [31:0] $end
+   $var wire 32 \! ONE [31:0] $end
   $upscope $end
   $scope module t $end
-   $var wire 32 T! PARAM_A [31:0] $end
-   $var wire 32 U! PARAM_B [31:0] $end
-   $var wire 1 Q! clk $end
-   $var wire 8 6! out0 [7:0] $end
-   $var wire 8 7! out1 [7:0] $end
-   $var wire 8 8! out2 [7:0] $end
-   $var wire 8 R! out3 [7:0] $end
+   $var wire 32 V! PARAM_A [31:0] $end
+   $var wire 32 W! PARAM_B [31:0] $end
+   $var wire 1 U! clk $end
+   $var wire 8 :! out0 [7:0] $end
+   $var wire 8 ;! out1 [7:0] $end
+   $var wire 8 <! out2 [7:0] $end
+   $var wire 8 7! out3 [7:0] $end
    $var wire 8 & out3_2 [7:0] $end
    $var wire 8 ' out5 [7:0] $end
    $var wire 8 ( out6 [7:0] $end
    $var wire 32 ) count [31:0] $end
    $scope module i_delay0 $end
-    $var wire 32 V! N [31:0] $end
-    $var wire 32 W! WIDTH [31:0] $end
-    $var wire 1 Q! clk $end
-    $var wire 8 R! in [7:0] $end
+    $var wire 32 X! N [31:0] $end
+    $var wire 32 Y! WIDTH [31:0] $end
+    $var wire 1 U! clk $end
+    $var wire 8 7! in [7:0] $end
     $var wire 8 ' out [7:0] $end
     $var wire 8 * tmp [7:0] $end
     $scope module genblk1 $end
      $scope module i_delay $end
-      $var wire 32 X! N [31:0] $end
-      $var wire 32 W! WIDTH [31:0] $end
-      $var wire 1 Q! clk $end
+      $var wire 32 Z! N [31:0] $end
+      $var wire 32 Y! WIDTH [31:0] $end
+      $var wire 1 U! clk $end
       $var wire 8 * in [7:0] $end
       $var wire 8 ' out [7:0] $end
       $var wire 8 ' tmp [7:0] $end
@@ -36,25 +36,25 @@ $timescale 1ps $end
     $upscope $end
    $upscope $end
    $scope module i_delay1 $end
-    $var wire 32 Y! N [31:0] $end
-    $var wire 32 W! WIDTH [31:0] $end
-    $var wire 1 Q! clk $end
+    $var wire 32 [! N [31:0] $end
+    $var wire 32 Y! WIDTH [31:0] $end
+    $var wire 1 U! clk $end
     $var wire 8 ' in [7:0] $end
     $var wire 8 ( out [7:0] $end
     $var wire 8 + tmp [7:0] $end
     $scope module genblk1 $end
      $scope module i_delay $end
-      $var wire 32 V! N [31:0] $end
-      $var wire 32 W! WIDTH [31:0] $end
-      $var wire 1 Q! clk $end
+      $var wire 32 X! N [31:0] $end
+      $var wire 32 Y! WIDTH [31:0] $end
+      $var wire 1 U! clk $end
       $var wire 8 + in [7:0] $end
       $var wire 8 ( out [7:0] $end
       $var wire 8 , tmp [7:0] $end
       $scope module genblk1 $end
        $scope module i_delay $end
-        $var wire 32 X! N [31:0] $end
-        $var wire 32 W! WIDTH [31:0] $end
-        $var wire 1 Q! clk $end
+        $var wire 32 Z! N [31:0] $end
+        $var wire 32 Y! WIDTH [31:0] $end
+        $var wire 1 U! clk $end
         $var wire 8 , in [7:0] $end
         $var wire 8 ( out [7:0] $end
         $var wire 8 ( tmp [7:0] $end
@@ -64,27 +64,27 @@ $timescale 1ps $end
     $upscope $end
    $upscope $end
    $scope module i_sub0 $end
-    $var wire 1 Q! clk $end
-    $var wire 8 R! in [7:0] $end
-    $var wire 8 6! out [7:0] $end
+    $var wire 1 U! clk $end
+    $var wire 8 7! in [7:0] $end
+    $var wire 8 :! out [7:0] $end
     $scope module i_sub0 $end
-     $var wire 1 i! clk $end
-     $var wire 8 j! in [7:0] $end
-     $var wire 8 k! out [7:0] $end
-     $var wire 8 l! ff [7:0] $end
+     $var wire 1 k! clk $end
+     $var wire 8 l! in [7:0] $end
+     $var wire 8 m! out [7:0] $end
+     $var wire 8 m! ff [7:0] $end
     $upscope $end
    $upscope $end
    $scope module i_sub1 $end
-    $var wire 1 m! clk $end
-    $var wire 8 n! in [11:4] $end
-    $var wire 8 o! out [7:0] $end
+    $var wire 1 n! clk $end
+    $var wire 8 o! in [11:4] $end
+    $var wire 8 p! out [7:0] $end
     $var wire 8 p! ff [7:0] $end
     $var wire 2 q! enum_v [1:0] $end
    $upscope $end
    $scope module i_sub2 $end
-    $var wire 1 >% clk $end
-    $var wire 8 ?% in [7:0] $end
-    $var wire 8 @% out [7:0] $end
+    $var wire 1 @% clk $end
+    $var wire 8 A% in [7:0] $end
+    $var wire 8 B% out [7:0] $end
     $var wire 8 X" ff [7:0] $end
     $var wire 2 Y" alt_enum_v [1:0] $end
     $scope module i_sub3 $end
@@ -92,325 +92,325 @@ $timescale 1ps $end
      $var wire 8 Z" out_1 [7:0] $end
      $var wire 8 [" out_2 [7:0] $end
      $scope module i_sub3 $end
-      $var wire 8 A% P0 [7:0] $end
-      $var wire 32 B% UNPACKED_ARRAY[0] [31:0] $end
-      $var wire 32 C% UNPACKED_ARRAY[1] [31:0] $end
-      $var wire 16 D% UNUSED [15:0] $end
-      $var wire 2 E% ENUM [1:0] $end
-      $var wire 1 >% clk $end
+      $var wire 8 C% P0 [7:0] $end
+      $var wire 32 D% UNPACKED_ARRAY[0] [31:0] $end
+      $var wire 32 E% UNPACKED_ARRAY[1] [31:0] $end
+      $var wire 16 F% UNUSED [15:0] $end
+      $var wire 2 G% ENUM [1:0] $end
+      $var wire 1 @% clk $end
       $var wire 8 X" in [7:0] $end
       $var wire 8 Z" out [7:0] $end
       $var wire 8 \" ff [7:0] $end
       $var wire 8 Z" out4 [7:0] $end
       $var wire 8 ]" out4_2 [7:0] $end
       $scope module i_sub4_0 $end
-       $var wire 32 F% P0 [31:0] $end
-       $var real 64 G% P1 $end
-       $var real 64 I% P3 $end
-       $var wire 1 >% clk $end
-       $var wire 8 \" in [7:0] $end
+       $var wire 32 J% P0 [31:0] $end
+       $var real 64 K% P1 $end
+       $var real 64 M% P3 $end
+       $var wire 1 @% clk $end
+       $var wire 8 `" in [7:0] $end
        $var wire 8 Z" out [7:0] $end
        $var wire 8 Z" ff [7:0] $end
-       $var wire 128 ^" sub5_in[0][0] [127:0] $end
-       $var wire 128 b" sub5_in[0][1] [127:0] $end
-       $var wire 128 f" sub5_in[0][2] [127:0] $end
-       $var wire 128 j" sub5_in[1][0] [127:0] $end
-       $var wire 128 n" sub5_in[1][1] [127:0] $end
-       $var wire 128 r" sub5_in[1][2] [127:0] $end
-       $var wire 8 v" sub5_out[0][0] [7:0] $end
-       $var wire 8 w" sub5_out[0][1] [7:0] $end
-       $var wire 8 x" sub5_out[0][2] [7:0] $end
-       $var wire 8 y" sub5_out[1][0] [7:0] $end
-       $var wire 8 z" sub5_out[1][1] [7:0] $end
-       $var wire 8 {" sub5_out[1][2] [7:0] $end
-       $var wire 32 |" count [31:0] $end
+       $var wire 128 a" sub5_in[0][0] [127:0] $end
+       $var wire 128 e" sub5_in[0][1] [127:0] $end
+       $var wire 128 i" sub5_in[0][2] [127:0] $end
+       $var wire 128 m" sub5_in[1][0] [127:0] $end
+       $var wire 128 q" sub5_in[1][1] [127:0] $end
+       $var wire 128 u" sub5_in[1][2] [127:0] $end
+       $var wire 8 y" sub5_out[0][0] [7:0] $end
+       $var wire 8 z" sub5_out[0][1] [7:0] $end
+       $var wire 8 {" sub5_out[0][2] [7:0] $end
+       $var wire 8 |" sub5_out[1][0] [7:0] $end
+       $var wire 8 }" sub5_out[1][1] [7:0] $end
+       $var wire 8 ~" sub5_out[1][2] [7:0] $end
+       $var wire 32 !# count [31:0] $end
        $var wire 32 r! driven_from_bind [31:0] $end
        $scope module i_sub4_bound $end
-        $var real 64 G% P1 $end
+        $var real 64 K% P1 $end
         $var wire 32 r! driven_from_bind [31:0] $end
        $upscope $end
        $scope module i_sub5 $end
-        $var wire 1 >% clk $end
-        $var wire 128 }" in[0][0] [127:0] $end
-        $var wire 128 ## in[0][1] [127:0] $end
-        $var wire 128 '# in[0][2] [127:0] $end
-        $var wire 128 +# in[1][0] [127:0] $end
-        $var wire 128 /# in[1][1] [127:0] $end
-        $var wire 128 3# in[1][2] [127:0] $end
-        $var wire 8 7# out[0][0] [7:0] $end
-        $var wire 8 8# out[0][1] [7:0] $end
-        $var wire 8 9# out[0][2] [7:0] $end
-        $var wire 8 :# out[1][0] [7:0] $end
-        $var wire 8 ;# out[1][1] [7:0] $end
-        $var wire 8 <# out[1][2] [7:0] $end
-        $var wire 32 =# count [31:0] $end
-        $var wire 8 s! val0[0] [7:0] $end
-        $var wire 8 t! val0[1] [7:0] $end
-        $var wire 8 u! val1[0] [7:0] $end
-        $var wire 8 v! val1[1] [7:0] $end
-        $var wire 8 w! val2[0] [7:0] $end
-        $var wire 8 x! val2[1] [7:0] $end
-        $var wire 8 y! val3[0] [7:0] $end
-        $var wire 8 z! val3[1] [7:0] $end
+        $var wire 1 @% clk $end
+        $var wire 128 "$ in[0][0] [127:0] $end
+        $var wire 128 &$ in[0][1] [127:0] $end
+        $var wire 128 *$ in[0][2] [127:0] $end
+        $var wire 128 .$ in[1][0] [127:0] $end
+        $var wire 128 2$ in[1][1] [127:0] $end
+        $var wire 128 6$ in[1][2] [127:0] $end
+        $var wire 8 :$ out[0][0] [7:0] $end
+        $var wire 8 ;$ out[0][1] [7:0] $end
+        $var wire 8 <$ out[0][2] [7:0] $end
+        $var wire 8 =$ out[1][0] [7:0] $end
+        $var wire 8 >$ out[1][1] [7:0] $end
+        $var wire 8 ?$ out[1][2] [7:0] $end
+        $var wire 32 @$ count [31:0] $end
+        $var wire 8 v! val0[0] [7:0] $end
+        $var wire 8 w! val0[1] [7:0] $end
+        $var wire 8 x! val1[0] [7:0] $end
+        $var wire 8 y! val1[1] [7:0] $end
+        $var wire 8 z! val2[0] [7:0] $end
+        $var wire 8 {! val2[1] [7:0] $end
+        $var wire 8 |! val3[0] [7:0] $end
+        $var wire 8 }! val3[1] [7:0] $end
         $scope module i_sub0 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 L% P1 [31:0] $end
-         $var wire 8 {! out[0] [7:0] $end
-         $var wire 8 |! out[1] [7:0] $end
+         $var wire 32 Q% P0 [31:0] $end
+         $var wire 32 R% P1 [31:0] $end
+         $var wire 8 8" out[0] [7:0] $end
+         $var wire 8 9" out[1] [7:0] $end
         $upscope $end
         $scope module i_sub1 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 L% P1 [31:0] $end
-         $var wire 8 }! out[0] [7:0] $end
-         $var wire 8 ~! out[1] [7:0] $end
+         $var wire 32 Q% P0 [31:0] $end
+         $var wire 32 R% P1 [31:0] $end
+         $var wire 8 :" out[0] [7:0] $end
+         $var wire 8 ;" out[1] [7:0] $end
         $upscope $end
         $scope module i_sub2 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 L% P1 [31:0] $end
-         $var wire 8 !" out[0] [7:0] $end
-         $var wire 8 "" out[1] [7:0] $end
+         $var wire 32 Q% P0 [31:0] $end
+         $var wire 32 R% P1 [31:0] $end
+         $var wire 8 <" out[0] [7:0] $end
+         $var wire 8 =" out[1] [7:0] $end
         $upscope $end
         $scope module i_sub3 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 M% P1 [31:0] $end
-         $var wire 8 #" out[0] [7:0] $end
-         $var wire 8 $" out[1] [7:0] $end
+         $var wire 32 Q% P0 [31:0] $end
+         $var wire 32 S% P1 [31:0] $end
+         $var wire 8 P" out[0] [7:0] $end
+         $var wire 8 Q" out[1] [7:0] $end
         $upscope $end
        $upscope $end
       $upscope $end
       $scope module i_sub4_1 $end
-       $var wire 32 F% P0 [31:0] $end
-       $var real 64 G% P1 $end
-       $var real 64 N% P3 $end
-       $var wire 1 >% clk $end
-       $var wire 8 \" in [7:0] $end
+       $var wire 32 J% P0 [31:0] $end
+       $var real 64 K% P1 $end
+       $var real 64 O% P3 $end
+       $var wire 1 @% clk $end
+       $var wire 8 `" in [7:0] $end
        $var wire 8 ]" out [7:0] $end
        $var wire 8 ]" ff [7:0] $end
-       $var wire 128 ># sub5_in[0][0] [127:0] $end
-       $var wire 128 B# sub5_in[0][1] [127:0] $end
-       $var wire 128 F# sub5_in[0][2] [127:0] $end
-       $var wire 128 J# sub5_in[1][0] [127:0] $end
-       $var wire 128 N# sub5_in[1][1] [127:0] $end
-       $var wire 128 R# sub5_in[1][2] [127:0] $end
-       $var wire 8 V# sub5_out[0][0] [7:0] $end
-       $var wire 8 W# sub5_out[0][1] [7:0] $end
-       $var wire 8 X# sub5_out[0][2] [7:0] $end
-       $var wire 8 Y# sub5_out[1][0] [7:0] $end
-       $var wire 8 Z# sub5_out[1][1] [7:0] $end
-       $var wire 8 [# sub5_out[1][2] [7:0] $end
-       $var wire 32 \# count [31:0] $end
-       $var wire 32 %" driven_from_bind [31:0] $end
+       $var wire 128 B# sub5_in[0][0] [127:0] $end
+       $var wire 128 F# sub5_in[0][1] [127:0] $end
+       $var wire 128 J# sub5_in[0][2] [127:0] $end
+       $var wire 128 N# sub5_in[1][0] [127:0] $end
+       $var wire 128 R# sub5_in[1][1] [127:0] $end
+       $var wire 128 V# sub5_in[1][2] [127:0] $end
+       $var wire 8 Z# sub5_out[0][0] [7:0] $end
+       $var wire 8 [# sub5_out[0][1] [7:0] $end
+       $var wire 8 \# sub5_out[0][2] [7:0] $end
+       $var wire 8 ]# sub5_out[1][0] [7:0] $end
+       $var wire 8 ^# sub5_out[1][1] [7:0] $end
+       $var wire 8 _# sub5_out[1][2] [7:0] $end
+       $var wire 32 `# count [31:0] $end
+       $var wire 32 t! driven_from_bind [31:0] $end
        $scope module i_sub4_bound $end
-        $var real 64 G% P1 $end
-        $var wire 32 %" driven_from_bind [31:0] $end
+        $var real 64 K% P1 $end
+        $var wire 32 t! driven_from_bind [31:0] $end
        $upscope $end
        $scope module i_sub5 $end
-        $var wire 1 >% clk $end
-        $var wire 128 ]# in[0][0] [127:0] $end
-        $var wire 128 a# in[0][1] [127:0] $end
-        $var wire 128 e# in[0][2] [127:0] $end
-        $var wire 128 i# in[1][0] [127:0] $end
-        $var wire 128 m# in[1][1] [127:0] $end
-        $var wire 128 q# in[1][2] [127:0] $end
-        $var wire 8 u# out[0][0] [7:0] $end
-        $var wire 8 v# out[0][1] [7:0] $end
-        $var wire 8 w# out[0][2] [7:0] $end
-        $var wire 8 x# out[1][0] [7:0] $end
-        $var wire 8 y# out[1][1] [7:0] $end
-        $var wire 8 z# out[1][2] [7:0] $end
-        $var wire 32 {# count [31:0] $end
-        $var wire 8 &" val0[0] [7:0] $end
-        $var wire 8 '" val0[1] [7:0] $end
-        $var wire 8 (" val1[0] [7:0] $end
-        $var wire 8 )" val1[1] [7:0] $end
-        $var wire 8 *" val2[0] [7:0] $end
-        $var wire 8 +" val2[1] [7:0] $end
-        $var wire 8 ," val3[0] [7:0] $end
-        $var wire 8 -" val3[1] [7:0] $end
+        $var wire 1 @% clk $end
+        $var wire 128 A$ in[0][0] [127:0] $end
+        $var wire 128 E$ in[0][1] [127:0] $end
+        $var wire 128 I$ in[0][2] [127:0] $end
+        $var wire 128 M$ in[1][0] [127:0] $end
+        $var wire 128 Q$ in[1][1] [127:0] $end
+        $var wire 128 U$ in[1][2] [127:0] $end
+        $var wire 8 Y$ out[0][0] [7:0] $end
+        $var wire 8 Z$ out[0][1] [7:0] $end
+        $var wire 8 [$ out[0][2] [7:0] $end
+        $var wire 8 \$ out[1][0] [7:0] $end
+        $var wire 8 ]$ out[1][1] [7:0] $end
+        $var wire 8 ^$ out[1][2] [7:0] $end
+        $var wire 32 _$ count [31:0] $end
+        $var wire 8 ~! val0[0] [7:0] $end
+        $var wire 8 !" val0[1] [7:0] $end
+        $var wire 8 "" val1[0] [7:0] $end
+        $var wire 8 #" val1[1] [7:0] $end
+        $var wire 8 $" val2[0] [7:0] $end
+        $var wire 8 %" val2[1] [7:0] $end
+        $var wire 8 &" val3[0] [7:0] $end
+        $var wire 8 '" val3[1] [7:0] $end
         $scope module i_sub0 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 L% P1 [31:0] $end
-         $var wire 8 ." out[0] [7:0] $end
-         $var wire 8 /" out[1] [7:0] $end
+         $var wire 32 Q% P0 [31:0] $end
+         $var wire 32 R% P1 [31:0] $end
+         $var wire 8 >" out[0] [7:0] $end
+         $var wire 8 ?" out[1] [7:0] $end
         $upscope $end
         $scope module i_sub1 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 L% P1 [31:0] $end
-         $var wire 8 0" out[0] [7:0] $end
-         $var wire 8 1" out[1] [7:0] $end
+         $var wire 32 Q% P0 [31:0] $end
+         $var wire 32 R% P1 [31:0] $end
+         $var wire 8 @" out[0] [7:0] $end
+         $var wire 8 A" out[1] [7:0] $end
         $upscope $end
         $scope module i_sub2 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 L% P1 [31:0] $end
-         $var wire 8 2" out[0] [7:0] $end
-         $var wire 8 3" out[1] [7:0] $end
+         $var wire 32 Q% P0 [31:0] $end
+         $var wire 32 R% P1 [31:0] $end
+         $var wire 8 B" out[0] [7:0] $end
+         $var wire 8 C" out[1] [7:0] $end
         $upscope $end
         $scope module i_sub3 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 M% P1 [31:0] $end
-         $var wire 8 4" out[0] [7:0] $end
-         $var wire 8 5" out[1] [7:0] $end
+         $var wire 32 Q% P0 [31:0] $end
+         $var wire 32 S% P1 [31:0] $end
+         $var wire 8 R" out[0] [7:0] $end
+         $var wire 8 S" out[1] [7:0] $end
         $upscope $end
        $upscope $end
       $upscope $end
      $upscope $end
      $scope module i_sub3_2 $end
-      $var wire 8 A% P0 [7:0] $end
-      $var wire 32 P% UNPACKED_ARRAY[0] [31:0] $end
-      $var wire 32 Q% UNPACKED_ARRAY[1] [31:0] $end
-      $var wire 16 D% UNUSED [15:0] $end
-      $var wire 2 E% ENUM [1:0] $end
-      $var wire 1 >% clk $end
+      $var wire 8 C% P0 [7:0] $end
+      $var wire 32 H% UNPACKED_ARRAY[0] [31:0] $end
+      $var wire 32 I% UNPACKED_ARRAY[1] [31:0] $end
+      $var wire 16 F% UNUSED [15:0] $end
+      $var wire 2 G% ENUM [1:0] $end
+      $var wire 1 @% clk $end
       $var wire 8 X" in [7:0] $end
       $var wire 8 [" out [7:0] $end
-      $var wire 8 |# ff [7:0] $end
+      $var wire 8 ^" ff [7:0] $end
       $var wire 8 [" out4 [7:0] $end
-      $var wire 8 }# out4_2 [7:0] $end
+      $var wire 8 _" out4_2 [7:0] $end
       $scope module i_sub4_0 $end
-       $var wire 32 F% P0 [31:0] $end
-       $var real 64 G% P1 $end
-       $var real 64 I% P3 $end
-       $var wire 1 >% clk $end
-       $var wire 8 |# in [7:0] $end
+       $var wire 32 J% P0 [31:0] $end
+       $var real 64 K% P1 $end
+       $var real 64 M% P3 $end
+       $var wire 1 @% clk $end
+       $var wire 8 "# in [7:0] $end
        $var wire 8 [" out [7:0] $end
        $var wire 8 [" ff [7:0] $end
-       $var wire 128 ~# sub5_in[0][0] [127:0] $end
-       $var wire 128 $$ sub5_in[0][1] [127:0] $end
-       $var wire 128 ($ sub5_in[0][2] [127:0] $end
-       $var wire 128 ,$ sub5_in[1][0] [127:0] $end
-       $var wire 128 0$ sub5_in[1][1] [127:0] $end
-       $var wire 128 4$ sub5_in[1][2] [127:0] $end
-       $var wire 8 8$ sub5_out[0][0] [7:0] $end
-       $var wire 8 9$ sub5_out[0][1] [7:0] $end
-       $var wire 8 :$ sub5_out[0][2] [7:0] $end
-       $var wire 8 ;$ sub5_out[1][0] [7:0] $end
-       $var wire 8 <$ sub5_out[1][1] [7:0] $end
-       $var wire 8 =$ sub5_out[1][2] [7:0] $end
-       $var wire 32 >$ count [31:0] $end
-       $var wire 32 6" driven_from_bind [31:0] $end
+       $var wire 128 ## sub5_in[0][0] [127:0] $end
+       $var wire 128 '# sub5_in[0][1] [127:0] $end
+       $var wire 128 +# sub5_in[0][2] [127:0] $end
+       $var wire 128 /# sub5_in[1][0] [127:0] $end
+       $var wire 128 3# sub5_in[1][1] [127:0] $end
+       $var wire 128 7# sub5_in[1][2] [127:0] $end
+       $var wire 8 ;# sub5_out[0][0] [7:0] $end
+       $var wire 8 <# sub5_out[0][1] [7:0] $end
+       $var wire 8 =# sub5_out[0][2] [7:0] $end
+       $var wire 8 ># sub5_out[1][0] [7:0] $end
+       $var wire 8 ?# sub5_out[1][1] [7:0] $end
+       $var wire 8 @# sub5_out[1][2] [7:0] $end
+       $var wire 32 A# count [31:0] $end
+       $var wire 32 s! driven_from_bind [31:0] $end
        $scope module i_sub4_bound $end
-        $var real 64 G% P1 $end
-        $var wire 32 6" driven_from_bind [31:0] $end
+        $var real 64 K% P1 $end
+        $var wire 32 s! driven_from_bind [31:0] $end
        $upscope $end
        $scope module i_sub5 $end
-        $var wire 1 >% clk $end
-        $var wire 128 ?$ in[0][0] [127:0] $end
-        $var wire 128 C$ in[0][1] [127:0] $end
-        $var wire 128 G$ in[0][2] [127:0] $end
-        $var wire 128 K$ in[1][0] [127:0] $end
-        $var wire 128 O$ in[1][1] [127:0] $end
-        $var wire 128 S$ in[1][2] [127:0] $end
-        $var wire 8 W$ out[0][0] [7:0] $end
-        $var wire 8 X$ out[0][1] [7:0] $end
-        $var wire 8 Y$ out[0][2] [7:0] $end
-        $var wire 8 Z$ out[1][0] [7:0] $end
-        $var wire 8 [$ out[1][1] [7:0] $end
-        $var wire 8 \$ out[1][2] [7:0] $end
-        $var wire 32 ]$ count [31:0] $end
-        $var wire 8 7" val0[0] [7:0] $end
-        $var wire 8 8" val0[1] [7:0] $end
-        $var wire 8 9" val1[0] [7:0] $end
-        $var wire 8 :" val1[1] [7:0] $end
-        $var wire 8 ;" val2[0] [7:0] $end
-        $var wire 8 <" val2[1] [7:0] $end
-        $var wire 8 =" val3[0] [7:0] $end
-        $var wire 8 >" val3[1] [7:0] $end
+        $var wire 1 @% clk $end
+        $var wire 128 `$ in[0][0] [127:0] $end
+        $var wire 128 d$ in[0][1] [127:0] $end
+        $var wire 128 h$ in[0][2] [127:0] $end
+        $var wire 128 l$ in[1][0] [127:0] $end
+        $var wire 128 p$ in[1][1] [127:0] $end
+        $var wire 128 t$ in[1][2] [127:0] $end
+        $var wire 8 x$ out[0][0] [7:0] $end
+        $var wire 8 y$ out[0][1] [7:0] $end
+        $var wire 8 z$ out[0][2] [7:0] $end
+        $var wire 8 {$ out[1][0] [7:0] $end
+        $var wire 8 |$ out[1][1] [7:0] $end
+        $var wire 8 }$ out[1][2] [7:0] $end
+        $var wire 32 ~$ count [31:0] $end
+        $var wire 8 (" val0[0] [7:0] $end
+        $var wire 8 )" val0[1] [7:0] $end
+        $var wire 8 *" val1[0] [7:0] $end
+        $var wire 8 +" val1[1] [7:0] $end
+        $var wire 8 ," val2[0] [7:0] $end
+        $var wire 8 -" val2[1] [7:0] $end
+        $var wire 8 ." val3[0] [7:0] $end
+        $var wire 8 /" val3[1] [7:0] $end
         $scope module i_sub0 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 L% P1 [31:0] $end
-         $var wire 8 ?" out[0] [7:0] $end
-         $var wire 8 @" out[1] [7:0] $end
+         $var wire 32 Q% P0 [31:0] $end
+         $var wire 32 R% P1 [31:0] $end
+         $var wire 8 D" out[0] [7:0] $end
+         $var wire 8 E" out[1] [7:0] $end
         $upscope $end
         $scope module i_sub1 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 L% P1 [31:0] $end
-         $var wire 8 A" out[0] [7:0] $end
-         $var wire 8 B" out[1] [7:0] $end
+         $var wire 32 Q% P0 [31:0] $end
+         $var wire 32 R% P1 [31:0] $end
+         $var wire 8 F" out[0] [7:0] $end
+         $var wire 8 G" out[1] [7:0] $end
         $upscope $end
         $scope module i_sub2 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 L% P1 [31:0] $end
-         $var wire 8 C" out[0] [7:0] $end
-         $var wire 8 D" out[1] [7:0] $end
+         $var wire 32 Q% P0 [31:0] $end
+         $var wire 32 R% P1 [31:0] $end
+         $var wire 8 H" out[0] [7:0] $end
+         $var wire 8 I" out[1] [7:0] $end
         $upscope $end
         $scope module i_sub3 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 M% P1 [31:0] $end
-         $var wire 8 E" out[0] [7:0] $end
-         $var wire 8 F" out[1] [7:0] $end
+         $var wire 32 Q% P0 [31:0] $end
+         $var wire 32 S% P1 [31:0] $end
+         $var wire 8 T" out[0] [7:0] $end
+         $var wire 8 U" out[1] [7:0] $end
         $upscope $end
        $upscope $end
       $upscope $end
       $scope module i_sub4_1 $end
-       $var wire 32 F% P0 [31:0] $end
-       $var real 64 G% P1 $end
-       $var real 64 N% P3 $end
-       $var wire 1 >% clk $end
-       $var wire 8 |# in [7:0] $end
-       $var wire 8 }# out [7:0] $end
-       $var wire 8 }# ff [7:0] $end
-       $var wire 128 ^$ sub5_in[0][0] [127:0] $end
-       $var wire 128 b$ sub5_in[0][1] [127:0] $end
-       $var wire 128 f$ sub5_in[0][2] [127:0] $end
-       $var wire 128 j$ sub5_in[1][0] [127:0] $end
-       $var wire 128 n$ sub5_in[1][1] [127:0] $end
-       $var wire 128 r$ sub5_in[1][2] [127:0] $end
-       $var wire 8 v$ sub5_out[0][0] [7:0] $end
-       $var wire 8 w$ sub5_out[0][1] [7:0] $end
-       $var wire 8 x$ sub5_out[0][2] [7:0] $end
-       $var wire 8 y$ sub5_out[1][0] [7:0] $end
-       $var wire 8 z$ sub5_out[1][1] [7:0] $end
-       $var wire 8 {$ sub5_out[1][2] [7:0] $end
-       $var wire 32 |$ count [31:0] $end
-       $var wire 32 G" driven_from_bind [31:0] $end
+       $var wire 32 J% P0 [31:0] $end
+       $var real 64 K% P1 $end
+       $var real 64 O% P3 $end
+       $var wire 1 @% clk $end
+       $var wire 8 "# in [7:0] $end
+       $var wire 8 _" out [7:0] $end
+       $var wire 8 _" ff [7:0] $end
+       $var wire 128 a# sub5_in[0][0] [127:0] $end
+       $var wire 128 e# sub5_in[0][1] [127:0] $end
+       $var wire 128 i# sub5_in[0][2] [127:0] $end
+       $var wire 128 m# sub5_in[1][0] [127:0] $end
+       $var wire 128 q# sub5_in[1][1] [127:0] $end
+       $var wire 128 u# sub5_in[1][2] [127:0] $end
+       $var wire 8 y# sub5_out[0][0] [7:0] $end
+       $var wire 8 z# sub5_out[0][1] [7:0] $end
+       $var wire 8 {# sub5_out[0][2] [7:0] $end
+       $var wire 8 |# sub5_out[1][0] [7:0] $end
+       $var wire 8 }# sub5_out[1][1] [7:0] $end
+       $var wire 8 ~# sub5_out[1][2] [7:0] $end
+       $var wire 32 !$ count [31:0] $end
+       $var wire 32 u! driven_from_bind [31:0] $end
        $scope module i_sub4_bound $end
-        $var real 64 G% P1 $end
-        $var wire 32 G" driven_from_bind [31:0] $end
+        $var real 64 K% P1 $end
+        $var wire 32 u! driven_from_bind [31:0] $end
        $upscope $end
        $scope module i_sub5 $end
-        $var wire 1 >% clk $end
-        $var wire 128 }$ in[0][0] [127:0] $end
-        $var wire 128 #% in[0][1] [127:0] $end
-        $var wire 128 '% in[0][2] [127:0] $end
-        $var wire 128 +% in[1][0] [127:0] $end
-        $var wire 128 /% in[1][1] [127:0] $end
-        $var wire 128 3% in[1][2] [127:0] $end
-        $var wire 8 7% out[0][0] [7:0] $end
-        $var wire 8 8% out[0][1] [7:0] $end
-        $var wire 8 9% out[0][2] [7:0] $end
-        $var wire 8 :% out[1][0] [7:0] $end
-        $var wire 8 ;% out[1][1] [7:0] $end
-        $var wire 8 <% out[1][2] [7:0] $end
-        $var wire 32 =% count [31:0] $end
-        $var wire 8 H" val0[0] [7:0] $end
-        $var wire 8 I" val0[1] [7:0] $end
-        $var wire 8 J" val1[0] [7:0] $end
-        $var wire 8 K" val1[1] [7:0] $end
-        $var wire 8 L" val2[0] [7:0] $end
-        $var wire 8 M" val2[1] [7:0] $end
-        $var wire 8 N" val3[0] [7:0] $end
-        $var wire 8 O" val3[1] [7:0] $end
+        $var wire 1 @% clk $end
+        $var wire 128 !% in[0][0] [127:0] $end
+        $var wire 128 %% in[0][1] [127:0] $end
+        $var wire 128 )% in[0][2] [127:0] $end
+        $var wire 128 -% in[1][0] [127:0] $end
+        $var wire 128 1% in[1][1] [127:0] $end
+        $var wire 128 5% in[1][2] [127:0] $end
+        $var wire 8 9% out[0][0] [7:0] $end
+        $var wire 8 :% out[0][1] [7:0] $end
+        $var wire 8 ;% out[0][2] [7:0] $end
+        $var wire 8 <% out[1][0] [7:0] $end
+        $var wire 8 =% out[1][1] [7:0] $end
+        $var wire 8 >% out[1][2] [7:0] $end
+        $var wire 32 ?% count [31:0] $end
+        $var wire 8 0" val0[0] [7:0] $end
+        $var wire 8 1" val0[1] [7:0] $end
+        $var wire 8 2" val1[0] [7:0] $end
+        $var wire 8 3" val1[1] [7:0] $end
+        $var wire 8 4" val2[0] [7:0] $end
+        $var wire 8 5" val2[1] [7:0] $end
+        $var wire 8 6" val3[0] [7:0] $end
+        $var wire 8 7" val3[1] [7:0] $end
         $scope module i_sub0 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 L% P1 [31:0] $end
-         $var wire 8 P" out[0] [7:0] $end
-         $var wire 8 Q" out[1] [7:0] $end
+         $var wire 32 Q% P0 [31:0] $end
+         $var wire 32 R% P1 [31:0] $end
+         $var wire 8 J" out[0] [7:0] $end
+         $var wire 8 K" out[1] [7:0] $end
         $upscope $end
         $scope module i_sub1 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 L% P1 [31:0] $end
-         $var wire 8 R" out[0] [7:0] $end
-         $var wire 8 S" out[1] [7:0] $end
+         $var wire 32 Q% P0 [31:0] $end
+         $var wire 32 R% P1 [31:0] $end
+         $var wire 8 L" out[0] [7:0] $end
+         $var wire 8 M" out[1] [7:0] $end
         $upscope $end
         $scope module i_sub2 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 L% P1 [31:0] $end
-         $var wire 8 T" out[0] [7:0] $end
-         $var wire 8 U" out[1] [7:0] $end
+         $var wire 32 Q% P0 [31:0] $end
+         $var wire 32 R% P1 [31:0] $end
+         $var wire 8 N" out[0] [7:0] $end
+         $var wire 8 O" out[1] [7:0] $end
         $upscope $end
         $scope module i_sub3 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 M% P1 [31:0] $end
+         $var wire 32 Q% P0 [31:0] $end
+         $var wire 32 S% P1 [31:0] $end
          $var wire 8 V" out[0] [7:0] $end
          $var wire 8 W" out[1] [7:0] $end
         $upscope $end
@@ -418,346 +418,346 @@ $timescale 1ps $end
       $upscope $end
      $upscope $end
      $scope module in $end
-      $var wire 1 >% clk $end
+      $var wire 1 @% clk $end
       $var wire 8 X" data [7:0] $end
      $upscope $end
      $scope module out $end
-      $var wire 1 >% clk $end
+      $var wire 1 @% clk $end
       $var wire 8 Z" data [7:0] $end
      $upscope $end
     $upscope $end
     $scope module in_ifs $end
-     $var wire 1 >% clk $end
+     $var wire 1 @% clk $end
      $var wire 8 X" data [7:0] $end
     $upscope $end
     $scope module out_ifs $end
-     $var wire 1 >% clk $end
+     $var wire 1 @% clk $end
      $var wire 8 Z" data [7:0] $end
     $upscope $end
    $upscope $end
    $scope module i_sub3 $end
-    $var wire 8 Z! P0 [7:0] $end
-    $var wire 32 [! UNPACKED_ARRAY[0] [31:0] $end
-    $var wire 32 \! UNPACKED_ARRAY[1] [31:0] $end
-    $var wire 16 ]! UNUSED [15:0] $end
-    $var wire 2 ^! ENUM [1:0] $end
-    $var wire 1 Q! clk $end
-    $var wire 8 8! in [7:0] $end
-    $var wire 8 R! out [7:0] $end
-    $var wire 8 S! ff [7:0] $end
-    $var wire 8 R! out4 [7:0] $end
+    $var wire 8 ]! P0 [7:0] $end
+    $var wire 32 ^! UNPACKED_ARRAY[0] [31:0] $end
+    $var wire 32 _! UNPACKED_ARRAY[1] [31:0] $end
+    $var wire 16 `! UNUSED [15:0] $end
+    $var wire 2 a! ENUM [1:0] $end
+    $var wire 1 U! clk $end
+    $var wire 8 <! in [7:0] $end
+    $var wire 8 7! out [7:0] $end
+    $var wire 8 8! ff [7:0] $end
+    $var wire 8 7! out4 [7:0] $end
     $var wire 8 - out4_2 [7:0] $end
     $scope module i_sub4_0 $end
-     $var wire 32 _! P0 [31:0] $end
-     $var real 64 `! P1 $end
-     $var real 64 b! P3 $end
-     $var wire 1 Q! clk $end
-     $var wire 8 S! in [7:0] $end
-     $var wire 8 R! out [7:0] $end
-     $var wire 8 R! ff [7:0] $end
-     $var wire 128 . sub5_in[0][0] [127:0] $end
-     $var wire 128 2 sub5_in[0][1] [127:0] $end
-     $var wire 128 6 sub5_in[0][2] [127:0] $end
-     $var wire 128 : sub5_in[1][0] [127:0] $end
-     $var wire 128 > sub5_in[1][1] [127:0] $end
-     $var wire 128 B sub5_in[1][2] [127:0] $end
-     $var wire 8 9! sub5_out[0][0] [7:0] $end
-     $var wire 8 :! sub5_out[0][1] [7:0] $end
-     $var wire 8 ;! sub5_out[0][2] [7:0] $end
-     $var wire 8 <! sub5_out[1][0] [7:0] $end
-     $var wire 8 =! sub5_out[1][1] [7:0] $end
-     $var wire 8 >! sub5_out[1][2] [7:0] $end
-     $var wire 32 F count [31:0] $end
+     $var wire 32 d! P0 [31:0] $end
+     $var real 64 e! P1 $end
+     $var real 64 g! P3 $end
+     $var wire 1 U! clk $end
+     $var wire 8 9! in [7:0] $end
+     $var wire 8 7! out [7:0] $end
+     $var wire 8 7! ff [7:0] $end
+     $var wire 128 0 sub5_in[0][0] [127:0] $end
+     $var wire 128 4 sub5_in[0][1] [127:0] $end
+     $var wire 128 8 sub5_in[0][2] [127:0] $end
+     $var wire 128 < sub5_in[1][0] [127:0] $end
+     $var wire 128 @ sub5_in[1][1] [127:0] $end
+     $var wire 128 D sub5_in[1][2] [127:0] $end
+     $var wire 8 =! sub5_out[0][0] [7:0] $end
+     $var wire 8 >! sub5_out[0][1] [7:0] $end
+     $var wire 8 ?! sub5_out[0][2] [7:0] $end
+     $var wire 8 @! sub5_out[1][0] [7:0] $end
+     $var wire 8 A! sub5_out[1][1] [7:0] $end
+     $var wire 8 B! sub5_out[1][2] [7:0] $end
+     $var wire 32 H count [31:0] $end
      $var wire 32 " driven_from_bind [31:0] $end
      $scope module i_sub4_bound $end
-      $var real 64 `! P1 $end
+      $var real 64 e! P1 $end
       $var wire 32 " driven_from_bind [31:0] $end
      $upscope $end
      $scope module i_sub5 $end
-      $var wire 1 #& clk $end
-      $var wire 128 b% in[0][0] [127:0] $end
-      $var wire 128 f% in[0][1] [127:0] $end
-      $var wire 128 j% in[0][2] [127:0] $end
-      $var wire 128 n% in[1][0] [127:0] $end
-      $var wire 128 r% in[1][1] [127:0] $end
-      $var wire 128 v% in[1][2] [127:0] $end
-      $var wire 8 z% out[0][0] [7:0] $end
-      $var wire 8 {% out[0][1] [7:0] $end
-      $var wire 8 |% out[0][2] [7:0] $end
-      $var wire 8 }% out[1][0] [7:0] $end
-      $var wire 8 ~% out[1][1] [7:0] $end
-      $var wire 8 !& out[1][2] [7:0] $end
-      $var wire 32 "& count [31:0] $end
-      $var wire 8 R% val0[0] [7:0] $end
-      $var wire 8 S% val0[1] [7:0] $end
-      $var wire 8 T% val1[0] [7:0] $end
-      $var wire 8 U% val1[1] [7:0] $end
-      $var wire 8 V% val2[0] [7:0] $end
-      $var wire 8 W% val2[1] [7:0] $end
-      $var wire 8 X% val3[0] [7:0] $end
-      $var wire 8 Y% val3[1] [7:0] $end
+      $var wire 1 |% clk $end
+      $var wire 128 d% in[0][0] [127:0] $end
+      $var wire 128 h% in[0][1] [127:0] $end
+      $var wire 128 l% in[0][2] [127:0] $end
+      $var wire 128 p% in[1][0] [127:0] $end
+      $var wire 128 t% in[1][1] [127:0] $end
+      $var wire 128 x% in[1][2] [127:0] $end
+      $var wire 8 }% out[0][0] [7:0] $end
+      $var wire 8 ~% out[0][1] [7:0] $end
+      $var wire 8 !& out[0][2] [7:0] $end
+      $var wire 8 "& out[1][0] [7:0] $end
+      $var wire 8 #& out[1][1] [7:0] $end
+      $var wire 8 $& out[1][2] [7:0] $end
+      $var wire 32 %& count [31:0] $end
+      $var wire 8 T% val0[0] [7:0] $end
+      $var wire 8 U% val0[1] [7:0] $end
+      $var wire 8 V% val1[0] [7:0] $end
+      $var wire 8 W% val1[1] [7:0] $end
+      $var wire 8 X% val2[0] [7:0] $end
+      $var wire 8 Y% val2[1] [7:0] $end
+      $var wire 8 Z% val3[0] [7:0] $end
+      $var wire 8 [% val3[1] [7:0] $end
       $scope module i_sub0 $end
-       $var wire 32 $& P0 [31:0] $end
-       $var wire 32 %& P1 [31:0] $end
-       $var wire 8 Z% out[0] [7:0] $end
-       $var wire 8 [% out[1] [7:0] $end
-      $upscope $end
-      $scope module i_sub1 $end
-       $var wire 32 $& P0 [31:0] $end
-       $var wire 32 %& P1 [31:0] $end
+       $var wire 32 && P0 [31:0] $end
+       $var wire 32 '& P1 [31:0] $end
        $var wire 8 \% out[0] [7:0] $end
        $var wire 8 ]% out[1] [7:0] $end
       $upscope $end
-      $scope module i_sub2 $end
-       $var wire 32 $& P0 [31:0] $end
-       $var wire 32 %& P1 [31:0] $end
+      $scope module i_sub1 $end
+       $var wire 32 && P0 [31:0] $end
+       $var wire 32 '& P1 [31:0] $end
        $var wire 8 ^% out[0] [7:0] $end
        $var wire 8 _% out[1] [7:0] $end
       $upscope $end
-      $scope module i_sub3 $end
-       $var wire 32 $& P0 [31:0] $end
-       $var wire 32 && P1 [31:0] $end
+      $scope module i_sub2 $end
+       $var wire 32 && P0 [31:0] $end
+       $var wire 32 '& P1 [31:0] $end
        $var wire 8 `% out[0] [7:0] $end
        $var wire 8 a% out[1] [7:0] $end
       $upscope $end
+      $scope module i_sub3 $end
+       $var wire 32 && P0 [31:0] $end
+       $var wire 32 (& P1 [31:0] $end
+       $var wire 8 b% out[0] [7:0] $end
+       $var wire 8 c% out[1] [7:0] $end
+      $upscope $end
      $upscope $end
     $upscope $end
     $scope module i_sub4_1 $end
-     $var wire 32 _! P0 [31:0] $end
-     $var real 64 `! P1 $end
-     $var real 64 d! P3 $end
-     $var wire 1 Q! clk $end
-     $var wire 8 S! in [7:0] $end
+     $var wire 32 d! P0 [31:0] $end
+     $var real 64 e! P1 $end
+     $var real 64 i! P3 $end
+     $var wire 1 U! clk $end
+     $var wire 8 9! in [7:0] $end
      $var wire 8 - out [7:0] $end
      $var wire 8 - ff [7:0] $end
-     $var wire 128 G sub5_in[0][0] [127:0] $end
-     $var wire 128 K sub5_in[0][1] [127:0] $end
-     $var wire 128 O sub5_in[0][2] [127:0] $end
-     $var wire 128 S sub5_in[1][0] [127:0] $end
-     $var wire 128 W sub5_in[1][1] [127:0] $end
-     $var wire 128 [ sub5_in[1][2] [127:0] $end
-     $var wire 8 ?! sub5_out[0][0] [7:0] $end
-     $var wire 8 @! sub5_out[0][1] [7:0] $end
-     $var wire 8 A! sub5_out[0][2] [7:0] $end
-     $var wire 8 B! sub5_out[1][0] [7:0] $end
-     $var wire 8 C! sub5_out[1][1] [7:0] $end
-     $var wire 8 D! sub5_out[1][2] [7:0] $end
-     $var wire 32 _ count [31:0] $end
-     $var wire 32 # driven_from_bind [31:0] $end
+     $var wire 128 c sub5_in[0][0] [127:0] $end
+     $var wire 128 g sub5_in[0][1] [127:0] $end
+     $var wire 128 k sub5_in[0][2] [127:0] $end
+     $var wire 128 o sub5_in[1][0] [127:0] $end
+     $var wire 128 s sub5_in[1][1] [127:0] $end
+     $var wire 128 w sub5_in[1][2] [127:0] $end
+     $var wire 8 I! sub5_out[0][0] [7:0] $end
+     $var wire 8 J! sub5_out[0][1] [7:0] $end
+     $var wire 8 K! sub5_out[0][2] [7:0] $end
+     $var wire 8 L! sub5_out[1][0] [7:0] $end
+     $var wire 8 M! sub5_out[1][1] [7:0] $end
+     $var wire 8 N! sub5_out[1][2] [7:0] $end
+     $var wire 32 { count [31:0] $end
+     $var wire 32 $ driven_from_bind [31:0] $end
      $scope module i_sub4_bound $end
-      $var real 64 `! P1 $end
-      $var wire 32 # driven_from_bind [31:0] $end
+      $var real 64 e! P1 $end
+      $var wire 32 $ driven_from_bind [31:0] $end
      $upscope $end
      $scope module i_sub5 $end
-      $var wire 1 V& clk $end
-      $var wire 128 7& in[0][0] [127:0] $end
-      $var wire 128 ;& in[0][1] [127:0] $end
-      $var wire 128 ?& in[0][2] [127:0] $end
-      $var wire 128 C& in[1][0] [127:0] $end
-      $var wire 128 G& in[1][1] [127:0] $end
-      $var wire 128 K& in[1][2] [127:0] $end
-      $var wire 8 O& out[0][0] [7:0] $end
-      $var wire 8 P& out[0][1] [7:0] $end
-      $var wire 8 Q& out[0][2] [7:0] $end
-      $var wire 8 R& out[1][0] [7:0] $end
-      $var wire 8 S& out[1][1] [7:0] $end
-      $var wire 8 T& out[1][2] [7:0] $end
-      $var wire 32 U& count [31:0] $end
-      $var wire 8 '& val0[0] [7:0] $end
-      $var wire 8 (& val0[1] [7:0] $end
-      $var wire 8 )& val1[0] [7:0] $end
-      $var wire 8 *& val1[1] [7:0] $end
-      $var wire 8 +& val2[0] [7:0] $end
-      $var wire 8 ,& val2[1] [7:0] $end
-      $var wire 8 -& val3[0] [7:0] $end
-      $var wire 8 .& val3[1] [7:0] $end
+      $var wire 1 Q& clk $end
+      $var wire 128 9& in[0][0] [127:0] $end
+      $var wire 128 =& in[0][1] [127:0] $end
+      $var wire 128 A& in[0][2] [127:0] $end
+      $var wire 128 E& in[1][0] [127:0] $end
+      $var wire 128 I& in[1][1] [127:0] $end
+      $var wire 128 M& in[1][2] [127:0] $end
+      $var wire 8 R& out[0][0] [7:0] $end
+      $var wire 8 S& out[0][1] [7:0] $end
+      $var wire 8 T& out[0][2] [7:0] $end
+      $var wire 8 U& out[1][0] [7:0] $end
+      $var wire 8 V& out[1][1] [7:0] $end
+      $var wire 8 W& out[1][2] [7:0] $end
+      $var wire 32 X& count [31:0] $end
+      $var wire 8 )& val0[0] [7:0] $end
+      $var wire 8 *& val0[1] [7:0] $end
+      $var wire 8 +& val1[0] [7:0] $end
+      $var wire 8 ,& val1[1] [7:0] $end
+      $var wire 8 -& val2[0] [7:0] $end
+      $var wire 8 .& val2[1] [7:0] $end
+      $var wire 8 /& val3[0] [7:0] $end
+      $var wire 8 0& val3[1] [7:0] $end
       $scope module i_sub0 $end
-       $var wire 32 W& P0 [31:0] $end
-       $var wire 32 X& P1 [31:0] $end
-       $var wire 8 /& out[0] [7:0] $end
-       $var wire 8 0& out[1] [7:0] $end
-      $upscope $end
-      $scope module i_sub1 $end
-       $var wire 32 W& P0 [31:0] $end
-       $var wire 32 X& P1 [31:0] $end
+       $var wire 32 Y& P0 [31:0] $end
+       $var wire 32 Z& P1 [31:0] $end
        $var wire 8 1& out[0] [7:0] $end
        $var wire 8 2& out[1] [7:0] $end
       $upscope $end
-      $scope module i_sub2 $end
-       $var wire 32 W& P0 [31:0] $end
-       $var wire 32 X& P1 [31:0] $end
+      $scope module i_sub1 $end
+       $var wire 32 Y& P0 [31:0] $end
+       $var wire 32 Z& P1 [31:0] $end
        $var wire 8 3& out[0] [7:0] $end
        $var wire 8 4& out[1] [7:0] $end
       $upscope $end
-      $scope module i_sub3 $end
-       $var wire 32 W& P0 [31:0] $end
-       $var wire 32 Y& P1 [31:0] $end
+      $scope module i_sub2 $end
+       $var wire 32 Y& P0 [31:0] $end
+       $var wire 32 Z& P1 [31:0] $end
        $var wire 8 5& out[0] [7:0] $end
        $var wire 8 6& out[1] [7:0] $end
       $upscope $end
+      $scope module i_sub3 $end
+       $var wire 32 Y& P0 [31:0] $end
+       $var wire 32 [& P1 [31:0] $end
+       $var wire 8 7& out[0] [7:0] $end
+       $var wire 8 8& out[1] [7:0] $end
+      $upscope $end
      $upscope $end
     $upscope $end
    $upscope $end
    $scope module i_sub3_2 $end
-    $var wire 8 Z! P0 [7:0] $end
-    $var wire 32 f! UNPACKED_ARRAY[0] [31:0] $end
-    $var wire 32 g! UNPACKED_ARRAY[1] [31:0] $end
-    $var wire 16 ]! UNUSED [15:0] $end
-    $var wire 2 ^! ENUM [1:0] $end
-    $var wire 1 Q! clk $end
-    $var wire 8 8! in [7:0] $end
+    $var wire 8 ]! P0 [7:0] $end
+    $var wire 32 b! UNPACKED_ARRAY[0] [31:0] $end
+    $var wire 32 c! UNPACKED_ARRAY[1] [31:0] $end
+    $var wire 16 `! UNUSED [15:0] $end
+    $var wire 2 a! ENUM [1:0] $end
+    $var wire 1 U! clk $end
+    $var wire 8 <! in [7:0] $end
     $var wire 8 & out [7:0] $end
-    $var wire 8 ` ff [7:0] $end
+    $var wire 8 . ff [7:0] $end
     $var wire 8 & out4 [7:0] $end
-    $var wire 8 a out4_2 [7:0] $end
+    $var wire 8 / out4_2 [7:0] $end
     $scope module i_sub4_0 $end
-     $var wire 32 _! P0 [31:0] $end
-     $var real 64 `! P1 $end
-     $var real 64 b! P3 $end
-     $var wire 1 Q! clk $end
-     $var wire 8 ` in [7:0] $end
+     $var wire 32 d! P0 [31:0] $end
+     $var real 64 e! P1 $end
+     $var real 64 g! P3 $end
+     $var wire 1 U! clk $end
+     $var wire 8 I in [7:0] $end
      $var wire 8 & out [7:0] $end
      $var wire 8 & ff [7:0] $end
-     $var wire 128 b sub5_in[0][0] [127:0] $end
-     $var wire 128 f sub5_in[0][1] [127:0] $end
-     $var wire 128 j sub5_in[0][2] [127:0] $end
-     $var wire 128 n sub5_in[1][0] [127:0] $end
-     $var wire 128 r sub5_in[1][1] [127:0] $end
-     $var wire 128 v sub5_in[1][2] [127:0] $end
-     $var wire 8 E! sub5_out[0][0] [7:0] $end
-     $var wire 8 F! sub5_out[0][1] [7:0] $end
-     $var wire 8 G! sub5_out[0][2] [7:0] $end
-     $var wire 8 H! sub5_out[1][0] [7:0] $end
-     $var wire 8 I! sub5_out[1][1] [7:0] $end
-     $var wire 8 J! sub5_out[1][2] [7:0] $end
-     $var wire 32 z count [31:0] $end
-     $var wire 32 $ driven_from_bind [31:0] $end
+     $var wire 128 J sub5_in[0][0] [127:0] $end
+     $var wire 128 N sub5_in[0][1] [127:0] $end
+     $var wire 128 R sub5_in[0][2] [127:0] $end
+     $var wire 128 V sub5_in[1][0] [127:0] $end
+     $var wire 128 Z sub5_in[1][1] [127:0] $end
+     $var wire 128 ^ sub5_in[1][2] [127:0] $end
+     $var wire 8 C! sub5_out[0][0] [7:0] $end
+     $var wire 8 D! sub5_out[0][1] [7:0] $end
+     $var wire 8 E! sub5_out[0][2] [7:0] $end
+     $var wire 8 F! sub5_out[1][0] [7:0] $end
+     $var wire 8 G! sub5_out[1][1] [7:0] $end
+     $var wire 8 H! sub5_out[1][2] [7:0] $end
+     $var wire 32 b count [31:0] $end
+     $var wire 32 # driven_from_bind [31:0] $end
      $scope module i_sub4_bound $end
-      $var real 64 `! P1 $end
-      $var wire 32 $ driven_from_bind [31:0] $end
+      $var real 64 e! P1 $end
+      $var wire 32 # driven_from_bind [31:0] $end
      $upscope $end
      $scope module i_sub5 $end
-      $var wire 1 +' clk $end
-      $var wire 128 j& in[0][0] [127:0] $end
-      $var wire 128 n& in[0][1] [127:0] $end
-      $var wire 128 r& in[0][2] [127:0] $end
-      $var wire 128 v& in[1][0] [127:0] $end
-      $var wire 128 z& in[1][1] [127:0] $end
-      $var wire 128 ~& in[1][2] [127:0] $end
-      $var wire 8 $' out[0][0] [7:0] $end
-      $var wire 8 %' out[0][1] [7:0] $end
-      $var wire 8 &' out[0][2] [7:0] $end
-      $var wire 8 '' out[1][0] [7:0] $end
-      $var wire 8 (' out[1][1] [7:0] $end
-      $var wire 8 )' out[1][2] [7:0] $end
-      $var wire 32 *' count [31:0] $end
-      $var wire 8 Z& val0[0] [7:0] $end
-      $var wire 8 [& val0[1] [7:0] $end
-      $var wire 8 \& val1[0] [7:0] $end
-      $var wire 8 ]& val1[1] [7:0] $end
-      $var wire 8 ^& val2[0] [7:0] $end
-      $var wire 8 _& val2[1] [7:0] $end
-      $var wire 8 `& val3[0] [7:0] $end
-      $var wire 8 a& val3[1] [7:0] $end
+      $var wire 1 &' clk $end
+      $var wire 128 l& in[0][0] [127:0] $end
+      $var wire 128 p& in[0][1] [127:0] $end
+      $var wire 128 t& in[0][2] [127:0] $end
+      $var wire 128 x& in[1][0] [127:0] $end
+      $var wire 128 |& in[1][1] [127:0] $end
+      $var wire 128 "' in[1][2] [127:0] $end
+      $var wire 8 '' out[0][0] [7:0] $end
+      $var wire 8 (' out[0][1] [7:0] $end
+      $var wire 8 )' out[0][2] [7:0] $end
+      $var wire 8 *' out[1][0] [7:0] $end
+      $var wire 8 +' out[1][1] [7:0] $end
+      $var wire 8 ,' out[1][2] [7:0] $end
+      $var wire 32 -' count [31:0] $end
+      $var wire 8 \& val0[0] [7:0] $end
+      $var wire 8 ]& val0[1] [7:0] $end
+      $var wire 8 ^& val1[0] [7:0] $end
+      $var wire 8 _& val1[1] [7:0] $end
+      $var wire 8 `& val2[0] [7:0] $end
+      $var wire 8 a& val2[1] [7:0] $end
+      $var wire 8 b& val3[0] [7:0] $end
+      $var wire 8 c& val3[1] [7:0] $end
       $scope module i_sub0 $end
-       $var wire 32 ,' P0 [31:0] $end
-       $var wire 32 -' P1 [31:0] $end
-       $var wire 8 b& out[0] [7:0] $end
-       $var wire 8 c& out[1] [7:0] $end
-      $upscope $end
-      $scope module i_sub1 $end
-       $var wire 32 ,' P0 [31:0] $end
-       $var wire 32 -' P1 [31:0] $end
+       $var wire 32 .' P0 [31:0] $end
+       $var wire 32 /' P1 [31:0] $end
        $var wire 8 d& out[0] [7:0] $end
        $var wire 8 e& out[1] [7:0] $end
       $upscope $end
-      $scope module i_sub2 $end
-       $var wire 32 ,' P0 [31:0] $end
-       $var wire 32 -' P1 [31:0] $end
+      $scope module i_sub1 $end
+       $var wire 32 .' P0 [31:0] $end
+       $var wire 32 /' P1 [31:0] $end
        $var wire 8 f& out[0] [7:0] $end
        $var wire 8 g& out[1] [7:0] $end
       $upscope $end
-      $scope module i_sub3 $end
-       $var wire 32 ,' P0 [31:0] $end
-       $var wire 32 .' P1 [31:0] $end
+      $scope module i_sub2 $end
+       $var wire 32 .' P0 [31:0] $end
+       $var wire 32 /' P1 [31:0] $end
        $var wire 8 h& out[0] [7:0] $end
        $var wire 8 i& out[1] [7:0] $end
       $upscope $end
+      $scope module i_sub3 $end
+       $var wire 32 .' P0 [31:0] $end
+       $var wire 32 0' P1 [31:0] $end
+       $var wire 8 j& out[0] [7:0] $end
+       $var wire 8 k& out[1] [7:0] $end
+      $upscope $end
      $upscope $end
     $upscope $end
     $scope module i_sub4_1 $end
-     $var wire 32 _! P0 [31:0] $end
-     $var real 64 `! P1 $end
-     $var real 64 d! P3 $end
-     $var wire 1 Q! clk $end
-     $var wire 8 ` in [7:0] $end
-     $var wire 8 a out [7:0] $end
-     $var wire 8 a ff [7:0] $end
-     $var wire 128 { sub5_in[0][0] [127:0] $end
-     $var wire 128 !! sub5_in[0][1] [127:0] $end
-     $var wire 128 %! sub5_in[0][2] [127:0] $end
-     $var wire 128 )! sub5_in[1][0] [127:0] $end
-     $var wire 128 -! sub5_in[1][1] [127:0] $end
-     $var wire 128 1! sub5_in[1][2] [127:0] $end
-     $var wire 8 K! sub5_out[0][0] [7:0] $end
-     $var wire 8 L! sub5_out[0][1] [7:0] $end
-     $var wire 8 M! sub5_out[0][2] [7:0] $end
-     $var wire 8 N! sub5_out[1][0] [7:0] $end
-     $var wire 8 O! sub5_out[1][1] [7:0] $end
-     $var wire 8 P! sub5_out[1][2] [7:0] $end
-     $var wire 32 5! count [31:0] $end
+     $var wire 32 d! P0 [31:0] $end
+     $var real 64 e! P1 $end
+     $var real 64 i! P3 $end
+     $var wire 1 U! clk $end
+     $var wire 8 I in [7:0] $end
+     $var wire 8 / out [7:0] $end
+     $var wire 8 / ff [7:0] $end
+     $var wire 128 | sub5_in[0][0] [127:0] $end
+     $var wire 128 "! sub5_in[0][1] [127:0] $end
+     $var wire 128 &! sub5_in[0][2] [127:0] $end
+     $var wire 128 *! sub5_in[1][0] [127:0] $end
+     $var wire 128 .! sub5_in[1][1] [127:0] $end
+     $var wire 128 2! sub5_in[1][2] [127:0] $end
+     $var wire 8 O! sub5_out[0][0] [7:0] $end
+     $var wire 8 P! sub5_out[0][1] [7:0] $end
+     $var wire 8 Q! sub5_out[0][2] [7:0] $end
+     $var wire 8 R! sub5_out[1][0] [7:0] $end
+     $var wire 8 S! sub5_out[1][1] [7:0] $end
+     $var wire 8 T! sub5_out[1][2] [7:0] $end
+     $var wire 32 6! count [31:0] $end
      $var wire 32 % driven_from_bind [31:0] $end
      $scope module i_sub4_bound $end
-      $var real 64 `! P1 $end
+      $var real 64 e! P1 $end
       $var wire 32 % driven_from_bind [31:0] $end
      $upscope $end
      $scope module i_sub5 $end
-      $var wire 1 ^' clk $end
-      $var wire 128 ?' in[0][0] [127:0] $end
-      $var wire 128 C' in[0][1] [127:0] $end
-      $var wire 128 G' in[0][2] [127:0] $end
-      $var wire 128 K' in[1][0] [127:0] $end
-      $var wire 128 O' in[1][1] [127:0] $end
-      $var wire 128 S' in[1][2] [127:0] $end
-      $var wire 8 W' out[0][0] [7:0] $end
-      $var wire 8 X' out[0][1] [7:0] $end
-      $var wire 8 Y' out[0][2] [7:0] $end
-      $var wire 8 Z' out[1][0] [7:0] $end
-      $var wire 8 [' out[1][1] [7:0] $end
-      $var wire 8 \' out[1][2] [7:0] $end
-      $var wire 32 ]' count [31:0] $end
-      $var wire 8 /' val0[0] [7:0] $end
-      $var wire 8 0' val0[1] [7:0] $end
-      $var wire 8 1' val1[0] [7:0] $end
-      $var wire 8 2' val1[1] [7:0] $end
-      $var wire 8 3' val2[0] [7:0] $end
-      $var wire 8 4' val2[1] [7:0] $end
-      $var wire 8 5' val3[0] [7:0] $end
-      $var wire 8 6' val3[1] [7:0] $end
+      $var wire 1 Y' clk $end
+      $var wire 128 A' in[0][0] [127:0] $end
+      $var wire 128 E' in[0][1] [127:0] $end
+      $var wire 128 I' in[0][2] [127:0] $end
+      $var wire 128 M' in[1][0] [127:0] $end
+      $var wire 128 Q' in[1][1] [127:0] $end
+      $var wire 128 U' in[1][2] [127:0] $end
+      $var wire 8 Z' out[0][0] [7:0] $end
+      $var wire 8 [' out[0][1] [7:0] $end
+      $var wire 8 \' out[0][2] [7:0] $end
+      $var wire 8 ]' out[1][0] [7:0] $end
+      $var wire 8 ^' out[1][1] [7:0] $end
+      $var wire 8 _' out[1][2] [7:0] $end
+      $var wire 32 `' count [31:0] $end
+      $var wire 8 1' val0[0] [7:0] $end
+      $var wire 8 2' val0[1] [7:0] $end
+      $var wire 8 3' val1[0] [7:0] $end
+      $var wire 8 4' val1[1] [7:0] $end
+      $var wire 8 5' val2[0] [7:0] $end
+      $var wire 8 6' val2[1] [7:0] $end
+      $var wire 8 7' val3[0] [7:0] $end
+      $var wire 8 8' val3[1] [7:0] $end
       $scope module i_sub0 $end
-       $var wire 32 _' P0 [31:0] $end
-       $var wire 32 `' P1 [31:0] $end
-       $var wire 8 7' out[0] [7:0] $end
-       $var wire 8 8' out[1] [7:0] $end
-      $upscope $end
-      $scope module i_sub1 $end
-       $var wire 32 _' P0 [31:0] $end
-       $var wire 32 `' P1 [31:0] $end
+       $var wire 32 a' P0 [31:0] $end
+       $var wire 32 b' P1 [31:0] $end
        $var wire 8 9' out[0] [7:0] $end
        $var wire 8 :' out[1] [7:0] $end
       $upscope $end
-      $scope module i_sub2 $end
-       $var wire 32 _' P0 [31:0] $end
-       $var wire 32 `' P1 [31:0] $end
+      $scope module i_sub1 $end
+       $var wire 32 a' P0 [31:0] $end
+       $var wire 32 b' P1 [31:0] $end
        $var wire 8 ;' out[0] [7:0] $end
        $var wire 8 <' out[1] [7:0] $end
       $upscope $end
-      $scope module i_sub3 $end
-       $var wire 32 _' P0 [31:0] $end
-       $var wire 32 a' P1 [31:0] $end
+      $scope module i_sub2 $end
+       $var wire 32 a' P0 [31:0] $end
+       $var wire 32 b' P1 [31:0] $end
        $var wire 8 =' out[0] [7:0] $end
        $var wire 8 >' out[1] [7:0] $end
       $upscope $end
+      $scope module i_sub3 $end
+       $var wire 32 a' P0 [31:0] $end
+       $var wire 32 c' P1 [31:0] $end
+       $var wire 8 ?' out[0] [7:0] $end
+       $var wire 8 @' out[1] [7:0] $end
+      $upscope $end
      $upscope $end
     $upscope $end
    $upscope $end
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diff --git a/test_regress/t/t_trace_hier_block_default_sc_fst.out b/test_regress/t/t_trace_hier_block_default_sc_fst.out
index 6ad6a50e4..bfd9b153d 100644
--- a/test_regress/t/t_trace_hier_block_default_sc_fst.out
+++ b/test_regress/t/t_trace_hier_block_default_sc_fst.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 14 09:16:54 2026
+Tue Apr 14 17:15:24 2026
 
 $end
 $version
@@ -125,44 +125,44 @@ $end
        $var real_parameter 64 L P1 $end
        $var real_parameter 64 M P3 $end
        $var wire 1 = clk $end
-       $var wire 8 I in [7:0] $end
+       $var wire 8 N in [7:0] $end
        $var wire 8 B out [7:0] $end
        $var logic 8 B ff [7:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array sub5_in $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [0] $end
-         $var logic 128 N sub5_in[0][0] [127:0] $end
-         $var logic 128 O sub5_in[0][1] [127:0] $end
-         $var logic 128 P sub5_in[0][2] [127:0] $end
+         $var logic 128 O sub5_in[0][0] [127:0] $end
+         $var logic 128 P sub5_in[0][1] [127:0] $end
+         $var logic 128 Q sub5_in[0][2] [127:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [1] $end
-         $var logic 128 Q sub5_in[1][0] [127:0] $end
-         $var logic 128 R sub5_in[1][1] [127:0] $end
-         $var logic 128 S sub5_in[1][2] [127:0] $end
+         $var logic 128 R sub5_in[1][0] [127:0] $end
+         $var logic 128 S sub5_in[1][1] [127:0] $end
+         $var logic 128 T sub5_in[1][2] [127:0] $end
         $upscope $end
        $upscope $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array sub5_out $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [0] $end
-         $var wire 8 T sub5_out[0][0] [7:0] $end
-         $var wire 8 U sub5_out[0][1] [7:0] $end
-         $var wire 8 V sub5_out[0][2] [7:0] $end
+         $var wire 8 U sub5_out[0][0] [7:0] $end
+         $var wire 8 V sub5_out[0][1] [7:0] $end
+         $var wire 8 W sub5_out[0][2] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [1] $end
-         $var wire 8 W sub5_out[1][0] [7:0] $end
-         $var wire 8 X sub5_out[1][1] [7:0] $end
-         $var wire 8 Y sub5_out[1][2] [7:0] $end
+         $var wire 8 X sub5_out[1][0] [7:0] $end
+         $var wire 8 Y sub5_out[1][1] [7:0] $end
+         $var wire 8 Z sub5_out[1][2] [7:0] $end
         $upscope $end
        $upscope $end
-       $var int 32 Z count [31:0] $end
-       $var int 32 [ driven_from_bind [31:0] $end
+       $var int 32 [ count [31:0] $end
+       $var int 32 \ driven_from_bind [31:0] $end
        $scope module i_sub4_bound $end
         $var real_parameter 64 L P1 $end
-        $var wire 32 [ driven_from_bind [31:0] $end
+        $var wire 32 \ driven_from_bind [31:0] $end
        $upscope $end
        $scope module i_sub5 $end
         $var wire 1 = clk $end
@@ -170,87 +170,87 @@ $end
         $scope sv_array in $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [0] $end
-          $var wire 128 \ in[0][0] [127:0] $end
-          $var wire 128 ] in[0][1] [127:0] $end
-          $var wire 128 ^ in[0][2] [127:0] $end
+          $var wire 128 ] in[0][0] [127:0] $end
+          $var wire 128 ^ in[0][1] [127:0] $end
+          $var wire 128 _ in[0][2] [127:0] $end
          $upscope $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [1] $end
-          $var wire 128 _ in[1][0] [127:0] $end
-          $var wire 128 ` in[1][1] [127:0] $end
-          $var wire 128 a in[1][2] [127:0] $end
+          $var wire 128 ` in[1][0] [127:0] $end
+          $var wire 128 a in[1][1] [127:0] $end
+          $var wire 128 b in[1][2] [127:0] $end
          $upscope $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array out $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [0] $end
-          $var wire 8 b out[0][0] [7:0] $end
-          $var wire 8 c out[0][1] [7:0] $end
-          $var wire 8 d out[0][2] [7:0] $end
+          $var wire 8 c out[0][0] [7:0] $end
+          $var wire 8 d out[0][1] [7:0] $end
+          $var wire 8 e out[0][2] [7:0] $end
          $upscope $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [1] $end
-          $var wire 8 e out[1][0] [7:0] $end
-          $var wire 8 f out[1][1] [7:0] $end
-          $var wire 8 g out[1][2] [7:0] $end
+          $var wire 8 f out[1][0] [7:0] $end
+          $var wire 8 g out[1][1] [7:0] $end
+          $var wire 8 h out[1][2] [7:0] $end
          $upscope $end
         $upscope $end
-        $var int 32 h count [31:0] $end
+        $var int 32 i count [31:0] $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val0 $end
-         $var wire 8 i val0[0] [7:0] $end
-         $var wire 8 j val0[1] [7:0] $end
+         $var wire 8 j val0[0] [7:0] $end
+         $var wire 8 k val0[1] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val1 $end
-         $var wire 8 k val1[0] [7:0] $end
-         $var wire 8 l val1[1] [7:0] $end
+         $var wire 8 l val1[0] [7:0] $end
+         $var wire 8 m val1[1] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val2 $end
-         $var wire 8 m val2[0] [7:0] $end
-         $var wire 8 n val2[1] [7:0] $end
+         $var wire 8 n val2[0] [7:0] $end
+         $var wire 8 o val2[1] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val3 $end
-         $var wire 8 o val3[0] [7:0] $end
-         $var wire 8 p val3[1] [7:0] $end
+         $var wire 8 p val3[0] [7:0] $end
+         $var wire 8 q val3[1] [7:0] $end
         $upscope $end
         $scope module i_sub0 $end
-         $var parameter 32 q P0 [31:0] $end
-         $var parameter 32 r P1 [31:0] $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 s P1 [31:0] $end
          $attrbegin array unpacked bounds 1 $end
          $scope sv_array out $end
-          $var wire 8 s out[0] [7:0] $end
-          $var wire 8 t out[1] [7:0] $end
+          $var wire 8 t out[0] [7:0] $end
+          $var wire 8 u out[1] [7:0] $end
          $upscope $end
         $upscope $end
         $scope module i_sub1 $end
-         $var parameter 32 q P0 [31:0] $end
-         $var parameter 32 r P1 [31:0] $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 s P1 [31:0] $end
          $attrbegin array unpacked bounds 1 $end
          $scope sv_array out $end
-          $var wire 8 u out[0] [7:0] $end
-          $var wire 8 v out[1] [7:0] $end
+          $var wire 8 v out[0] [7:0] $end
+          $var wire 8 w out[1] [7:0] $end
          $upscope $end
         $upscope $end
         $scope module i_sub2 $end
-         $var parameter 32 q P0 [31:0] $end
-         $var parameter 32 r P1 [31:0] $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 s P1 [31:0] $end
          $attrbegin array unpacked bounds 1 $end
          $scope sv_array out $end
-          $var wire 8 w out[0] [7:0] $end
-          $var wire 8 x out[1] [7:0] $end
+          $var wire 8 x out[0] [7:0] $end
+          $var wire 8 y out[1] [7:0] $end
          $upscope $end
         $upscope $end
         $scope module i_sub3 $end
-         $var parameter 32 q P0 [31:0] $end
-         $var parameter 32 y P1 [31:0] $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 z P1 [31:0] $end
          $attrbegin array unpacked bounds 1 $end
          $scope sv_array out $end
-          $var wire 8 z out[0] [7:0] $end
-          $var wire 8 { out[1] [7:0] $end
+          $var wire 8 { out[0] [7:0] $end
+          $var wire 8 | out[1] [7:0] $end
          $upscope $end
         $upscope $end
        $upscope $end
@@ -258,46 +258,46 @@ $end
       $scope module i_sub4_1 $end
        $var parameter 32 K P0 [31:0] $end
        $var real_parameter 64 L P1 $end
-       $var real_parameter 64 | P3 $end
+       $var real_parameter 64 } P3 $end
        $var wire 1 = clk $end
-       $var wire 8 I in [7:0] $end
+       $var wire 8 N in [7:0] $end
        $var wire 8 J out [7:0] $end
        $var logic 8 J ff [7:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array sub5_in $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [0] $end
-         $var logic 128 } sub5_in[0][0] [127:0] $end
-         $var logic 128 ~ sub5_in[0][1] [127:0] $end
-         $var logic 128 !! sub5_in[0][2] [127:0] $end
+         $var logic 128 ~ sub5_in[0][0] [127:0] $end
+         $var logic 128 !! sub5_in[0][1] [127:0] $end
+         $var logic 128 "! sub5_in[0][2] [127:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [1] $end
-         $var logic 128 "! sub5_in[1][0] [127:0] $end
-         $var logic 128 #! sub5_in[1][1] [127:0] $end
-         $var logic 128 $! sub5_in[1][2] [127:0] $end
+         $var logic 128 #! sub5_in[1][0] [127:0] $end
+         $var logic 128 $! sub5_in[1][1] [127:0] $end
+         $var logic 128 %! sub5_in[1][2] [127:0] $end
         $upscope $end
        $upscope $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array sub5_out $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [0] $end
-         $var wire 8 %! sub5_out[0][0] [7:0] $end
-         $var wire 8 &! sub5_out[0][1] [7:0] $end
-         $var wire 8 '! sub5_out[0][2] [7:0] $end
+         $var wire 8 &! sub5_out[0][0] [7:0] $end
+         $var wire 8 '! sub5_out[0][1] [7:0] $end
+         $var wire 8 (! sub5_out[0][2] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [1] $end
-         $var wire 8 (! sub5_out[1][0] [7:0] $end
-         $var wire 8 )! sub5_out[1][1] [7:0] $end
-         $var wire 8 *! sub5_out[1][2] [7:0] $end
+         $var wire 8 )! sub5_out[1][0] [7:0] $end
+         $var wire 8 *! sub5_out[1][1] [7:0] $end
+         $var wire 8 +! sub5_out[1][2] [7:0] $end
         $upscope $end
        $upscope $end
-       $var int 32 +! count [31:0] $end
-       $var int 32 ,! driven_from_bind [31:0] $end
+       $var int 32 ,! count [31:0] $end
+       $var int 32 -! driven_from_bind [31:0] $end
        $scope module i_sub4_bound $end
         $var real_parameter 64 L P1 $end
-        $var wire 32 ,! driven_from_bind [31:0] $end
+        $var wire 32 -! driven_from_bind [31:0] $end
        $upscope $end
        $scope module i_sub5 $end
         $var wire 1 = clk $end
@@ -305,87 +305,87 @@ $end
         $scope sv_array in $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [0] $end
-          $var wire 128 -! in[0][0] [127:0] $end
-          $var wire 128 .! in[0][1] [127:0] $end
-          $var wire 128 /! in[0][2] [127:0] $end
+          $var wire 128 .! in[0][0] [127:0] $end
+          $var wire 128 /! in[0][1] [127:0] $end
+          $var wire 128 0! in[0][2] [127:0] $end
          $upscope $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [1] $end
-          $var wire 128 0! in[1][0] [127:0] $end
-          $var wire 128 1! in[1][1] [127:0] $end
-          $var wire 128 2! in[1][2] [127:0] $end
+          $var wire 128 1! in[1][0] [127:0] $end
+          $var wire 128 2! in[1][1] [127:0] $end
+          $var wire 128 3! in[1][2] [127:0] $end
          $upscope $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array out $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [0] $end
-          $var wire 8 3! out[0][0] [7:0] $end
-          $var wire 8 4! out[0][1] [7:0] $end
-          $var wire 8 5! out[0][2] [7:0] $end
+          $var wire 8 4! out[0][0] [7:0] $end
+          $var wire 8 5! out[0][1] [7:0] $end
+          $var wire 8 6! out[0][2] [7:0] $end
          $upscope $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [1] $end
-          $var wire 8 6! out[1][0] [7:0] $end
-          $var wire 8 7! out[1][1] [7:0] $end
-          $var wire 8 8! out[1][2] [7:0] $end
+          $var wire 8 7! out[1][0] [7:0] $end
+          $var wire 8 8! out[1][1] [7:0] $end
+          $var wire 8 9! out[1][2] [7:0] $end
          $upscope $end
         $upscope $end
-        $var int 32 9! count [31:0] $end
+        $var int 32 :! count [31:0] $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val0 $end
-         $var wire 8 :! val0[0] [7:0] $end
-         $var wire 8 ;! val0[1] [7:0] $end
+         $var wire 8 ;! val0[0] [7:0] $end
+         $var wire 8 <! val0[1] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val1 $end
-         $var wire 8 <! val1[0] [7:0] $end
-         $var wire 8 =! val1[1] [7:0] $end
+         $var wire 8 =! val1[0] [7:0] $end
+         $var wire 8 >! val1[1] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val2 $end
-         $var wire 8 >! val2[0] [7:0] $end
-         $var wire 8 ?! val2[1] [7:0] $end
+         $var wire 8 ?! val2[0] [7:0] $end
+         $var wire 8 @! val2[1] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val3 $end
-         $var wire 8 @! val3[0] [7:0] $end
-         $var wire 8 A! val3[1] [7:0] $end
+         $var wire 8 A! val3[0] [7:0] $end
+         $var wire 8 B! val3[1] [7:0] $end
         $upscope $end
         $scope module i_sub0 $end
-         $var parameter 32 q P0 [31:0] $end
-         $var parameter 32 r P1 [31:0] $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 s P1 [31:0] $end
          $attrbegin array unpacked bounds 1 $end
          $scope sv_array out $end
-          $var wire 8 B! out[0] [7:0] $end
-          $var wire 8 C! out[1] [7:0] $end
+          $var wire 8 C! out[0] [7:0] $end
+          $var wire 8 D! out[1] [7:0] $end
          $upscope $end
         $upscope $end
         $scope module i_sub1 $end
-         $var parameter 32 q P0 [31:0] $end
-         $var parameter 32 r P1 [31:0] $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 s P1 [31:0] $end
          $attrbegin array unpacked bounds 1 $end
          $scope sv_array out $end
-          $var wire 8 D! out[0] [7:0] $end
-          $var wire 8 E! out[1] [7:0] $end
+          $var wire 8 E! out[0] [7:0] $end
+          $var wire 8 F! out[1] [7:0] $end
          $upscope $end
         $upscope $end
         $scope module i_sub2 $end
-         $var parameter 32 q P0 [31:0] $end
-         $var parameter 32 r P1 [31:0] $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 s P1 [31:0] $end
          $attrbegin array unpacked bounds 1 $end
          $scope sv_array out $end
-          $var wire 8 F! out[0] [7:0] $end
-          $var wire 8 G! out[1] [7:0] $end
+          $var wire 8 G! out[0] [7:0] $end
+          $var wire 8 H! out[1] [7:0] $end
          $upscope $end
         $upscope $end
         $scope module i_sub3 $end
-         $var parameter 32 q P0 [31:0] $end
-         $var parameter 32 y P1 [31:0] $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 z P1 [31:0] $end
          $attrbegin array unpacked bounds 1 $end
          $scope sv_array out $end
-          $var wire 8 H! out[0] [7:0] $end
-          $var wire 8 I! out[1] [7:0] $end
+          $var wire 8 I! out[0] [7:0] $end
+          $var wire 8 J! out[1] [7:0] $end
          $upscope $end
         $upscope $end
        $upscope $end
@@ -395,8 +395,8 @@ $end
       $var parameter 8 D P0 [7:0] $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array UNPACKED_ARRAY $end
-       $var parameter 32 J! UNPACKED_ARRAY[0] [31:0] $end
-       $var parameter 32 K! UNPACKED_ARRAY[1] [31:0] $end
+       $var parameter 32 K! UNPACKED_ARRAY[0] [31:0] $end
+       $var parameter 32 L! UNPACKED_ARRAY[1] [31:0] $end
       $upscope $end
       $var parameter 16 G UNUSED [15:0] $end
       $attrbegin misc 07 "" 4 $end
@@ -404,52 +404,52 @@ $end
       $var wire 1 = clk $end
       $var wire 8 @ in [7:0] $end
       $var wire 8 C out [7:0] $end
-      $var logic 8 L! ff [7:0] $end
+      $var logic 8 M! ff [7:0] $end
       $var wire 8 C out4 [7:0] $end
-      $var wire 8 M! out4_2 [7:0] $end
+      $var wire 8 N! out4_2 [7:0] $end
       $scope module i_sub4_0 $end
        $var parameter 32 K P0 [31:0] $end
        $var real_parameter 64 L P1 $end
        $var real_parameter 64 M P3 $end
        $var wire 1 = clk $end
-       $var wire 8 L! in [7:0] $end
+       $var wire 8 O! in [7:0] $end
        $var wire 8 C out [7:0] $end
        $var logic 8 C ff [7:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array sub5_in $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [0] $end
-         $var logic 128 N! sub5_in[0][0] [127:0] $end
-         $var logic 128 O! sub5_in[0][1] [127:0] $end
-         $var logic 128 P! sub5_in[0][2] [127:0] $end
+         $var logic 128 P! sub5_in[0][0] [127:0] $end
+         $var logic 128 Q! sub5_in[0][1] [127:0] $end
+         $var logic 128 R! sub5_in[0][2] [127:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [1] $end
-         $var logic 128 Q! sub5_in[1][0] [127:0] $end
-         $var logic 128 R! sub5_in[1][1] [127:0] $end
-         $var logic 128 S! sub5_in[1][2] [127:0] $end
+         $var logic 128 S! sub5_in[1][0] [127:0] $end
+         $var logic 128 T! sub5_in[1][1] [127:0] $end
+         $var logic 128 U! sub5_in[1][2] [127:0] $end
         $upscope $end
        $upscope $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array sub5_out $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [0] $end
-         $var wire 8 T! sub5_out[0][0] [7:0] $end
-         $var wire 8 U! sub5_out[0][1] [7:0] $end
-         $var wire 8 V! sub5_out[0][2] [7:0] $end
+         $var wire 8 V! sub5_out[0][0] [7:0] $end
+         $var wire 8 W! sub5_out[0][1] [7:0] $end
+         $var wire 8 X! sub5_out[0][2] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [1] $end
-         $var wire 8 W! sub5_out[1][0] [7:0] $end
-         $var wire 8 X! sub5_out[1][1] [7:0] $end
-         $var wire 8 Y! sub5_out[1][2] [7:0] $end
+         $var wire 8 Y! sub5_out[1][0] [7:0] $end
+         $var wire 8 Z! sub5_out[1][1] [7:0] $end
+         $var wire 8 [! sub5_out[1][2] [7:0] $end
         $upscope $end
        $upscope $end
-       $var int 32 Z! count [31:0] $end
-       $var int 32 [! driven_from_bind [31:0] $end
+       $var int 32 \! count [31:0] $end
+       $var int 32 ]! driven_from_bind [31:0] $end
        $scope module i_sub4_bound $end
         $var real_parameter 64 L P1 $end
-        $var wire 32 [! driven_from_bind [31:0] $end
+        $var wire 32 ]! driven_from_bind [31:0] $end
        $upscope $end
        $scope module i_sub5 $end
         $var wire 1 = clk $end
@@ -457,134 +457,134 @@ $end
         $scope sv_array in $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [0] $end
-          $var wire 128 \! in[0][0] [127:0] $end
-          $var wire 128 ]! in[0][1] [127:0] $end
-          $var wire 128 ^! in[0][2] [127:0] $end
+          $var wire 128 ^! in[0][0] [127:0] $end
+          $var wire 128 _! in[0][1] [127:0] $end
+          $var wire 128 `! in[0][2] [127:0] $end
          $upscope $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [1] $end
-          $var wire 128 _! in[1][0] [127:0] $end
-          $var wire 128 `! in[1][1] [127:0] $end
-          $var wire 128 a! in[1][2] [127:0] $end
+          $var wire 128 a! in[1][0] [127:0] $end
+          $var wire 128 b! in[1][1] [127:0] $end
+          $var wire 128 c! in[1][2] [127:0] $end
          $upscope $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array out $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [0] $end
-          $var wire 8 b! out[0][0] [7:0] $end
-          $var wire 8 c! out[0][1] [7:0] $end
-          $var wire 8 d! out[0][2] [7:0] $end
+          $var wire 8 d! out[0][0] [7:0] $end
+          $var wire 8 e! out[0][1] [7:0] $end
+          $var wire 8 f! out[0][2] [7:0] $end
          $upscope $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [1] $end
-          $var wire 8 e! out[1][0] [7:0] $end
-          $var wire 8 f! out[1][1] [7:0] $end
-          $var wire 8 g! out[1][2] [7:0] $end
+          $var wire 8 g! out[1][0] [7:0] $end
+          $var wire 8 h! out[1][1] [7:0] $end
+          $var wire 8 i! out[1][2] [7:0] $end
          $upscope $end
         $upscope $end
-        $var int 32 h! count [31:0] $end
+        $var int 32 j! count [31:0] $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val0 $end
-         $var wire 8 i! val0[0] [7:0] $end
-         $var wire 8 j! val0[1] [7:0] $end
+         $var wire 8 k! val0[0] [7:0] $end
+         $var wire 8 l! val0[1] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val1 $end
-         $var wire 8 k! val1[0] [7:0] $end
-         $var wire 8 l! val1[1] [7:0] $end
+         $var wire 8 m! val1[0] [7:0] $end
+         $var wire 8 n! val1[1] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val2 $end
-         $var wire 8 m! val2[0] [7:0] $end
-         $var wire 8 n! val2[1] [7:0] $end
+         $var wire 8 o! val2[0] [7:0] $end
+         $var wire 8 p! val2[1] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val3 $end
-         $var wire 8 o! val3[0] [7:0] $end
-         $var wire 8 p! val3[1] [7:0] $end
+         $var wire 8 q! val3[0] [7:0] $end
+         $var wire 8 r! val3[1] [7:0] $end
         $upscope $end
         $scope module i_sub0 $end
-         $var parameter 32 q P0 [31:0] $end
-         $var parameter 32 r P1 [31:0] $end
-         $attrbegin array unpacked bounds 1 $end
-         $scope sv_array out $end
-          $var wire 8 q! out[0] [7:0] $end
-          $var wire 8 r! out[1] [7:0] $end
-         $upscope $end
-        $upscope $end
-        $scope module i_sub1 $end
-         $var parameter 32 q P0 [31:0] $end
-         $var parameter 32 r P1 [31:0] $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 s P1 [31:0] $end
          $attrbegin array unpacked bounds 1 $end
          $scope sv_array out $end
           $var wire 8 s! out[0] [7:0] $end
           $var wire 8 t! out[1] [7:0] $end
          $upscope $end
         $upscope $end
-        $scope module i_sub2 $end
-         $var parameter 32 q P0 [31:0] $end
-         $var parameter 32 r P1 [31:0] $end
+        $scope module i_sub1 $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 s P1 [31:0] $end
          $attrbegin array unpacked bounds 1 $end
          $scope sv_array out $end
           $var wire 8 u! out[0] [7:0] $end
           $var wire 8 v! out[1] [7:0] $end
          $upscope $end
         $upscope $end
-        $scope module i_sub3 $end
-         $var parameter 32 q P0 [31:0] $end
-         $var parameter 32 y P1 [31:0] $end
+        $scope module i_sub2 $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 s P1 [31:0] $end
          $attrbegin array unpacked bounds 1 $end
          $scope sv_array out $end
           $var wire 8 w! out[0] [7:0] $end
           $var wire 8 x! out[1] [7:0] $end
          $upscope $end
         $upscope $end
+        $scope module i_sub3 $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 z P1 [31:0] $end
+         $attrbegin array unpacked bounds 1 $end
+         $scope sv_array out $end
+          $var wire 8 y! out[0] [7:0] $end
+          $var wire 8 z! out[1] [7:0] $end
+         $upscope $end
+        $upscope $end
        $upscope $end
       $upscope $end
       $scope module i_sub4_1 $end
        $var parameter 32 K P0 [31:0] $end
        $var real_parameter 64 L P1 $end
-       $var real_parameter 64 | P3 $end
+       $var real_parameter 64 } P3 $end
        $var wire 1 = clk $end
-       $var wire 8 L! in [7:0] $end
-       $var wire 8 M! out [7:0] $end
-       $var logic 8 M! ff [7:0] $end
+       $var wire 8 O! in [7:0] $end
+       $var wire 8 N! out [7:0] $end
+       $var logic 8 N! ff [7:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array sub5_in $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [0] $end
-         $var logic 128 y! sub5_in[0][0] [127:0] $end
-         $var logic 128 z! sub5_in[0][1] [127:0] $end
-         $var logic 128 {! sub5_in[0][2] [127:0] $end
+         $var logic 128 {! sub5_in[0][0] [127:0] $end
+         $var logic 128 |! sub5_in[0][1] [127:0] $end
+         $var logic 128 }! sub5_in[0][2] [127:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [1] $end
-         $var logic 128 |! sub5_in[1][0] [127:0] $end
-         $var logic 128 }! sub5_in[1][1] [127:0] $end
-         $var logic 128 ~! sub5_in[1][2] [127:0] $end
+         $var logic 128 ~! sub5_in[1][0] [127:0] $end
+         $var logic 128 !" sub5_in[1][1] [127:0] $end
+         $var logic 128 "" sub5_in[1][2] [127:0] $end
         $upscope $end
        $upscope $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array sub5_out $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [0] $end
-         $var wire 8 !" sub5_out[0][0] [7:0] $end
-         $var wire 8 "" sub5_out[0][1] [7:0] $end
-         $var wire 8 #" sub5_out[0][2] [7:0] $end
+         $var wire 8 #" sub5_out[0][0] [7:0] $end
+         $var wire 8 $" sub5_out[0][1] [7:0] $end
+         $var wire 8 %" sub5_out[0][2] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [1] $end
-         $var wire 8 $" sub5_out[1][0] [7:0] $end
-         $var wire 8 %" sub5_out[1][1] [7:0] $end
-         $var wire 8 &" sub5_out[1][2] [7:0] $end
+         $var wire 8 &" sub5_out[1][0] [7:0] $end
+         $var wire 8 '" sub5_out[1][1] [7:0] $end
+         $var wire 8 (" sub5_out[1][2] [7:0] $end
         $upscope $end
        $upscope $end
-       $var int 32 '" count [31:0] $end
-       $var int 32 (" driven_from_bind [31:0] $end
+       $var int 32 )" count [31:0] $end
+       $var int 32 *" driven_from_bind [31:0] $end
        $scope module i_sub4_bound $end
         $var real_parameter 64 L P1 $end
-        $var wire 32 (" driven_from_bind [31:0] $end
+        $var wire 32 *" driven_from_bind [31:0] $end
        $upscope $end
        $scope module i_sub5 $end
         $var wire 1 = clk $end
@@ -592,89 +592,89 @@ $end
         $scope sv_array in $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [0] $end
-          $var wire 128 )" in[0][0] [127:0] $end
-          $var wire 128 *" in[0][1] [127:0] $end
-          $var wire 128 +" in[0][2] [127:0] $end
+          $var wire 128 +" in[0][0] [127:0] $end
+          $var wire 128 ," in[0][1] [127:0] $end
+          $var wire 128 -" in[0][2] [127:0] $end
          $upscope $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [1] $end
-          $var wire 128 ," in[1][0] [127:0] $end
-          $var wire 128 -" in[1][1] [127:0] $end
-          $var wire 128 ." in[1][2] [127:0] $end
+          $var wire 128 ." in[1][0] [127:0] $end
+          $var wire 128 /" in[1][1] [127:0] $end
+          $var wire 128 0" in[1][2] [127:0] $end
          $upscope $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array out $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [0] $end
-          $var wire 8 /" out[0][0] [7:0] $end
-          $var wire 8 0" out[0][1] [7:0] $end
-          $var wire 8 1" out[0][2] [7:0] $end
+          $var wire 8 1" out[0][0] [7:0] $end
+          $var wire 8 2" out[0][1] [7:0] $end
+          $var wire 8 3" out[0][2] [7:0] $end
          $upscope $end
          $attrbegin array unpacked bounds 2 $end
          $scope sv_array [1] $end
-          $var wire 8 2" out[1][0] [7:0] $end
-          $var wire 8 3" out[1][1] [7:0] $end
-          $var wire 8 4" out[1][2] [7:0] $end
+          $var wire 8 4" out[1][0] [7:0] $end
+          $var wire 8 5" out[1][1] [7:0] $end
+          $var wire 8 6" out[1][2] [7:0] $end
          $upscope $end
         $upscope $end
-        $var int 32 5" count [31:0] $end
+        $var int 32 7" count [31:0] $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val0 $end
-         $var wire 8 6" val0[0] [7:0] $end
-         $var wire 8 7" val0[1] [7:0] $end
+         $var wire 8 8" val0[0] [7:0] $end
+         $var wire 8 9" val0[1] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val1 $end
-         $var wire 8 8" val1[0] [7:0] $end
-         $var wire 8 9" val1[1] [7:0] $end
+         $var wire 8 :" val1[0] [7:0] $end
+         $var wire 8 ;" val1[1] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val2 $end
-         $var wire 8 :" val2[0] [7:0] $end
-         $var wire 8 ;" val2[1] [7:0] $end
+         $var wire 8 <" val2[0] [7:0] $end
+         $var wire 8 =" val2[1] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array val3 $end
-         $var wire 8 <" val3[0] [7:0] $end
-         $var wire 8 =" val3[1] [7:0] $end
+         $var wire 8 >" val3[0] [7:0] $end
+         $var wire 8 ?" val3[1] [7:0] $end
         $upscope $end
         $scope module i_sub0 $end
-         $var parameter 32 q P0 [31:0] $end
-         $var parameter 32 r P1 [31:0] $end
-         $attrbegin array unpacked bounds 1 $end
-         $scope sv_array out $end
-          $var wire 8 >" out[0] [7:0] $end
-          $var wire 8 ?" out[1] [7:0] $end
-         $upscope $end
-        $upscope $end
-        $scope module i_sub1 $end
-         $var parameter 32 q P0 [31:0] $end
-         $var parameter 32 r P1 [31:0] $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 s P1 [31:0] $end
          $attrbegin array unpacked bounds 1 $end
          $scope sv_array out $end
           $var wire 8 @" out[0] [7:0] $end
           $var wire 8 A" out[1] [7:0] $end
          $upscope $end
         $upscope $end
-        $scope module i_sub2 $end
-         $var parameter 32 q P0 [31:0] $end
-         $var parameter 32 r P1 [31:0] $end
+        $scope module i_sub1 $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 s P1 [31:0] $end
          $attrbegin array unpacked bounds 1 $end
          $scope sv_array out $end
           $var wire 8 B" out[0] [7:0] $end
           $var wire 8 C" out[1] [7:0] $end
          $upscope $end
         $upscope $end
-        $scope module i_sub3 $end
-         $var parameter 32 q P0 [31:0] $end
-         $var parameter 32 y P1 [31:0] $end
+        $scope module i_sub2 $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 s P1 [31:0] $end
          $attrbegin array unpacked bounds 1 $end
          $scope sv_array out $end
           $var wire 8 D" out[0] [7:0] $end
           $var wire 8 E" out[1] [7:0] $end
          $upscope $end
         $upscope $end
+        $scope module i_sub3 $end
+         $var parameter 32 r P0 [31:0] $end
+         $var parameter 32 z P1 [31:0] $end
+         $attrbegin array unpacked bounds 1 $end
+         $scope sv_array out $end
+          $var wire 8 F" out[0] [7:0] $end
+          $var wire 8 G" out[1] [7:0] $end
+         $upscope $end
+        $upscope $end
        $upscope $end
       $upscope $end
      $upscope $end
@@ -697,574 +697,574 @@ $end
     $upscope $end
    $upscope $end
    $scope module i_sub3 $end
-    $var parameter 8 F" P0 [7:0] $end
+    $var parameter 8 H" P0 [7:0] $end
     $attrbegin array unpacked bounds 1 $end
     $scope sv_array UNPACKED_ARRAY $end
-     $var parameter 32 G" UNPACKED_ARRAY[0] [31:0] $end
-     $var parameter 32 H" UNPACKED_ARRAY[1] [31:0] $end
+     $var parameter 32 I" UNPACKED_ARRAY[0] [31:0] $end
+     $var parameter 32 J" UNPACKED_ARRAY[1] [31:0] $end
     $upscope $end
-    $var parameter 16 I" UNUSED [15:0] $end
+    $var parameter 16 K" UNUSED [15:0] $end
     $attrbegin misc 07 "" 1 $end
-    $var parameter 2 J" ENUM [1:0] $end
+    $var parameter 2 L" ENUM [1:0] $end
     $var wire 1 $ clk $end
     $var wire 8 ' in [7:0] $end
     $var wire 8 ( out [7:0] $end
-    $var logic 8 K" ff [7:0] $end
+    $var logic 8 M" ff [7:0] $end
     $var wire 8 ( out4 [7:0] $end
-    $var wire 8 L" out4_2 [7:0] $end
+    $var wire 8 N" out4_2 [7:0] $end
     $scope module i_sub4_0 $end
-     $var parameter 32 M" P0 [31:0] $end
-     $var real_parameter 64 N" P1 $end
-     $var real_parameter 64 O" P3 $end
+     $var parameter 32 O" P0 [31:0] $end
+     $var real_parameter 64 P" P1 $end
+     $var real_parameter 64 Q" P3 $end
      $var wire 1 $ clk $end
-     $var wire 8 K" in [7:0] $end
+     $var wire 8 R" in [7:0] $end
      $var wire 8 ( out [7:0] $end
      $var logic 8 ( ff [7:0] $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array sub5_in $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [0] $end
-       $var logic 128 P" sub5_in[0][0] [127:0] $end
-       $var logic 128 Q" sub5_in[0][1] [127:0] $end
-       $var logic 128 R" sub5_in[0][2] [127:0] $end
+       $var logic 128 S" sub5_in[0][0] [127:0] $end
+       $var logic 128 T" sub5_in[0][1] [127:0] $end
+       $var logic 128 U" sub5_in[0][2] [127:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [1] $end
-       $var logic 128 S" sub5_in[1][0] [127:0] $end
-       $var logic 128 T" sub5_in[1][1] [127:0] $end
-       $var logic 128 U" sub5_in[1][2] [127:0] $end
+       $var logic 128 V" sub5_in[1][0] [127:0] $end
+       $var logic 128 W" sub5_in[1][1] [127:0] $end
+       $var logic 128 X" sub5_in[1][2] [127:0] $end
       $upscope $end
      $upscope $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array sub5_out $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [0] $end
-       $var wire 8 V" sub5_out[0][0] [7:0] $end
-       $var wire 8 W" sub5_out[0][1] [7:0] $end
-       $var wire 8 X" sub5_out[0][2] [7:0] $end
+       $var wire 8 Y" sub5_out[0][0] [7:0] $end
+       $var wire 8 Z" sub5_out[0][1] [7:0] $end
+       $var wire 8 [" sub5_out[0][2] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [1] $end
-       $var wire 8 Y" sub5_out[1][0] [7:0] $end
-       $var wire 8 Z" sub5_out[1][1] [7:0] $end
-       $var wire 8 [" sub5_out[1][2] [7:0] $end
+       $var wire 8 \" sub5_out[1][0] [7:0] $end
+       $var wire 8 ]" sub5_out[1][1] [7:0] $end
+       $var wire 8 ^" sub5_out[1][2] [7:0] $end
       $upscope $end
      $upscope $end
-     $var int 32 \" count [31:0] $end
-     $var int 32 ]" driven_from_bind [31:0] $end
+     $var int 32 _" count [31:0] $end
+     $var int 32 `" driven_from_bind [31:0] $end
      $scope module i_sub4_bound $end
-      $var real_parameter 64 N" P1 $end
-      $var wire 32 ]" driven_from_bind [31:0] $end
+      $var real_parameter 64 P" P1 $end
+      $var wire 32 `" driven_from_bind [31:0] $end
      $upscope $end
      $scope module i_sub5 $end
-      $var wire 1 ^" clk $end
+      $var wire 1 a" clk $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array in $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [0] $end
-        $var wire 128 _" in[0][0] [127:0] $end
-        $var wire 128 `" in[0][1] [127:0] $end
-        $var wire 128 a" in[0][2] [127:0] $end
+        $var wire 128 b" in[0][0] [127:0] $end
+        $var wire 128 c" in[0][1] [127:0] $end
+        $var wire 128 d" in[0][2] [127:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [1] $end
-        $var wire 128 b" in[1][0] [127:0] $end
-        $var wire 128 c" in[1][1] [127:0] $end
-        $var wire 128 d" in[1][2] [127:0] $end
+        $var wire 128 e" in[1][0] [127:0] $end
+        $var wire 128 f" in[1][1] [127:0] $end
+        $var wire 128 g" in[1][2] [127:0] $end
        $upscope $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array out $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [0] $end
-        $var wire 8 e" out[0][0] [7:0] $end
-        $var wire 8 f" out[0][1] [7:0] $end
-        $var wire 8 g" out[0][2] [7:0] $end
+        $var wire 8 h" out[0][0] [7:0] $end
+        $var wire 8 i" out[0][1] [7:0] $end
+        $var wire 8 j" out[0][2] [7:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [1] $end
-        $var wire 8 h" out[1][0] [7:0] $end
-        $var wire 8 i" out[1][1] [7:0] $end
-        $var wire 8 j" out[1][2] [7:0] $end
+        $var wire 8 k" out[1][0] [7:0] $end
+        $var wire 8 l" out[1][1] [7:0] $end
+        $var wire 8 m" out[1][2] [7:0] $end
        $upscope $end
       $upscope $end
-      $var int 32 k" count [31:0] $end
+      $var int 32 n" count [31:0] $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array val0 $end
-       $var wire 8 l" val0[0] [7:0] $end
-       $var wire 8 m" val0[1] [7:0] $end
+       $var wire 8 o" val0[0] [7:0] $end
+       $var wire 8 p" val0[1] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array val1 $end
-       $var wire 8 n" val1[0] [7:0] $end
-       $var wire 8 o" val1[1] [7:0] $end
+       $var wire 8 q" val1[0] [7:0] $end
+       $var wire 8 r" val1[1] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array val2 $end
-       $var wire 8 p" val2[0] [7:0] $end
-       $var wire 8 q" val2[1] [7:0] $end
+       $var wire 8 s" val2[0] [7:0] $end
+       $var wire 8 t" val2[1] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array val3 $end
-       $var wire 8 r" val3[0] [7:0] $end
-       $var wire 8 s" val3[1] [7:0] $end
+       $var wire 8 u" val3[0] [7:0] $end
+       $var wire 8 v" val3[1] [7:0] $end
       $upscope $end
       $scope module i_sub0 $end
-       $var parameter 32 t" P0 [31:0] $end
-       $var parameter 32 u" P1 [31:0] $end
+       $var parameter 32 w" P0 [31:0] $end
+       $var parameter 32 x" P1 [31:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array out $end
-        $var wire 8 v" out[0] [7:0] $end
-        $var wire 8 w" out[1] [7:0] $end
+        $var wire 8 y" out[0] [7:0] $end
+        $var wire 8 z" out[1] [7:0] $end
        $upscope $end
       $upscope $end
       $scope module i_sub1 $end
-       $var parameter 32 t" P0 [31:0] $end
-       $var parameter 32 u" P1 [31:0] $end
+       $var parameter 32 w" P0 [31:0] $end
+       $var parameter 32 x" P1 [31:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array out $end
-        $var wire 8 x" out[0] [7:0] $end
-        $var wire 8 y" out[1] [7:0] $end
+        $var wire 8 {" out[0] [7:0] $end
+        $var wire 8 |" out[1] [7:0] $end
        $upscope $end
       $upscope $end
       $scope module i_sub2 $end
-       $var parameter 32 t" P0 [31:0] $end
-       $var parameter 32 u" P1 [31:0] $end
-       $attrbegin array unpacked bounds 1 $end
-       $scope sv_array out $end
-        $var wire 8 z" out[0] [7:0] $end
-        $var wire 8 {" out[1] [7:0] $end
-       $upscope $end
-      $upscope $end
-      $scope module i_sub3 $end
-       $var parameter 32 t" P0 [31:0] $end
-       $var parameter 32 |" P1 [31:0] $end
+       $var parameter 32 w" P0 [31:0] $end
+       $var parameter 32 x" P1 [31:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array out $end
         $var wire 8 }" out[0] [7:0] $end
         $var wire 8 ~" out[1] [7:0] $end
        $upscope $end
       $upscope $end
+      $scope module i_sub3 $end
+       $var parameter 32 w" P0 [31:0] $end
+       $var parameter 32 !# P1 [31:0] $end
+       $attrbegin array unpacked bounds 1 $end
+       $scope sv_array out $end
+        $var wire 8 "# out[0] [7:0] $end
+        $var wire 8 ## out[1] [7:0] $end
+       $upscope $end
+      $upscope $end
      $upscope $end
     $upscope $end
     $scope module i_sub4_1 $end
-     $var parameter 32 M" P0 [31:0] $end
-     $var real_parameter 64 N" P1 $end
-     $var real_parameter 64 !# P3 $end
+     $var parameter 32 O" P0 [31:0] $end
+     $var real_parameter 64 P" P1 $end
+     $var real_parameter 64 $# P3 $end
      $var wire 1 $ clk $end
-     $var wire 8 K" in [7:0] $end
-     $var wire 8 L" out [7:0] $end
-     $var logic 8 L" ff [7:0] $end
+     $var wire 8 R" in [7:0] $end
+     $var wire 8 N" out [7:0] $end
+     $var logic 8 N" ff [7:0] $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array sub5_in $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [0] $end
-       $var logic 128 "# sub5_in[0][0] [127:0] $end
-       $var logic 128 ## sub5_in[0][1] [127:0] $end
-       $var logic 128 $# sub5_in[0][2] [127:0] $end
+       $var logic 128 %# sub5_in[0][0] [127:0] $end
+       $var logic 128 &# sub5_in[0][1] [127:0] $end
+       $var logic 128 '# sub5_in[0][2] [127:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [1] $end
-       $var logic 128 %# sub5_in[1][0] [127:0] $end
-       $var logic 128 &# sub5_in[1][1] [127:0] $end
-       $var logic 128 '# sub5_in[1][2] [127:0] $end
+       $var logic 128 (# sub5_in[1][0] [127:0] $end
+       $var logic 128 )# sub5_in[1][1] [127:0] $end
+       $var logic 128 *# sub5_in[1][2] [127:0] $end
       $upscope $end
      $upscope $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array sub5_out $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [0] $end
-       $var wire 8 (# sub5_out[0][0] [7:0] $end
-       $var wire 8 )# sub5_out[0][1] [7:0] $end
-       $var wire 8 *# sub5_out[0][2] [7:0] $end
+       $var wire 8 +# sub5_out[0][0] [7:0] $end
+       $var wire 8 ,# sub5_out[0][1] [7:0] $end
+       $var wire 8 -# sub5_out[0][2] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [1] $end
-       $var wire 8 +# sub5_out[1][0] [7:0] $end
-       $var wire 8 ,# sub5_out[1][1] [7:0] $end
-       $var wire 8 -# sub5_out[1][2] [7:0] $end
+       $var wire 8 .# sub5_out[1][0] [7:0] $end
+       $var wire 8 /# sub5_out[1][1] [7:0] $end
+       $var wire 8 0# sub5_out[1][2] [7:0] $end
       $upscope $end
      $upscope $end
-     $var int 32 .# count [31:0] $end
-     $var int 32 /# driven_from_bind [31:0] $end
+     $var int 32 1# count [31:0] $end
+     $var int 32 2# driven_from_bind [31:0] $end
      $scope module i_sub4_bound $end
-      $var real_parameter 64 N" P1 $end
-      $var wire 32 /# driven_from_bind [31:0] $end
+      $var real_parameter 64 P" P1 $end
+      $var wire 32 2# driven_from_bind [31:0] $end
      $upscope $end
      $scope module i_sub5 $end
-      $var wire 1 0# clk $end
+      $var wire 1 3# clk $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array in $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [0] $end
-        $var wire 128 1# in[0][0] [127:0] $end
-        $var wire 128 2# in[0][1] [127:0] $end
-        $var wire 128 3# in[0][2] [127:0] $end
+        $var wire 128 4# in[0][0] [127:0] $end
+        $var wire 128 5# in[0][1] [127:0] $end
+        $var wire 128 6# in[0][2] [127:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [1] $end
-        $var wire 128 4# in[1][0] [127:0] $end
-        $var wire 128 5# in[1][1] [127:0] $end
-        $var wire 128 6# in[1][2] [127:0] $end
+        $var wire 128 7# in[1][0] [127:0] $end
+        $var wire 128 8# in[1][1] [127:0] $end
+        $var wire 128 9# in[1][2] [127:0] $end
        $upscope $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array out $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [0] $end
-        $var wire 8 7# out[0][0] [7:0] $end
-        $var wire 8 8# out[0][1] [7:0] $end
-        $var wire 8 9# out[0][2] [7:0] $end
+        $var wire 8 :# out[0][0] [7:0] $end
+        $var wire 8 ;# out[0][1] [7:0] $end
+        $var wire 8 <# out[0][2] [7:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [1] $end
-        $var wire 8 :# out[1][0] [7:0] $end
-        $var wire 8 ;# out[1][1] [7:0] $end
-        $var wire 8 <# out[1][2] [7:0] $end
+        $var wire 8 =# out[1][0] [7:0] $end
+        $var wire 8 ># out[1][1] [7:0] $end
+        $var wire 8 ?# out[1][2] [7:0] $end
        $upscope $end
       $upscope $end
-      $var int 32 =# count [31:0] $end
+      $var int 32 @# count [31:0] $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array val0 $end
-       $var wire 8 ># val0[0] [7:0] $end
-       $var wire 8 ?# val0[1] [7:0] $end
+       $var wire 8 A# val0[0] [7:0] $end
+       $var wire 8 B# val0[1] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array val1 $end
-       $var wire 8 @# val1[0] [7:0] $end
-       $var wire 8 A# val1[1] [7:0] $end
+       $var wire 8 C# val1[0] [7:0] $end
+       $var wire 8 D# val1[1] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array val2 $end
-       $var wire 8 B# val2[0] [7:0] $end
-       $var wire 8 C# val2[1] [7:0] $end
+       $var wire 8 E# val2[0] [7:0] $end
+       $var wire 8 F# val2[1] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array val3 $end
-       $var wire 8 D# val3[0] [7:0] $end
-       $var wire 8 E# val3[1] [7:0] $end
+       $var wire 8 G# val3[0] [7:0] $end
+       $var wire 8 H# val3[1] [7:0] $end
       $upscope $end
       $scope module i_sub0 $end
-       $var parameter 32 F# P0 [31:0] $end
-       $var parameter 32 G# P1 [31:0] $end
+       $var parameter 32 I# P0 [31:0] $end
+       $var parameter 32 J# P1 [31:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array out $end
-        $var wire 8 H# out[0] [7:0] $end
-        $var wire 8 I# out[1] [7:0] $end
+        $var wire 8 K# out[0] [7:0] $end
+        $var wire 8 L# out[1] [7:0] $end
        $upscope $end
       $upscope $end
       $scope module i_sub1 $end
-       $var parameter 32 F# P0 [31:0] $end
-       $var parameter 32 G# P1 [31:0] $end
+       $var parameter 32 I# P0 [31:0] $end
+       $var parameter 32 J# P1 [31:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array out $end
-        $var wire 8 J# out[0] [7:0] $end
-        $var wire 8 K# out[1] [7:0] $end
+        $var wire 8 M# out[0] [7:0] $end
+        $var wire 8 N# out[1] [7:0] $end
        $upscope $end
       $upscope $end
       $scope module i_sub2 $end
-       $var parameter 32 F# P0 [31:0] $end
-       $var parameter 32 G# P1 [31:0] $end
-       $attrbegin array unpacked bounds 1 $end
-       $scope sv_array out $end
-        $var wire 8 L# out[0] [7:0] $end
-        $var wire 8 M# out[1] [7:0] $end
-       $upscope $end
-      $upscope $end
-      $scope module i_sub3 $end
-       $var parameter 32 F# P0 [31:0] $end
-       $var parameter 32 N# P1 [31:0] $end
+       $var parameter 32 I# P0 [31:0] $end
+       $var parameter 32 J# P1 [31:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array out $end
         $var wire 8 O# out[0] [7:0] $end
         $var wire 8 P# out[1] [7:0] $end
        $upscope $end
       $upscope $end
+      $scope module i_sub3 $end
+       $var parameter 32 I# P0 [31:0] $end
+       $var parameter 32 Q# P1 [31:0] $end
+       $attrbegin array unpacked bounds 1 $end
+       $scope sv_array out $end
+        $var wire 8 R# out[0] [7:0] $end
+        $var wire 8 S# out[1] [7:0] $end
+       $upscope $end
+      $upscope $end
      $upscope $end
     $upscope $end
    $upscope $end
    $scope module i_sub3_2 $end
-    $var parameter 8 F" P0 [7:0] $end
+    $var parameter 8 H" P0 [7:0] $end
     $attrbegin array unpacked bounds 1 $end
     $scope sv_array UNPACKED_ARRAY $end
-     $var parameter 32 Q# UNPACKED_ARRAY[0] [31:0] $end
-     $var parameter 32 R# UNPACKED_ARRAY[1] [31:0] $end
+     $var parameter 32 T# UNPACKED_ARRAY[0] [31:0] $end
+     $var parameter 32 U# UNPACKED_ARRAY[1] [31:0] $end
     $upscope $end
-    $var parameter 16 I" UNUSED [15:0] $end
+    $var parameter 16 K" UNUSED [15:0] $end
     $attrbegin misc 07 "" 1 $end
-    $var parameter 2 J" ENUM [1:0] $end
+    $var parameter 2 L" ENUM [1:0] $end
     $var wire 1 $ clk $end
     $var wire 8 ' in [7:0] $end
     $var wire 8 ) out [7:0] $end
-    $var logic 8 S# ff [7:0] $end
+    $var logic 8 V# ff [7:0] $end
     $var wire 8 ) out4 [7:0] $end
-    $var wire 8 T# out4_2 [7:0] $end
+    $var wire 8 W# out4_2 [7:0] $end
     $scope module i_sub4_0 $end
-     $var parameter 32 M" P0 [31:0] $end
-     $var real_parameter 64 N" P1 $end
-     $var real_parameter 64 O" P3 $end
+     $var parameter 32 O" P0 [31:0] $end
+     $var real_parameter 64 P" P1 $end
+     $var real_parameter 64 Q" P3 $end
      $var wire 1 $ clk $end
-     $var wire 8 S# in [7:0] $end
+     $var wire 8 X# in [7:0] $end
      $var wire 8 ) out [7:0] $end
      $var logic 8 ) ff [7:0] $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array sub5_in $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [0] $end
-       $var logic 128 U# sub5_in[0][0] [127:0] $end
-       $var logic 128 V# sub5_in[0][1] [127:0] $end
-       $var logic 128 W# sub5_in[0][2] [127:0] $end
+       $var logic 128 Y# sub5_in[0][0] [127:0] $end
+       $var logic 128 Z# sub5_in[0][1] [127:0] $end
+       $var logic 128 [# sub5_in[0][2] [127:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [1] $end
-       $var logic 128 X# sub5_in[1][0] [127:0] $end
-       $var logic 128 Y# sub5_in[1][1] [127:0] $end
-       $var logic 128 Z# sub5_in[1][2] [127:0] $end
+       $var logic 128 \# sub5_in[1][0] [127:0] $end
+       $var logic 128 ]# sub5_in[1][1] [127:0] $end
+       $var logic 128 ^# sub5_in[1][2] [127:0] $end
       $upscope $end
      $upscope $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array sub5_out $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [0] $end
-       $var wire 8 [# sub5_out[0][0] [7:0] $end
-       $var wire 8 \# sub5_out[0][1] [7:0] $end
-       $var wire 8 ]# sub5_out[0][2] [7:0] $end
+       $var wire 8 _# sub5_out[0][0] [7:0] $end
+       $var wire 8 `# sub5_out[0][1] [7:0] $end
+       $var wire 8 a# sub5_out[0][2] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [1] $end
-       $var wire 8 ^# sub5_out[1][0] [7:0] $end
-       $var wire 8 _# sub5_out[1][1] [7:0] $end
-       $var wire 8 `# sub5_out[1][2] [7:0] $end
+       $var wire 8 b# sub5_out[1][0] [7:0] $end
+       $var wire 8 c# sub5_out[1][1] [7:0] $end
+       $var wire 8 d# sub5_out[1][2] [7:0] $end
       $upscope $end
      $upscope $end
-     $var int 32 a# count [31:0] $end
-     $var int 32 b# driven_from_bind [31:0] $end
+     $var int 32 e# count [31:0] $end
+     $var int 32 f# driven_from_bind [31:0] $end
      $scope module i_sub4_bound $end
-      $var real_parameter 64 N" P1 $end
-      $var wire 32 b# driven_from_bind [31:0] $end
+      $var real_parameter 64 P" P1 $end
+      $var wire 32 f# driven_from_bind [31:0] $end
      $upscope $end
      $scope module i_sub5 $end
-      $var wire 1 c# clk $end
+      $var wire 1 g# clk $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array in $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [0] $end
-        $var wire 128 d# in[0][0] [127:0] $end
-        $var wire 128 e# in[0][1] [127:0] $end
-        $var wire 128 f# in[0][2] [127:0] $end
+        $var wire 128 h# in[0][0] [127:0] $end
+        $var wire 128 i# in[0][1] [127:0] $end
+        $var wire 128 j# in[0][2] [127:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [1] $end
-        $var wire 128 g# in[1][0] [127:0] $end
-        $var wire 128 h# in[1][1] [127:0] $end
-        $var wire 128 i# in[1][2] [127:0] $end
+        $var wire 128 k# in[1][0] [127:0] $end
+        $var wire 128 l# in[1][1] [127:0] $end
+        $var wire 128 m# in[1][2] [127:0] $end
        $upscope $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array out $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [0] $end
-        $var wire 8 j# out[0][0] [7:0] $end
-        $var wire 8 k# out[0][1] [7:0] $end
-        $var wire 8 l# out[0][2] [7:0] $end
+        $var wire 8 n# out[0][0] [7:0] $end
+        $var wire 8 o# out[0][1] [7:0] $end
+        $var wire 8 p# out[0][2] [7:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [1] $end
-        $var wire 8 m# out[1][0] [7:0] $end
-        $var wire 8 n# out[1][1] [7:0] $end
-        $var wire 8 o# out[1][2] [7:0] $end
+        $var wire 8 q# out[1][0] [7:0] $end
+        $var wire 8 r# out[1][1] [7:0] $end
+        $var wire 8 s# out[1][2] [7:0] $end
        $upscope $end
       $upscope $end
-      $var int 32 p# count [31:0] $end
+      $var int 32 t# count [31:0] $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array val0 $end
-       $var wire 8 q# val0[0] [7:0] $end
-       $var wire 8 r# val0[1] [7:0] $end
+       $var wire 8 u# val0[0] [7:0] $end
+       $var wire 8 v# val0[1] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array val1 $end
-       $var wire 8 s# val1[0] [7:0] $end
-       $var wire 8 t# val1[1] [7:0] $end
+       $var wire 8 w# val1[0] [7:0] $end
+       $var wire 8 x# val1[1] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array val2 $end
-       $var wire 8 u# val2[0] [7:0] $end
-       $var wire 8 v# val2[1] [7:0] $end
+       $var wire 8 y# val2[0] [7:0] $end
+       $var wire 8 z# val2[1] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array val3 $end
-       $var wire 8 w# val3[0] [7:0] $end
-       $var wire 8 x# val3[1] [7:0] $end
+       $var wire 8 {# val3[0] [7:0] $end
+       $var wire 8 |# val3[1] [7:0] $end
       $upscope $end
       $scope module i_sub0 $end
-       $var parameter 32 y# P0 [31:0] $end
-       $var parameter 32 z# P1 [31:0] $end
-       $attrbegin array unpacked bounds 1 $end
-       $scope sv_array out $end
-        $var wire 8 {# out[0] [7:0] $end
-        $var wire 8 |# out[1] [7:0] $end
-       $upscope $end
-      $upscope $end
-      $scope module i_sub1 $end
-       $var parameter 32 y# P0 [31:0] $end
-       $var parameter 32 z# P1 [31:0] $end
-       $attrbegin array unpacked bounds 1 $end
-       $scope sv_array out $end
-        $var wire 8 }# out[0] [7:0] $end
-        $var wire 8 ~# out[1] [7:0] $end
-       $upscope $end
-      $upscope $end
-      $scope module i_sub2 $end
-       $var parameter 32 y# P0 [31:0] $end
-       $var parameter 32 z# P1 [31:0] $end
+       $var parameter 32 }# P0 [31:0] $end
+       $var parameter 32 ~# P1 [31:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array out $end
         $var wire 8 !$ out[0] [7:0] $end
         $var wire 8 "$ out[1] [7:0] $end
        $upscope $end
       $upscope $end
-      $scope module i_sub3 $end
-       $var parameter 32 y# P0 [31:0] $end
-       $var parameter 32 #$ P1 [31:0] $end
+      $scope module i_sub1 $end
+       $var parameter 32 }# P0 [31:0] $end
+       $var parameter 32 ~# P1 [31:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array out $end
-        $var wire 8 $$ out[0] [7:0] $end
-        $var wire 8 %$ out[1] [7:0] $end
+        $var wire 8 #$ out[0] [7:0] $end
+        $var wire 8 $$ out[1] [7:0] $end
+       $upscope $end
+      $upscope $end
+      $scope module i_sub2 $end
+       $var parameter 32 }# P0 [31:0] $end
+       $var parameter 32 ~# P1 [31:0] $end
+       $attrbegin array unpacked bounds 1 $end
+       $scope sv_array out $end
+        $var wire 8 %$ out[0] [7:0] $end
+        $var wire 8 &$ out[1] [7:0] $end
+       $upscope $end
+      $upscope $end
+      $scope module i_sub3 $end
+       $var parameter 32 }# P0 [31:0] $end
+       $var parameter 32 '$ P1 [31:0] $end
+       $attrbegin array unpacked bounds 1 $end
+       $scope sv_array out $end
+        $var wire 8 ($ out[0] [7:0] $end
+        $var wire 8 )$ out[1] [7:0] $end
        $upscope $end
       $upscope $end
      $upscope $end
     $upscope $end
     $scope module i_sub4_1 $end
-     $var parameter 32 M" P0 [31:0] $end
-     $var real_parameter 64 N" P1 $end
-     $var real_parameter 64 !# P3 $end
+     $var parameter 32 O" P0 [31:0] $end
+     $var real_parameter 64 P" P1 $end
+     $var real_parameter 64 $# P3 $end
      $var wire 1 $ clk $end
-     $var wire 8 S# in [7:0] $end
-     $var wire 8 T# out [7:0] $end
-     $var logic 8 T# ff [7:0] $end
+     $var wire 8 X# in [7:0] $end
+     $var wire 8 W# out [7:0] $end
+     $var logic 8 W# ff [7:0] $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array sub5_in $end
       $attrbegin array unpacked bounds 2 $end
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-       $var logic 128 &$ sub5_in[0][0] [127:0] $end
-       $var logic 128 '$ sub5_in[0][1] [127:0] $end
-       $var logic 128 ($ sub5_in[0][2] [127:0] $end
+       $var logic 128 *$ sub5_in[0][0] [127:0] $end
+       $var logic 128 +$ sub5_in[0][1] [127:0] $end
+       $var logic 128 ,$ sub5_in[0][2] [127:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [1] $end
-       $var logic 128 )$ sub5_in[1][0] [127:0] $end
-       $var logic 128 *$ sub5_in[1][1] [127:0] $end
-       $var logic 128 +$ sub5_in[1][2] [127:0] $end
+       $var logic 128 -$ sub5_in[1][0] [127:0] $end
+       $var logic 128 .$ sub5_in[1][1] [127:0] $end
+       $var logic 128 /$ sub5_in[1][2] [127:0] $end
       $upscope $end
      $upscope $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array sub5_out $end
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-       $var wire 8 ,$ sub5_out[0][0] [7:0] $end
-       $var wire 8 -$ sub5_out[0][1] [7:0] $end
-       $var wire 8 .$ sub5_out[0][2] [7:0] $end
+       $var wire 8 0$ sub5_out[0][0] [7:0] $end
+       $var wire 8 1$ sub5_out[0][1] [7:0] $end
+       $var wire 8 2$ sub5_out[0][2] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 2 $end
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-       $var wire 8 /$ sub5_out[1][0] [7:0] $end
-       $var wire 8 0$ sub5_out[1][1] [7:0] $end
-       $var wire 8 1$ sub5_out[1][2] [7:0] $end
+       $var wire 8 3$ sub5_out[1][0] [7:0] $end
+       $var wire 8 4$ sub5_out[1][1] [7:0] $end
+       $var wire 8 5$ sub5_out[1][2] [7:0] $end
       $upscope $end
      $upscope $end
-     $var int 32 2$ count [31:0] $end
-     $var int 32 3$ driven_from_bind [31:0] $end
+     $var int 32 6$ count [31:0] $end
+     $var int 32 7$ driven_from_bind [31:0] $end
      $scope module i_sub4_bound $end
-      $var real_parameter 64 N" P1 $end
-      $var wire 32 3$ driven_from_bind [31:0] $end
+      $var real_parameter 64 P" P1 $end
+      $var wire 32 7$ driven_from_bind [31:0] $end
      $upscope $end
      $scope module i_sub5 $end
-      $var wire 1 4$ clk $end
+      $var wire 1 8$ clk $end
       $attrbegin array unpacked bounds 1 $end
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        $attrbegin array unpacked bounds 2 $end
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-        $var wire 128 5$ in[0][0] [127:0] $end
-        $var wire 128 6$ in[0][1] [127:0] $end
-        $var wire 128 7$ in[0][2] [127:0] $end
+        $var wire 128 9$ in[0][0] [127:0] $end
+        $var wire 128 :$ in[0][1] [127:0] $end
+        $var wire 128 ;$ in[0][2] [127:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 2 $end
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-        $var wire 128 8$ in[1][0] [127:0] $end
-        $var wire 128 9$ in[1][1] [127:0] $end
-        $var wire 128 :$ in[1][2] [127:0] $end
+        $var wire 128 <$ in[1][0] [127:0] $end
+        $var wire 128 =$ in[1][1] [127:0] $end
+        $var wire 128 >$ in[1][2] [127:0] $end
        $upscope $end
       $upscope $end
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-        $var wire 8 <$ out[0][1] [7:0] $end
-        $var wire 8 =$ out[0][2] [7:0] $end
+        $var wire 8 ?$ out[0][0] [7:0] $end
+        $var wire 8 @$ out[0][1] [7:0] $end
+        $var wire 8 A$ out[0][2] [7:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 2 $end
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-        $var wire 8 >$ out[1][0] [7:0] $end
-        $var wire 8 ?$ out[1][1] [7:0] $end
-        $var wire 8 @$ out[1][2] [7:0] $end
+        $var wire 8 B$ out[1][0] [7:0] $end
+        $var wire 8 C$ out[1][1] [7:0] $end
+        $var wire 8 D$ out[1][2] [7:0] $end
        $upscope $end
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-      $var int 32 A$ count [31:0] $end
+      $var int 32 E$ count [31:0] $end
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-       $var wire 8 B$ val0[0] [7:0] $end
-       $var wire 8 C$ val0[1] [7:0] $end
+       $var wire 8 F$ val0[0] [7:0] $end
+       $var wire 8 G$ val0[1] [7:0] $end
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-       $var wire 8 D$ val1[0] [7:0] $end
-       $var wire 8 E$ val1[1] [7:0] $end
+       $var wire 8 H$ val1[0] [7:0] $end
+       $var wire 8 I$ val1[1] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
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-       $var wire 8 F$ val2[0] [7:0] $end
-       $var wire 8 G$ val2[1] [7:0] $end
+       $var wire 8 J$ val2[0] [7:0] $end
+       $var wire 8 K$ val2[1] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array val3 $end
-       $var wire 8 H$ val3[0] [7:0] $end
-       $var wire 8 I$ val3[1] [7:0] $end
+       $var wire 8 L$ val3[0] [7:0] $end
+       $var wire 8 M$ val3[1] [7:0] $end
       $upscope $end
       $scope module i_sub0 $end
-       $var parameter 32 J$ P0 [31:0] $end
-       $var parameter 32 K$ P1 [31:0] $end
-       $attrbegin array unpacked bounds 1 $end
-       $scope sv_array out $end
-        $var wire 8 L$ out[0] [7:0] $end
-        $var wire 8 M$ out[1] [7:0] $end
-       $upscope $end
-      $upscope $end
-      $scope module i_sub1 $end
-       $var parameter 32 J$ P0 [31:0] $end
-       $var parameter 32 K$ P1 [31:0] $end
-       $attrbegin array unpacked bounds 1 $end
-       $scope sv_array out $end
-        $var wire 8 N$ out[0] [7:0] $end
-        $var wire 8 O$ out[1] [7:0] $end
-       $upscope $end
-      $upscope $end
-      $scope module i_sub2 $end
-       $var parameter 32 J$ P0 [31:0] $end
-       $var parameter 32 K$ P1 [31:0] $end
+       $var parameter 32 N$ P0 [31:0] $end
+       $var parameter 32 O$ P1 [31:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array out $end
         $var wire 8 P$ out[0] [7:0] $end
         $var wire 8 Q$ out[1] [7:0] $end
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       $upscope $end
-      $scope module i_sub3 $end
-       $var parameter 32 J$ P0 [31:0] $end
-       $var parameter 32 R$ P1 [31:0] $end
+      $scope module i_sub1 $end
+       $var parameter 32 N$ P0 [31:0] $end
+       $var parameter 32 O$ P1 [31:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array out $end
-        $var wire 8 S$ out[0] [7:0] $end
-        $var wire 8 T$ out[1] [7:0] $end
+        $var wire 8 R$ out[0] [7:0] $end
+        $var wire 8 S$ out[1] [7:0] $end
+       $upscope $end
+      $upscope $end
+      $scope module i_sub2 $end
+       $var parameter 32 N$ P0 [31:0] $end
+       $var parameter 32 O$ P1 [31:0] $end
+       $attrbegin array unpacked bounds 1 $end
+       $scope sv_array out $end
+        $var wire 8 T$ out[0] [7:0] $end
+        $var wire 8 U$ out[1] [7:0] $end
+       $upscope $end
+      $upscope $end
+      $scope module i_sub3 $end
+       $var parameter 32 N$ P0 [31:0] $end
+       $var parameter 32 V$ P1 [31:0] $end
+       $attrbegin array unpacked bounds 1 $end
+       $scope sv_array out $end
+        $var wire 8 W$ out[0] [7:0] $end
+        $var wire 8 X$ out[1] [7:0] $end
        $upscope $end
       $upscope $end
      $upscope $end
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+b00011101 N!
 b00010101 +
 b00011011 (
 b00011011 )
 b00011011 5
-b00011011 L"
-b00011011 T#
+b00011011 N"
+b00011011 W#
 b00011001 >
 b00011001 ;
 b00011001 :
diff --git a/test_regress/t/t_trace_hier_block_default_sc_vcd.out b/test_regress/t/t_trace_hier_block_default_sc_vcd.out
index dfa2c07dd..7c9621fbb 100644
--- a/test_regress/t/t_trace_hier_block_default_sc_vcd.out
+++ b/test_regress/t/t_trace_hier_block_default_sc_vcd.out
@@ -2,32 +2,32 @@ $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module top $end
   $scope module stateless_pkg $end
-   $var wire 32 h! ONE [31:0] $end
+   $var wire 32 j! ONE [31:0] $end
   $upscope $end
   $scope module t $end
-   $var wire 32 T! PARAM_A [31:0] $end
-   $var wire 32 U! PARAM_B [31:0] $end
-   $var wire 1 Q! clk $end
-   $var wire 8 6! out0 [7:0] $end
-   $var wire 8 7! out1 [7:0] $end
-   $var wire 8 8! out2 [7:0] $end
-   $var wire 8 R! out3 [7:0] $end
+   $var wire 32 V! PARAM_A [31:0] $end
+   $var wire 32 W! PARAM_B [31:0] $end
+   $var wire 1 U! clk $end
+   $var wire 8 :! out0 [7:0] $end
+   $var wire 8 ;! out1 [7:0] $end
+   $var wire 8 <! out2 [7:0] $end
+   $var wire 8 7! out3 [7:0] $end
    $var wire 8 & out3_2 [7:0] $end
    $var wire 8 ' out5 [7:0] $end
    $var wire 8 ( out6 [7:0] $end
    $var wire 32 ) count [31:0] $end
    $scope module i_delay0 $end
-    $var wire 32 V! N [31:0] $end
-    $var wire 32 W! WIDTH [31:0] $end
-    $var wire 1 Q! clk $end
-    $var wire 8 R! in [7:0] $end
+    $var wire 32 X! N [31:0] $end
+    $var wire 32 Y! WIDTH [31:0] $end
+    $var wire 1 U! clk $end
+    $var wire 8 7! in [7:0] $end
     $var wire 8 ' out [7:0] $end
     $var wire 8 * tmp [7:0] $end
     $scope module genblk1 $end
      $scope module i_delay $end
-      $var wire 32 X! N [31:0] $end
-      $var wire 32 W! WIDTH [31:0] $end
-      $var wire 1 Q! clk $end
+      $var wire 32 Z! N [31:0] $end
+      $var wire 32 Y! WIDTH [31:0] $end
+      $var wire 1 U! clk $end
       $var wire 8 * in [7:0] $end
       $var wire 8 ' out [7:0] $end
       $var wire 8 ' tmp [7:0] $end
@@ -35,25 +35,25 @@ $timescale 1ps $end
     $upscope $end
    $upscope $end
    $scope module i_delay1 $end
-    $var wire 32 Y! N [31:0] $end
-    $var wire 32 W! WIDTH [31:0] $end
-    $var wire 1 Q! clk $end
+    $var wire 32 [! N [31:0] $end
+    $var wire 32 Y! WIDTH [31:0] $end
+    $var wire 1 U! clk $end
     $var wire 8 ' in [7:0] $end
     $var wire 8 ( out [7:0] $end
     $var wire 8 + tmp [7:0] $end
     $scope module genblk1 $end
      $scope module i_delay $end
-      $var wire 32 V! N [31:0] $end
-      $var wire 32 W! WIDTH [31:0] $end
-      $var wire 1 Q! clk $end
+      $var wire 32 X! N [31:0] $end
+      $var wire 32 Y! WIDTH [31:0] $end
+      $var wire 1 U! clk $end
       $var wire 8 + in [7:0] $end
       $var wire 8 ( out [7:0] $end
       $var wire 8 , tmp [7:0] $end
       $scope module genblk1 $end
        $scope module i_delay $end
-        $var wire 32 X! N [31:0] $end
-        $var wire 32 W! WIDTH [31:0] $end
-        $var wire 1 Q! clk $end
+        $var wire 32 Z! N [31:0] $end
+        $var wire 32 Y! WIDTH [31:0] $end
+        $var wire 1 U! clk $end
         $var wire 8 , in [7:0] $end
         $var wire 8 ( out [7:0] $end
         $var wire 8 ( tmp [7:0] $end
@@ -63,470 +63,470 @@ $timescale 1ps $end
     $upscope $end
    $upscope $end
    $scope module i_sub0 $end
-    $var wire 1 Q! clk $end
-    $var wire 8 R! in [7:0] $end
-    $var wire 8 6! out [7:0] $end
+    $var wire 1 U! clk $end
+    $var wire 8 7! in [7:0] $end
+    $var wire 8 :! out [7:0] $end
     $scope module i_sub0 $end
-     $var wire 1 i! clk $end
-     $var wire 8 j! in [7:0] $end
-     $var wire 8 k! out [7:0] $end
-     $var wire 8 l! ff [7:0] $end
+     $var wire 1 k! clk $end
+     $var wire 8 l! in [7:0] $end
+     $var wire 8 m! out [7:0] $end
+     $var wire 8 n! ff [7:0] $end
     $upscope $end
    $upscope $end
    $scope module i_sub1 $end
-    $var wire 1 m! clk $end
-    $var wire 8 n! in [11:4] $end
-    $var wire 8 o! out [7:0] $end
-    $var wire 8 p! ff [7:0] $end
-    $var wire 2 q! enum_v [1:0] $end
+    $var wire 1 o! clk $end
+    $var wire 8 p! in [11:4] $end
+    $var wire 8 q! out [7:0] $end
+    $var wire 8 r! ff [7:0] $end
+    $var wire 2 s! enum_v [1:0] $end
    $upscope $end
    $scope module i_sub2 $end
-    $var wire 1 >% clk $end
-    $var wire 8 ?% in [7:0] $end
-    $var wire 8 @% out [7:0] $end
-    $var wire 8 X" ff [7:0] $end
-    $var wire 2 Y" alt_enum_v [1:0] $end
+    $var wire 1 B% clk $end
+    $var wire 8 C% in [7:0] $end
+    $var wire 8 D% out [7:0] $end
+    $var wire 8 Z" ff [7:0] $end
+    $var wire 2 [" alt_enum_v [1:0] $end
     $scope module i_sub3 $end
-     $var wire 8 X" in_wire [7:0] $end
-     $var wire 8 Z" out_1 [7:0] $end
-     $var wire 8 [" out_2 [7:0] $end
+     $var wire 8 Z" in_wire [7:0] $end
+     $var wire 8 \" out_1 [7:0] $end
+     $var wire 8 ]" out_2 [7:0] $end
      $scope module i_sub3 $end
-      $var wire 8 A% P0 [7:0] $end
-      $var wire 32 B% UNPACKED_ARRAY[0] [31:0] $end
-      $var wire 32 C% UNPACKED_ARRAY[1] [31:0] $end
-      $var wire 16 D% UNUSED [15:0] $end
-      $var wire 2 E% ENUM [1:0] $end
-      $var wire 1 >% clk $end
-      $var wire 8 X" in [7:0] $end
-      $var wire 8 Z" out [7:0] $end
-      $var wire 8 \" ff [7:0] $end
-      $var wire 8 Z" out4 [7:0] $end
-      $var wire 8 ]" out4_2 [7:0] $end
+      $var wire 8 E% P0 [7:0] $end
+      $var wire 32 F% UNPACKED_ARRAY[0] [31:0] $end
+      $var wire 32 G% UNPACKED_ARRAY[1] [31:0] $end
+      $var wire 16 H% UNUSED [15:0] $end
+      $var wire 2 I% ENUM [1:0] $end
+      $var wire 1 B% clk $end
+      $var wire 8 Z" in [7:0] $end
+      $var wire 8 \" out [7:0] $end
+      $var wire 8 ^" ff [7:0] $end
+      $var wire 8 \" out4 [7:0] $end
+      $var wire 8 _" out4_2 [7:0] $end
       $scope module i_sub4_0 $end
-       $var wire 32 F% P0 [31:0] $end
-       $var real 64 G% P1 $end
-       $var real 64 I% P3 $end
-       $var wire 1 >% clk $end
-       $var wire 8 \" in [7:0] $end
-       $var wire 8 Z" out [7:0] $end
-       $var wire 8 Z" ff [7:0] $end
-       $var wire 128 ^" sub5_in[0][0] [127:0] $end
-       $var wire 128 b" sub5_in[0][1] [127:0] $end
-       $var wire 128 f" sub5_in[0][2] [127:0] $end
-       $var wire 128 j" sub5_in[1][0] [127:0] $end
-       $var wire 128 n" sub5_in[1][1] [127:0] $end
-       $var wire 128 r" sub5_in[1][2] [127:0] $end
-       $var wire 8 v" sub5_out[0][0] [7:0] $end
-       $var wire 8 w" sub5_out[0][1] [7:0] $end
-       $var wire 8 x" sub5_out[0][2] [7:0] $end
-       $var wire 8 y" sub5_out[1][0] [7:0] $end
-       $var wire 8 z" sub5_out[1][1] [7:0] $end
-       $var wire 8 {" sub5_out[1][2] [7:0] $end
-       $var wire 32 |" count [31:0] $end
-       $var wire 32 r! driven_from_bind [31:0] $end
+       $var wire 32 J% P0 [31:0] $end
+       $var real 64 K% P1 $end
+       $var real 64 M% P3 $end
+       $var wire 1 B% clk $end
+       $var wire 8 `" in [7:0] $end
+       $var wire 8 \" out [7:0] $end
+       $var wire 8 \" ff [7:0] $end
+       $var wire 128 a" sub5_in[0][0] [127:0] $end
+       $var wire 128 e" sub5_in[0][1] [127:0] $end
+       $var wire 128 i" sub5_in[0][2] [127:0] $end
+       $var wire 128 m" sub5_in[1][0] [127:0] $end
+       $var wire 128 q" sub5_in[1][1] [127:0] $end
+       $var wire 128 u" sub5_in[1][2] [127:0] $end
+       $var wire 8 y" sub5_out[0][0] [7:0] $end
+       $var wire 8 z" sub5_out[0][1] [7:0] $end
+       $var wire 8 {" sub5_out[0][2] [7:0] $end
+       $var wire 8 |" sub5_out[1][0] [7:0] $end
+       $var wire 8 }" sub5_out[1][1] [7:0] $end
+       $var wire 8 ~" sub5_out[1][2] [7:0] $end
+       $var wire 32 !# count [31:0] $end
+       $var wire 32 t! driven_from_bind [31:0] $end
        $scope module i_sub4_bound $end
-        $var real 64 G% P1 $end
-        $var wire 32 r! driven_from_bind [31:0] $end
+        $var real 64 K% P1 $end
+        $var wire 32 t! driven_from_bind [31:0] $end
        $upscope $end
        $scope module i_sub5 $end
-        $var wire 1 >% clk $end
-        $var wire 128 }" in[0][0] [127:0] $end
-        $var wire 128 ## in[0][1] [127:0] $end
-        $var wire 128 '# in[0][2] [127:0] $end
-        $var wire 128 +# in[1][0] [127:0] $end
-        $var wire 128 /# in[1][1] [127:0] $end
-        $var wire 128 3# in[1][2] [127:0] $end
-        $var wire 8 7# out[0][0] [7:0] $end
-        $var wire 8 8# out[0][1] [7:0] $end
-        $var wire 8 9# out[0][2] [7:0] $end
-        $var wire 8 :# out[1][0] [7:0] $end
-        $var wire 8 ;# out[1][1] [7:0] $end
-        $var wire 8 <# out[1][2] [7:0] $end
-        $var wire 32 =# count [31:0] $end
-        $var wire 8 s! val0[0] [7:0] $end
-        $var wire 8 t! val0[1] [7:0] $end
-        $var wire 8 u! val1[0] [7:0] $end
-        $var wire 8 v! val1[1] [7:0] $end
-        $var wire 8 w! val2[0] [7:0] $end
-        $var wire 8 x! val2[1] [7:0] $end
-        $var wire 8 y! val3[0] [7:0] $end
-        $var wire 8 z! val3[1] [7:0] $end
+        $var wire 1 B% clk $end
+        $var wire 128 "# in[0][0] [127:0] $end
+        $var wire 128 &# in[0][1] [127:0] $end
+        $var wire 128 *# in[0][2] [127:0] $end
+        $var wire 128 .# in[1][0] [127:0] $end
+        $var wire 128 2# in[1][1] [127:0] $end
+        $var wire 128 6# in[1][2] [127:0] $end
+        $var wire 8 :# out[0][0] [7:0] $end
+        $var wire 8 ;# out[0][1] [7:0] $end
+        $var wire 8 <# out[0][2] [7:0] $end
+        $var wire 8 =# out[1][0] [7:0] $end
+        $var wire 8 ># out[1][1] [7:0] $end
+        $var wire 8 ?# out[1][2] [7:0] $end
+        $var wire 32 @# count [31:0] $end
+        $var wire 8 u! val0[0] [7:0] $end
+        $var wire 8 v! val0[1] [7:0] $end
+        $var wire 8 w! val1[0] [7:0] $end
+        $var wire 8 x! val1[1] [7:0] $end
+        $var wire 8 y! val2[0] [7:0] $end
+        $var wire 8 z! val2[1] [7:0] $end
+        $var wire 8 {! val3[0] [7:0] $end
+        $var wire 8 |! val3[1] [7:0] $end
         $scope module i_sub0 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 L% P1 [31:0] $end
-         $var wire 8 {! out[0] [7:0] $end
-         $var wire 8 |! out[1] [7:0] $end
-        $upscope $end
-        $scope module i_sub1 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 L% P1 [31:0] $end
+         $var wire 32 O% P0 [31:0] $end
+         $var wire 32 P% P1 [31:0] $end
          $var wire 8 }! out[0] [7:0] $end
          $var wire 8 ~! out[1] [7:0] $end
         $upscope $end
-        $scope module i_sub2 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 L% P1 [31:0] $end
+        $scope module i_sub1 $end
+         $var wire 32 O% P0 [31:0] $end
+         $var wire 32 P% P1 [31:0] $end
          $var wire 8 !" out[0] [7:0] $end
          $var wire 8 "" out[1] [7:0] $end
         $upscope $end
-        $scope module i_sub3 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 M% P1 [31:0] $end
+        $scope module i_sub2 $end
+         $var wire 32 O% P0 [31:0] $end
+         $var wire 32 P% P1 [31:0] $end
          $var wire 8 #" out[0] [7:0] $end
          $var wire 8 $" out[1] [7:0] $end
         $upscope $end
+        $scope module i_sub3 $end
+         $var wire 32 O% P0 [31:0] $end
+         $var wire 32 Q% P1 [31:0] $end
+         $var wire 8 %" out[0] [7:0] $end
+         $var wire 8 &" out[1] [7:0] $end
+        $upscope $end
        $upscope $end
       $upscope $end
       $scope module i_sub4_1 $end
-       $var wire 32 F% P0 [31:0] $end
-       $var real 64 G% P1 $end
-       $var real 64 N% P3 $end
-       $var wire 1 >% clk $end
-       $var wire 8 \" in [7:0] $end
-       $var wire 8 ]" out [7:0] $end
-       $var wire 8 ]" ff [7:0] $end
-       $var wire 128 ># sub5_in[0][0] [127:0] $end
-       $var wire 128 B# sub5_in[0][1] [127:0] $end
-       $var wire 128 F# sub5_in[0][2] [127:0] $end
-       $var wire 128 J# sub5_in[1][0] [127:0] $end
-       $var wire 128 N# sub5_in[1][1] [127:0] $end
-       $var wire 128 R# sub5_in[1][2] [127:0] $end
-       $var wire 8 V# sub5_out[0][0] [7:0] $end
-       $var wire 8 W# sub5_out[0][1] [7:0] $end
-       $var wire 8 X# sub5_out[0][2] [7:0] $end
-       $var wire 8 Y# sub5_out[1][0] [7:0] $end
-       $var wire 8 Z# sub5_out[1][1] [7:0] $end
-       $var wire 8 [# sub5_out[1][2] [7:0] $end
-       $var wire 32 \# count [31:0] $end
-       $var wire 32 %" driven_from_bind [31:0] $end
+       $var wire 32 J% P0 [31:0] $end
+       $var real 64 K% P1 $end
+       $var real 64 R% P3 $end
+       $var wire 1 B% clk $end
+       $var wire 8 `" in [7:0] $end
+       $var wire 8 _" out [7:0] $end
+       $var wire 8 _" ff [7:0] $end
+       $var wire 128 A# sub5_in[0][0] [127:0] $end
+       $var wire 128 E# sub5_in[0][1] [127:0] $end
+       $var wire 128 I# sub5_in[0][2] [127:0] $end
+       $var wire 128 M# sub5_in[1][0] [127:0] $end
+       $var wire 128 Q# sub5_in[1][1] [127:0] $end
+       $var wire 128 U# sub5_in[1][2] [127:0] $end
+       $var wire 8 Y# sub5_out[0][0] [7:0] $end
+       $var wire 8 Z# sub5_out[0][1] [7:0] $end
+       $var wire 8 [# sub5_out[0][2] [7:0] $end
+       $var wire 8 \# sub5_out[1][0] [7:0] $end
+       $var wire 8 ]# sub5_out[1][1] [7:0] $end
+       $var wire 8 ^# sub5_out[1][2] [7:0] $end
+       $var wire 32 _# count [31:0] $end
+       $var wire 32 '" driven_from_bind [31:0] $end
        $scope module i_sub4_bound $end
-        $var real 64 G% P1 $end
-        $var wire 32 %" driven_from_bind [31:0] $end
+        $var real 64 K% P1 $end
+        $var wire 32 '" driven_from_bind [31:0] $end
        $upscope $end
        $scope module i_sub5 $end
-        $var wire 1 >% clk $end
-        $var wire 128 ]# in[0][0] [127:0] $end
-        $var wire 128 a# in[0][1] [127:0] $end
-        $var wire 128 e# in[0][2] [127:0] $end
-        $var wire 128 i# in[1][0] [127:0] $end
-        $var wire 128 m# in[1][1] [127:0] $end
-        $var wire 128 q# in[1][2] [127:0] $end
-        $var wire 8 u# out[0][0] [7:0] $end
-        $var wire 8 v# out[0][1] [7:0] $end
-        $var wire 8 w# out[0][2] [7:0] $end
-        $var wire 8 x# out[1][0] [7:0] $end
-        $var wire 8 y# out[1][1] [7:0] $end
-        $var wire 8 z# out[1][2] [7:0] $end
-        $var wire 32 {# count [31:0] $end
-        $var wire 8 &" val0[0] [7:0] $end
-        $var wire 8 '" val0[1] [7:0] $end
-        $var wire 8 (" val1[0] [7:0] $end
-        $var wire 8 )" val1[1] [7:0] $end
-        $var wire 8 *" val2[0] [7:0] $end
-        $var wire 8 +" val2[1] [7:0] $end
-        $var wire 8 ," val3[0] [7:0] $end
-        $var wire 8 -" val3[1] [7:0] $end
+        $var wire 1 B% clk $end
+        $var wire 128 `# in[0][0] [127:0] $end
+        $var wire 128 d# in[0][1] [127:0] $end
+        $var wire 128 h# in[0][2] [127:0] $end
+        $var wire 128 l# in[1][0] [127:0] $end
+        $var wire 128 p# in[1][1] [127:0] $end
+        $var wire 128 t# in[1][2] [127:0] $end
+        $var wire 8 x# out[0][0] [7:0] $end
+        $var wire 8 y# out[0][1] [7:0] $end
+        $var wire 8 z# out[0][2] [7:0] $end
+        $var wire 8 {# out[1][0] [7:0] $end
+        $var wire 8 |# out[1][1] [7:0] $end
+        $var wire 8 }# out[1][2] [7:0] $end
+        $var wire 32 ~# count [31:0] $end
+        $var wire 8 (" val0[0] [7:0] $end
+        $var wire 8 )" val0[1] [7:0] $end
+        $var wire 8 *" val1[0] [7:0] $end
+        $var wire 8 +" val1[1] [7:0] $end
+        $var wire 8 ," val2[0] [7:0] $end
+        $var wire 8 -" val2[1] [7:0] $end
+        $var wire 8 ." val3[0] [7:0] $end
+        $var wire 8 /" val3[1] [7:0] $end
         $scope module i_sub0 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 L% P1 [31:0] $end
-         $var wire 8 ." out[0] [7:0] $end
-         $var wire 8 /" out[1] [7:0] $end
-        $upscope $end
-        $scope module i_sub1 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 L% P1 [31:0] $end
+         $var wire 32 O% P0 [31:0] $end
+         $var wire 32 P% P1 [31:0] $end
          $var wire 8 0" out[0] [7:0] $end
          $var wire 8 1" out[1] [7:0] $end
         $upscope $end
-        $scope module i_sub2 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 L% P1 [31:0] $end
+        $scope module i_sub1 $end
+         $var wire 32 O% P0 [31:0] $end
+         $var wire 32 P% P1 [31:0] $end
          $var wire 8 2" out[0] [7:0] $end
          $var wire 8 3" out[1] [7:0] $end
         $upscope $end
-        $scope module i_sub3 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 M% P1 [31:0] $end
+        $scope module i_sub2 $end
+         $var wire 32 O% P0 [31:0] $end
+         $var wire 32 P% P1 [31:0] $end
          $var wire 8 4" out[0] [7:0] $end
          $var wire 8 5" out[1] [7:0] $end
         $upscope $end
+        $scope module i_sub3 $end
+         $var wire 32 O% P0 [31:0] $end
+         $var wire 32 Q% P1 [31:0] $end
+         $var wire 8 6" out[0] [7:0] $end
+         $var wire 8 7" out[1] [7:0] $end
+        $upscope $end
        $upscope $end
       $upscope $end
      $upscope $end
      $scope module i_sub3_2 $end
-      $var wire 8 A% P0 [7:0] $end
-      $var wire 32 P% UNPACKED_ARRAY[0] [31:0] $end
-      $var wire 32 Q% UNPACKED_ARRAY[1] [31:0] $end
-      $var wire 16 D% UNUSED [15:0] $end
-      $var wire 2 E% ENUM [1:0] $end
-      $var wire 1 >% clk $end
-      $var wire 8 X" in [7:0] $end
-      $var wire 8 [" out [7:0] $end
-      $var wire 8 |# ff [7:0] $end
-      $var wire 8 [" out4 [7:0] $end
-      $var wire 8 }# out4_2 [7:0] $end
+      $var wire 8 E% P0 [7:0] $end
+      $var wire 32 T% UNPACKED_ARRAY[0] [31:0] $end
+      $var wire 32 U% UNPACKED_ARRAY[1] [31:0] $end
+      $var wire 16 H% UNUSED [15:0] $end
+      $var wire 2 I% ENUM [1:0] $end
+      $var wire 1 B% clk $end
+      $var wire 8 Z" in [7:0] $end
+      $var wire 8 ]" out [7:0] $end
+      $var wire 8 !$ ff [7:0] $end
+      $var wire 8 ]" out4 [7:0] $end
+      $var wire 8 "$ out4_2 [7:0] $end
       $scope module i_sub4_0 $end
-       $var wire 32 F% P0 [31:0] $end
-       $var real 64 G% P1 $end
-       $var real 64 I% P3 $end
-       $var wire 1 >% clk $end
-       $var wire 8 |# in [7:0] $end
-       $var wire 8 [" out [7:0] $end
-       $var wire 8 [" ff [7:0] $end
-       $var wire 128 ~# sub5_in[0][0] [127:0] $end
-       $var wire 128 $$ sub5_in[0][1] [127:0] $end
-       $var wire 128 ($ sub5_in[0][2] [127:0] $end
-       $var wire 128 ,$ sub5_in[1][0] [127:0] $end
-       $var wire 128 0$ sub5_in[1][1] [127:0] $end
-       $var wire 128 4$ sub5_in[1][2] [127:0] $end
-       $var wire 8 8$ sub5_out[0][0] [7:0] $end
-       $var wire 8 9$ sub5_out[0][1] [7:0] $end
-       $var wire 8 :$ sub5_out[0][2] [7:0] $end
-       $var wire 8 ;$ sub5_out[1][0] [7:0] $end
-       $var wire 8 <$ sub5_out[1][1] [7:0] $end
-       $var wire 8 =$ sub5_out[1][2] [7:0] $end
-       $var wire 32 >$ count [31:0] $end
-       $var wire 32 6" driven_from_bind [31:0] $end
+       $var wire 32 J% P0 [31:0] $end
+       $var real 64 K% P1 $end
+       $var real 64 M% P3 $end
+       $var wire 1 B% clk $end
+       $var wire 8 #$ in [7:0] $end
+       $var wire 8 ]" out [7:0] $end
+       $var wire 8 ]" ff [7:0] $end
+       $var wire 128 $$ sub5_in[0][0] [127:0] $end
+       $var wire 128 ($ sub5_in[0][1] [127:0] $end
+       $var wire 128 ,$ sub5_in[0][2] [127:0] $end
+       $var wire 128 0$ sub5_in[1][0] [127:0] $end
+       $var wire 128 4$ sub5_in[1][1] [127:0] $end
+       $var wire 128 8$ sub5_in[1][2] [127:0] $end
+       $var wire 8 <$ sub5_out[0][0] [7:0] $end
+       $var wire 8 =$ sub5_out[0][1] [7:0] $end
+       $var wire 8 >$ sub5_out[0][2] [7:0] $end
+       $var wire 8 ?$ sub5_out[1][0] [7:0] $end
+       $var wire 8 @$ sub5_out[1][1] [7:0] $end
+       $var wire 8 A$ sub5_out[1][2] [7:0] $end
+       $var wire 32 B$ count [31:0] $end
+       $var wire 32 8" driven_from_bind [31:0] $end
        $scope module i_sub4_bound $end
-        $var real 64 G% P1 $end
-        $var wire 32 6" driven_from_bind [31:0] $end
+        $var real 64 K% P1 $end
+        $var wire 32 8" driven_from_bind [31:0] $end
        $upscope $end
        $scope module i_sub5 $end
-        $var wire 1 >% clk $end
-        $var wire 128 ?$ in[0][0] [127:0] $end
-        $var wire 128 C$ in[0][1] [127:0] $end
-        $var wire 128 G$ in[0][2] [127:0] $end
-        $var wire 128 K$ in[1][0] [127:0] $end
-        $var wire 128 O$ in[1][1] [127:0] $end
-        $var wire 128 S$ in[1][2] [127:0] $end
-        $var wire 8 W$ out[0][0] [7:0] $end
-        $var wire 8 X$ out[0][1] [7:0] $end
-        $var wire 8 Y$ out[0][2] [7:0] $end
-        $var wire 8 Z$ out[1][0] [7:0] $end
-        $var wire 8 [$ out[1][1] [7:0] $end
-        $var wire 8 \$ out[1][2] [7:0] $end
-        $var wire 32 ]$ count [31:0] $end
-        $var wire 8 7" val0[0] [7:0] $end
-        $var wire 8 8" val0[1] [7:0] $end
-        $var wire 8 9" val1[0] [7:0] $end
-        $var wire 8 :" val1[1] [7:0] $end
-        $var wire 8 ;" val2[0] [7:0] $end
-        $var wire 8 <" val2[1] [7:0] $end
-        $var wire 8 =" val3[0] [7:0] $end
-        $var wire 8 >" val3[1] [7:0] $end
+        $var wire 1 B% clk $end
+        $var wire 128 C$ in[0][0] [127:0] $end
+        $var wire 128 G$ in[0][1] [127:0] $end
+        $var wire 128 K$ in[0][2] [127:0] $end
+        $var wire 128 O$ in[1][0] [127:0] $end
+        $var wire 128 S$ in[1][1] [127:0] $end
+        $var wire 128 W$ in[1][2] [127:0] $end
+        $var wire 8 [$ out[0][0] [7:0] $end
+        $var wire 8 \$ out[0][1] [7:0] $end
+        $var wire 8 ]$ out[0][2] [7:0] $end
+        $var wire 8 ^$ out[1][0] [7:0] $end
+        $var wire 8 _$ out[1][1] [7:0] $end
+        $var wire 8 `$ out[1][2] [7:0] $end
+        $var wire 32 a$ count [31:0] $end
+        $var wire 8 9" val0[0] [7:0] $end
+        $var wire 8 :" val0[1] [7:0] $end
+        $var wire 8 ;" val1[0] [7:0] $end
+        $var wire 8 <" val1[1] [7:0] $end
+        $var wire 8 =" val2[0] [7:0] $end
+        $var wire 8 >" val2[1] [7:0] $end
+        $var wire 8 ?" val3[0] [7:0] $end
+        $var wire 8 @" val3[1] [7:0] $end
         $scope module i_sub0 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 L% P1 [31:0] $end
-         $var wire 8 ?" out[0] [7:0] $end
-         $var wire 8 @" out[1] [7:0] $end
-        $upscope $end
-        $scope module i_sub1 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 L% P1 [31:0] $end
+         $var wire 32 O% P0 [31:0] $end
+         $var wire 32 P% P1 [31:0] $end
          $var wire 8 A" out[0] [7:0] $end
          $var wire 8 B" out[1] [7:0] $end
         $upscope $end
-        $scope module i_sub2 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 L% P1 [31:0] $end
+        $scope module i_sub1 $end
+         $var wire 32 O% P0 [31:0] $end
+         $var wire 32 P% P1 [31:0] $end
          $var wire 8 C" out[0] [7:0] $end
          $var wire 8 D" out[1] [7:0] $end
         $upscope $end
-        $scope module i_sub3 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 M% P1 [31:0] $end
+        $scope module i_sub2 $end
+         $var wire 32 O% P0 [31:0] $end
+         $var wire 32 P% P1 [31:0] $end
          $var wire 8 E" out[0] [7:0] $end
          $var wire 8 F" out[1] [7:0] $end
         $upscope $end
+        $scope module i_sub3 $end
+         $var wire 32 O% P0 [31:0] $end
+         $var wire 32 Q% P1 [31:0] $end
+         $var wire 8 G" out[0] [7:0] $end
+         $var wire 8 H" out[1] [7:0] $end
+        $upscope $end
        $upscope $end
       $upscope $end
       $scope module i_sub4_1 $end
-       $var wire 32 F% P0 [31:0] $end
-       $var real 64 G% P1 $end
-       $var real 64 N% P3 $end
-       $var wire 1 >% clk $end
-       $var wire 8 |# in [7:0] $end
-       $var wire 8 }# out [7:0] $end
-       $var wire 8 }# ff [7:0] $end
-       $var wire 128 ^$ sub5_in[0][0] [127:0] $end
-       $var wire 128 b$ sub5_in[0][1] [127:0] $end
-       $var wire 128 f$ sub5_in[0][2] [127:0] $end
-       $var wire 128 j$ sub5_in[1][0] [127:0] $end
-       $var wire 128 n$ sub5_in[1][1] [127:0] $end
-       $var wire 128 r$ sub5_in[1][2] [127:0] $end
-       $var wire 8 v$ sub5_out[0][0] [7:0] $end
-       $var wire 8 w$ sub5_out[0][1] [7:0] $end
-       $var wire 8 x$ sub5_out[0][2] [7:0] $end
-       $var wire 8 y$ sub5_out[1][0] [7:0] $end
-       $var wire 8 z$ sub5_out[1][1] [7:0] $end
-       $var wire 8 {$ sub5_out[1][2] [7:0] $end
-       $var wire 32 |$ count [31:0] $end
-       $var wire 32 G" driven_from_bind [31:0] $end
+       $var wire 32 J% P0 [31:0] $end
+       $var real 64 K% P1 $end
+       $var real 64 R% P3 $end
+       $var wire 1 B% clk $end
+       $var wire 8 #$ in [7:0] $end
+       $var wire 8 "$ out [7:0] $end
+       $var wire 8 "$ ff [7:0] $end
+       $var wire 128 b$ sub5_in[0][0] [127:0] $end
+       $var wire 128 f$ sub5_in[0][1] [127:0] $end
+       $var wire 128 j$ sub5_in[0][2] [127:0] $end
+       $var wire 128 n$ sub5_in[1][0] [127:0] $end
+       $var wire 128 r$ sub5_in[1][1] [127:0] $end
+       $var wire 128 v$ sub5_in[1][2] [127:0] $end
+       $var wire 8 z$ sub5_out[0][0] [7:0] $end
+       $var wire 8 {$ sub5_out[0][1] [7:0] $end
+       $var wire 8 |$ sub5_out[0][2] [7:0] $end
+       $var wire 8 }$ sub5_out[1][0] [7:0] $end
+       $var wire 8 ~$ sub5_out[1][1] [7:0] $end
+       $var wire 8 !% sub5_out[1][2] [7:0] $end
+       $var wire 32 "% count [31:0] $end
+       $var wire 32 I" driven_from_bind [31:0] $end
        $scope module i_sub4_bound $end
-        $var real 64 G% P1 $end
-        $var wire 32 G" driven_from_bind [31:0] $end
+        $var real 64 K% P1 $end
+        $var wire 32 I" driven_from_bind [31:0] $end
        $upscope $end
        $scope module i_sub5 $end
-        $var wire 1 >% clk $end
-        $var wire 128 }$ in[0][0] [127:0] $end
-        $var wire 128 #% in[0][1] [127:0] $end
-        $var wire 128 '% in[0][2] [127:0] $end
-        $var wire 128 +% in[1][0] [127:0] $end
-        $var wire 128 /% in[1][1] [127:0] $end
-        $var wire 128 3% in[1][2] [127:0] $end
-        $var wire 8 7% out[0][0] [7:0] $end
-        $var wire 8 8% out[0][1] [7:0] $end
-        $var wire 8 9% out[0][2] [7:0] $end
-        $var wire 8 :% out[1][0] [7:0] $end
-        $var wire 8 ;% out[1][1] [7:0] $end
-        $var wire 8 <% out[1][2] [7:0] $end
-        $var wire 32 =% count [31:0] $end
-        $var wire 8 H" val0[0] [7:0] $end
-        $var wire 8 I" val0[1] [7:0] $end
-        $var wire 8 J" val1[0] [7:0] $end
-        $var wire 8 K" val1[1] [7:0] $end
-        $var wire 8 L" val2[0] [7:0] $end
-        $var wire 8 M" val2[1] [7:0] $end
-        $var wire 8 N" val3[0] [7:0] $end
-        $var wire 8 O" val3[1] [7:0] $end
+        $var wire 1 B% clk $end
+        $var wire 128 #% in[0][0] [127:0] $end
+        $var wire 128 '% in[0][1] [127:0] $end
+        $var wire 128 +% in[0][2] [127:0] $end
+        $var wire 128 /% in[1][0] [127:0] $end
+        $var wire 128 3% in[1][1] [127:0] $end
+        $var wire 128 7% in[1][2] [127:0] $end
+        $var wire 8 ;% out[0][0] [7:0] $end
+        $var wire 8 <% out[0][1] [7:0] $end
+        $var wire 8 =% out[0][2] [7:0] $end
+        $var wire 8 >% out[1][0] [7:0] $end
+        $var wire 8 ?% out[1][1] [7:0] $end
+        $var wire 8 @% out[1][2] [7:0] $end
+        $var wire 32 A% count [31:0] $end
+        $var wire 8 J" val0[0] [7:0] $end
+        $var wire 8 K" val0[1] [7:0] $end
+        $var wire 8 L" val1[0] [7:0] $end
+        $var wire 8 M" val1[1] [7:0] $end
+        $var wire 8 N" val2[0] [7:0] $end
+        $var wire 8 O" val2[1] [7:0] $end
+        $var wire 8 P" val3[0] [7:0] $end
+        $var wire 8 Q" val3[1] [7:0] $end
         $scope module i_sub0 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 L% P1 [31:0] $end
-         $var wire 8 P" out[0] [7:0] $end
-         $var wire 8 Q" out[1] [7:0] $end
-        $upscope $end
-        $scope module i_sub1 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 L% P1 [31:0] $end
+         $var wire 32 O% P0 [31:0] $end
+         $var wire 32 P% P1 [31:0] $end
          $var wire 8 R" out[0] [7:0] $end
          $var wire 8 S" out[1] [7:0] $end
         $upscope $end
-        $scope module i_sub2 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 L% P1 [31:0] $end
+        $scope module i_sub1 $end
+         $var wire 32 O% P0 [31:0] $end
+         $var wire 32 P% P1 [31:0] $end
          $var wire 8 T" out[0] [7:0] $end
          $var wire 8 U" out[1] [7:0] $end
         $upscope $end
-        $scope module i_sub3 $end
-         $var wire 32 K% P0 [31:0] $end
-         $var wire 32 M% P1 [31:0] $end
+        $scope module i_sub2 $end
+         $var wire 32 O% P0 [31:0] $end
+         $var wire 32 P% P1 [31:0] $end
          $var wire 8 V" out[0] [7:0] $end
          $var wire 8 W" out[1] [7:0] $end
         $upscope $end
+        $scope module i_sub3 $end
+         $var wire 32 O% P0 [31:0] $end
+         $var wire 32 Q% P1 [31:0] $end
+         $var wire 8 X" out[0] [7:0] $end
+         $var wire 8 Y" out[1] [7:0] $end
+        $upscope $end
        $upscope $end
       $upscope $end
      $upscope $end
      $scope module in $end
-      $var wire 1 >% clk $end
-      $var wire 8 X" data [7:0] $end
+      $var wire 1 B% clk $end
+      $var wire 8 Z" data [7:0] $end
      $upscope $end
      $scope module out $end
-      $var wire 1 >% clk $end
-      $var wire 8 Z" data [7:0] $end
+      $var wire 1 B% clk $end
+      $var wire 8 \" data [7:0] $end
      $upscope $end
     $upscope $end
     $scope module in_ifs $end
-     $var wire 1 >% clk $end
-     $var wire 8 X" data [7:0] $end
+     $var wire 1 B% clk $end
+     $var wire 8 Z" data [7:0] $end
     $upscope $end
     $scope module out_ifs $end
-     $var wire 1 >% clk $end
-     $var wire 8 Z" data [7:0] $end
+     $var wire 1 B% clk $end
+     $var wire 8 \" data [7:0] $end
     $upscope $end
    $upscope $end
    $scope module i_sub3 $end
-    $var wire 8 Z! P0 [7:0] $end
-    $var wire 32 [! UNPACKED_ARRAY[0] [31:0] $end
-    $var wire 32 \! UNPACKED_ARRAY[1] [31:0] $end
-    $var wire 16 ]! UNUSED [15:0] $end
-    $var wire 2 ^! ENUM [1:0] $end
-    $var wire 1 Q! clk $end
-    $var wire 8 8! in [7:0] $end
-    $var wire 8 R! out [7:0] $end
-    $var wire 8 S! ff [7:0] $end
-    $var wire 8 R! out4 [7:0] $end
+    $var wire 8 \! P0 [7:0] $end
+    $var wire 32 ]! UNPACKED_ARRAY[0] [31:0] $end
+    $var wire 32 ^! UNPACKED_ARRAY[1] [31:0] $end
+    $var wire 16 _! UNUSED [15:0] $end
+    $var wire 2 `! ENUM [1:0] $end
+    $var wire 1 U! clk $end
+    $var wire 8 <! in [7:0] $end
+    $var wire 8 7! out [7:0] $end
+    $var wire 8 8! ff [7:0] $end
+    $var wire 8 7! out4 [7:0] $end
     $var wire 8 - out4_2 [7:0] $end
     $scope module i_sub4_0 $end
-     $var wire 32 _! P0 [31:0] $end
-     $var real 64 `! P1 $end
-     $var real 64 b! P3 $end
-     $var wire 1 Q! clk $end
-     $var wire 8 S! in [7:0] $end
-     $var wire 8 R! out [7:0] $end
-     $var wire 8 R! ff [7:0] $end
+     $var wire 32 a! P0 [31:0] $end
+     $var real 64 b! P1 $end
+     $var real 64 d! P3 $end
+     $var wire 1 U! clk $end
+     $var wire 8 9! in [7:0] $end
+     $var wire 8 7! out [7:0] $end
+     $var wire 8 7! ff [7:0] $end
      $var wire 128 . sub5_in[0][0] [127:0] $end
      $var wire 128 2 sub5_in[0][1] [127:0] $end
      $var wire 128 6 sub5_in[0][2] [127:0] $end
      $var wire 128 : sub5_in[1][0] [127:0] $end
      $var wire 128 > sub5_in[1][1] [127:0] $end
      $var wire 128 B sub5_in[1][2] [127:0] $end
-     $var wire 8 9! sub5_out[0][0] [7:0] $end
-     $var wire 8 :! sub5_out[0][1] [7:0] $end
-     $var wire 8 ;! sub5_out[0][2] [7:0] $end
-     $var wire 8 <! sub5_out[1][0] [7:0] $end
-     $var wire 8 =! sub5_out[1][1] [7:0] $end
-     $var wire 8 >! sub5_out[1][2] [7:0] $end
+     $var wire 8 =! sub5_out[0][0] [7:0] $end
+     $var wire 8 >! sub5_out[0][1] [7:0] $end
+     $var wire 8 ?! sub5_out[0][2] [7:0] $end
+     $var wire 8 @! sub5_out[1][0] [7:0] $end
+     $var wire 8 A! sub5_out[1][1] [7:0] $end
+     $var wire 8 B! sub5_out[1][2] [7:0] $end
      $var wire 32 F count [31:0] $end
      $var wire 32 " driven_from_bind [31:0] $end
      $scope module i_sub4_bound $end
-      $var real 64 `! P1 $end
+      $var real 64 b! P1 $end
       $var wire 32 " driven_from_bind [31:0] $end
      $upscope $end
      $scope module i_sub5 $end
-      $var wire 1 #& clk $end
-      $var wire 128 b% in[0][0] [127:0] $end
-      $var wire 128 f% in[0][1] [127:0] $end
-      $var wire 128 j% in[0][2] [127:0] $end
-      $var wire 128 n% in[1][0] [127:0] $end
-      $var wire 128 r% in[1][1] [127:0] $end
-      $var wire 128 v% in[1][2] [127:0] $end
-      $var wire 8 z% out[0][0] [7:0] $end
-      $var wire 8 {% out[0][1] [7:0] $end
-      $var wire 8 |% out[0][2] [7:0] $end
-      $var wire 8 }% out[1][0] [7:0] $end
-      $var wire 8 ~% out[1][1] [7:0] $end
-      $var wire 8 !& out[1][2] [7:0] $end
-      $var wire 32 "& count [31:0] $end
-      $var wire 8 R% val0[0] [7:0] $end
-      $var wire 8 S% val0[1] [7:0] $end
-      $var wire 8 T% val1[0] [7:0] $end
-      $var wire 8 U% val1[1] [7:0] $end
-      $var wire 8 V% val2[0] [7:0] $end
-      $var wire 8 W% val2[1] [7:0] $end
-      $var wire 8 X% val3[0] [7:0] $end
-      $var wire 8 Y% val3[1] [7:0] $end
+      $var wire 1 '& clk $end
+      $var wire 128 f% in[0][0] [127:0] $end
+      $var wire 128 j% in[0][1] [127:0] $end
+      $var wire 128 n% in[0][2] [127:0] $end
+      $var wire 128 r% in[1][0] [127:0] $end
+      $var wire 128 v% in[1][1] [127:0] $end
+      $var wire 128 z% in[1][2] [127:0] $end
+      $var wire 8 ~% out[0][0] [7:0] $end
+      $var wire 8 !& out[0][1] [7:0] $end
+      $var wire 8 "& out[0][2] [7:0] $end
+      $var wire 8 #& out[1][0] [7:0] $end
+      $var wire 8 $& out[1][1] [7:0] $end
+      $var wire 8 %& out[1][2] [7:0] $end
+      $var wire 32 && count [31:0] $end
+      $var wire 8 V% val0[0] [7:0] $end
+      $var wire 8 W% val0[1] [7:0] $end
+      $var wire 8 X% val1[0] [7:0] $end
+      $var wire 8 Y% val1[1] [7:0] $end
+      $var wire 8 Z% val2[0] [7:0] $end
+      $var wire 8 [% val2[1] [7:0] $end
+      $var wire 8 \% val3[0] [7:0] $end
+      $var wire 8 ]% val3[1] [7:0] $end
       $scope module i_sub0 $end
-       $var wire 32 $& P0 [31:0] $end
-       $var wire 32 %& P1 [31:0] $end
-       $var wire 8 Z% out[0] [7:0] $end
-       $var wire 8 [% out[1] [7:0] $end
-      $upscope $end
-      $scope module i_sub1 $end
-       $var wire 32 $& P0 [31:0] $end
-       $var wire 32 %& P1 [31:0] $end
-       $var wire 8 \% out[0] [7:0] $end
-       $var wire 8 ]% out[1] [7:0] $end
-      $upscope $end
-      $scope module i_sub2 $end
-       $var wire 32 $& P0 [31:0] $end
-       $var wire 32 %& P1 [31:0] $end
+       $var wire 32 (& P0 [31:0] $end
+       $var wire 32 )& P1 [31:0] $end
        $var wire 8 ^% out[0] [7:0] $end
        $var wire 8 _% out[1] [7:0] $end
       $upscope $end
-      $scope module i_sub3 $end
-       $var wire 32 $& P0 [31:0] $end
-       $var wire 32 && P1 [31:0] $end
+      $scope module i_sub1 $end
+       $var wire 32 (& P0 [31:0] $end
+       $var wire 32 )& P1 [31:0] $end
        $var wire 8 `% out[0] [7:0] $end
        $var wire 8 a% out[1] [7:0] $end
       $upscope $end
+      $scope module i_sub2 $end
+       $var wire 32 (& P0 [31:0] $end
+       $var wire 32 )& P1 [31:0] $end
+       $var wire 8 b% out[0] [7:0] $end
+       $var wire 8 c% out[1] [7:0] $end
+      $upscope $end
+      $scope module i_sub3 $end
+       $var wire 32 (& P0 [31:0] $end
+       $var wire 32 *& P1 [31:0] $end
+       $var wire 8 d% out[0] [7:0] $end
+       $var wire 8 e% out[1] [7:0] $end
+      $upscope $end
      $upscope $end
     $upscope $end
     $scope module i_sub4_1 $end
-     $var wire 32 _! P0 [31:0] $end
-     $var real 64 `! P1 $end
-     $var real 64 d! P3 $end
-     $var wire 1 Q! clk $end
-     $var wire 8 S! in [7:0] $end
+     $var wire 32 a! P0 [31:0] $end
+     $var real 64 b! P1 $end
+     $var real 64 f! P3 $end
+     $var wire 1 U! clk $end
+     $var wire 8 9! in [7:0] $end
      $var wire 8 - out [7:0] $end
      $var wire 8 - ff [7:0] $end
      $var wire 128 G sub5_in[0][0] [127:0] $end
@@ -535,228 +535,228 @@ $timescale 1ps $end
      $var wire 128 S sub5_in[1][0] [127:0] $end
      $var wire 128 W sub5_in[1][1] [127:0] $end
      $var wire 128 [ sub5_in[1][2] [127:0] $end
-     $var wire 8 ?! sub5_out[0][0] [7:0] $end
-     $var wire 8 @! sub5_out[0][1] [7:0] $end
-     $var wire 8 A! sub5_out[0][2] [7:0] $end
-     $var wire 8 B! sub5_out[1][0] [7:0] $end
-     $var wire 8 C! sub5_out[1][1] [7:0] $end
-     $var wire 8 D! sub5_out[1][2] [7:0] $end
+     $var wire 8 C! sub5_out[0][0] [7:0] $end
+     $var wire 8 D! sub5_out[0][1] [7:0] $end
+     $var wire 8 E! sub5_out[0][2] [7:0] $end
+     $var wire 8 F! sub5_out[1][0] [7:0] $end
+     $var wire 8 G! sub5_out[1][1] [7:0] $end
+     $var wire 8 H! sub5_out[1][2] [7:0] $end
      $var wire 32 _ count [31:0] $end
      $var wire 32 # driven_from_bind [31:0] $end
      $scope module i_sub4_bound $end
-      $var real 64 `! P1 $end
+      $var real 64 b! P1 $end
       $var wire 32 # driven_from_bind [31:0] $end
      $upscope $end
      $scope module i_sub5 $end
-      $var wire 1 V& clk $end
-      $var wire 128 7& in[0][0] [127:0] $end
-      $var wire 128 ;& in[0][1] [127:0] $end
-      $var wire 128 ?& in[0][2] [127:0] $end
-      $var wire 128 C& in[1][0] [127:0] $end
-      $var wire 128 G& in[1][1] [127:0] $end
-      $var wire 128 K& in[1][2] [127:0] $end
-      $var wire 8 O& out[0][0] [7:0] $end
-      $var wire 8 P& out[0][1] [7:0] $end
-      $var wire 8 Q& out[0][2] [7:0] $end
-      $var wire 8 R& out[1][0] [7:0] $end
-      $var wire 8 S& out[1][1] [7:0] $end
-      $var wire 8 T& out[1][2] [7:0] $end
-      $var wire 32 U& count [31:0] $end
-      $var wire 8 '& val0[0] [7:0] $end
-      $var wire 8 (& val0[1] [7:0] $end
-      $var wire 8 )& val1[0] [7:0] $end
-      $var wire 8 *& val1[1] [7:0] $end
-      $var wire 8 +& val2[0] [7:0] $end
-      $var wire 8 ,& val2[1] [7:0] $end
-      $var wire 8 -& val3[0] [7:0] $end
-      $var wire 8 .& val3[1] [7:0] $end
+      $var wire 1 Z& clk $end
+      $var wire 128 ;& in[0][0] [127:0] $end
+      $var wire 128 ?& in[0][1] [127:0] $end
+      $var wire 128 C& in[0][2] [127:0] $end
+      $var wire 128 G& in[1][0] [127:0] $end
+      $var wire 128 K& in[1][1] [127:0] $end
+      $var wire 128 O& in[1][2] [127:0] $end
+      $var wire 8 S& out[0][0] [7:0] $end
+      $var wire 8 T& out[0][1] [7:0] $end
+      $var wire 8 U& out[0][2] [7:0] $end
+      $var wire 8 V& out[1][0] [7:0] $end
+      $var wire 8 W& out[1][1] [7:0] $end
+      $var wire 8 X& out[1][2] [7:0] $end
+      $var wire 32 Y& count [31:0] $end
+      $var wire 8 +& val0[0] [7:0] $end
+      $var wire 8 ,& val0[1] [7:0] $end
+      $var wire 8 -& val1[0] [7:0] $end
+      $var wire 8 .& val1[1] [7:0] $end
+      $var wire 8 /& val2[0] [7:0] $end
+      $var wire 8 0& val2[1] [7:0] $end
+      $var wire 8 1& val3[0] [7:0] $end
+      $var wire 8 2& val3[1] [7:0] $end
       $scope module i_sub0 $end
-       $var wire 32 W& P0 [31:0] $end
-       $var wire 32 X& P1 [31:0] $end
-       $var wire 8 /& out[0] [7:0] $end
-       $var wire 8 0& out[1] [7:0] $end
-      $upscope $end
-      $scope module i_sub1 $end
-       $var wire 32 W& P0 [31:0] $end
-       $var wire 32 X& P1 [31:0] $end
-       $var wire 8 1& out[0] [7:0] $end
-       $var wire 8 2& out[1] [7:0] $end
-      $upscope $end
-      $scope module i_sub2 $end
-       $var wire 32 W& P0 [31:0] $end
-       $var wire 32 X& P1 [31:0] $end
+       $var wire 32 [& P0 [31:0] $end
+       $var wire 32 \& P1 [31:0] $end
        $var wire 8 3& out[0] [7:0] $end
        $var wire 8 4& out[1] [7:0] $end
       $upscope $end
-      $scope module i_sub3 $end
-       $var wire 32 W& P0 [31:0] $end
-       $var wire 32 Y& P1 [31:0] $end
+      $scope module i_sub1 $end
+       $var wire 32 [& P0 [31:0] $end
+       $var wire 32 \& P1 [31:0] $end
        $var wire 8 5& out[0] [7:0] $end
        $var wire 8 6& out[1] [7:0] $end
       $upscope $end
+      $scope module i_sub2 $end
+       $var wire 32 [& P0 [31:0] $end
+       $var wire 32 \& P1 [31:0] $end
+       $var wire 8 7& out[0] [7:0] $end
+       $var wire 8 8& out[1] [7:0] $end
+      $upscope $end
+      $scope module i_sub3 $end
+       $var wire 32 [& P0 [31:0] $end
+       $var wire 32 ]& P1 [31:0] $end
+       $var wire 8 9& out[0] [7:0] $end
+       $var wire 8 :& out[1] [7:0] $end
+      $upscope $end
      $upscope $end
     $upscope $end
    $upscope $end
    $scope module i_sub3_2 $end
-    $var wire 8 Z! P0 [7:0] $end
-    $var wire 32 f! UNPACKED_ARRAY[0] [31:0] $end
-    $var wire 32 g! UNPACKED_ARRAY[1] [31:0] $end
-    $var wire 16 ]! UNUSED [15:0] $end
-    $var wire 2 ^! ENUM [1:0] $end
-    $var wire 1 Q! clk $end
-    $var wire 8 8! in [7:0] $end
+    $var wire 8 \! P0 [7:0] $end
+    $var wire 32 h! UNPACKED_ARRAY[0] [31:0] $end
+    $var wire 32 i! UNPACKED_ARRAY[1] [31:0] $end
+    $var wire 16 _! UNUSED [15:0] $end
+    $var wire 2 `! ENUM [1:0] $end
+    $var wire 1 U! clk $end
+    $var wire 8 <! in [7:0] $end
     $var wire 8 & out [7:0] $end
     $var wire 8 ` ff [7:0] $end
     $var wire 8 & out4 [7:0] $end
     $var wire 8 a out4_2 [7:0] $end
     $scope module i_sub4_0 $end
-     $var wire 32 _! P0 [31:0] $end
-     $var real 64 `! P1 $end
-     $var real 64 b! P3 $end
-     $var wire 1 Q! clk $end
-     $var wire 8 ` in [7:0] $end
+     $var wire 32 a! P0 [31:0] $end
+     $var real 64 b! P1 $end
+     $var real 64 d! P3 $end
+     $var wire 1 U! clk $end
+     $var wire 8 b in [7:0] $end
      $var wire 8 & out [7:0] $end
      $var wire 8 & ff [7:0] $end
-     $var wire 128 b sub5_in[0][0] [127:0] $end
-     $var wire 128 f sub5_in[0][1] [127:0] $end
-     $var wire 128 j sub5_in[0][2] [127:0] $end
-     $var wire 128 n sub5_in[1][0] [127:0] $end
-     $var wire 128 r sub5_in[1][1] [127:0] $end
-     $var wire 128 v sub5_in[1][2] [127:0] $end
-     $var wire 8 E! sub5_out[0][0] [7:0] $end
-     $var wire 8 F! sub5_out[0][1] [7:0] $end
-     $var wire 8 G! sub5_out[0][2] [7:0] $end
-     $var wire 8 H! sub5_out[1][0] [7:0] $end
-     $var wire 8 I! sub5_out[1][1] [7:0] $end
-     $var wire 8 J! sub5_out[1][2] [7:0] $end
-     $var wire 32 z count [31:0] $end
+     $var wire 128 c sub5_in[0][0] [127:0] $end
+     $var wire 128 g sub5_in[0][1] [127:0] $end
+     $var wire 128 k sub5_in[0][2] [127:0] $end
+     $var wire 128 o sub5_in[1][0] [127:0] $end
+     $var wire 128 s sub5_in[1][1] [127:0] $end
+     $var wire 128 w sub5_in[1][2] [127:0] $end
+     $var wire 8 I! sub5_out[0][0] [7:0] $end
+     $var wire 8 J! sub5_out[0][1] [7:0] $end
+     $var wire 8 K! sub5_out[0][2] [7:0] $end
+     $var wire 8 L! sub5_out[1][0] [7:0] $end
+     $var wire 8 M! sub5_out[1][1] [7:0] $end
+     $var wire 8 N! sub5_out[1][2] [7:0] $end
+     $var wire 32 { count [31:0] $end
      $var wire 32 $ driven_from_bind [31:0] $end
      $scope module i_sub4_bound $end
-      $var real 64 `! P1 $end
+      $var real 64 b! P1 $end
       $var wire 32 $ driven_from_bind [31:0] $end
      $upscope $end
      $scope module i_sub5 $end
-      $var wire 1 +' clk $end
-      $var wire 128 j& in[0][0] [127:0] $end
-      $var wire 128 n& in[0][1] [127:0] $end
-      $var wire 128 r& in[0][2] [127:0] $end
-      $var wire 128 v& in[1][0] [127:0] $end
-      $var wire 128 z& in[1][1] [127:0] $end
-      $var wire 128 ~& in[1][2] [127:0] $end
-      $var wire 8 $' out[0][0] [7:0] $end
-      $var wire 8 %' out[0][1] [7:0] $end
-      $var wire 8 &' out[0][2] [7:0] $end
-      $var wire 8 '' out[1][0] [7:0] $end
-      $var wire 8 (' out[1][1] [7:0] $end
-      $var wire 8 )' out[1][2] [7:0] $end
-      $var wire 32 *' count [31:0] $end
-      $var wire 8 Z& val0[0] [7:0] $end
-      $var wire 8 [& val0[1] [7:0] $end
-      $var wire 8 \& val1[0] [7:0] $end
-      $var wire 8 ]& val1[1] [7:0] $end
-      $var wire 8 ^& val2[0] [7:0] $end
-      $var wire 8 _& val2[1] [7:0] $end
-      $var wire 8 `& val3[0] [7:0] $end
-      $var wire 8 a& val3[1] [7:0] $end
+      $var wire 1 /' clk $end
+      $var wire 128 n& in[0][0] [127:0] $end
+      $var wire 128 r& in[0][1] [127:0] $end
+      $var wire 128 v& in[0][2] [127:0] $end
+      $var wire 128 z& in[1][0] [127:0] $end
+      $var wire 128 ~& in[1][1] [127:0] $end
+      $var wire 128 $' in[1][2] [127:0] $end
+      $var wire 8 (' out[0][0] [7:0] $end
+      $var wire 8 )' out[0][1] [7:0] $end
+      $var wire 8 *' out[0][2] [7:0] $end
+      $var wire 8 +' out[1][0] [7:0] $end
+      $var wire 8 ,' out[1][1] [7:0] $end
+      $var wire 8 -' out[1][2] [7:0] $end
+      $var wire 32 .' count [31:0] $end
+      $var wire 8 ^& val0[0] [7:0] $end
+      $var wire 8 _& val0[1] [7:0] $end
+      $var wire 8 `& val1[0] [7:0] $end
+      $var wire 8 a& val1[1] [7:0] $end
+      $var wire 8 b& val2[0] [7:0] $end
+      $var wire 8 c& val2[1] [7:0] $end
+      $var wire 8 d& val3[0] [7:0] $end
+      $var wire 8 e& val3[1] [7:0] $end
       $scope module i_sub0 $end
-       $var wire 32 ,' P0 [31:0] $end
-       $var wire 32 -' P1 [31:0] $end
-       $var wire 8 b& out[0] [7:0] $end
-       $var wire 8 c& out[1] [7:0] $end
-      $upscope $end
-      $scope module i_sub1 $end
-       $var wire 32 ,' P0 [31:0] $end
-       $var wire 32 -' P1 [31:0] $end
-       $var wire 8 d& out[0] [7:0] $end
-       $var wire 8 e& out[1] [7:0] $end
-      $upscope $end
-      $scope module i_sub2 $end
-       $var wire 32 ,' P0 [31:0] $end
-       $var wire 32 -' P1 [31:0] $end
+       $var wire 32 0' P0 [31:0] $end
+       $var wire 32 1' P1 [31:0] $end
        $var wire 8 f& out[0] [7:0] $end
        $var wire 8 g& out[1] [7:0] $end
       $upscope $end
-      $scope module i_sub3 $end
-       $var wire 32 ,' P0 [31:0] $end
-       $var wire 32 .' P1 [31:0] $end
+      $scope module i_sub1 $end
+       $var wire 32 0' P0 [31:0] $end
+       $var wire 32 1' P1 [31:0] $end
        $var wire 8 h& out[0] [7:0] $end
        $var wire 8 i& out[1] [7:0] $end
       $upscope $end
+      $scope module i_sub2 $end
+       $var wire 32 0' P0 [31:0] $end
+       $var wire 32 1' P1 [31:0] $end
+       $var wire 8 j& out[0] [7:0] $end
+       $var wire 8 k& out[1] [7:0] $end
+      $upscope $end
+      $scope module i_sub3 $end
+       $var wire 32 0' P0 [31:0] $end
+       $var wire 32 2' P1 [31:0] $end
+       $var wire 8 l& out[0] [7:0] $end
+       $var wire 8 m& out[1] [7:0] $end
+      $upscope $end
      $upscope $end
     $upscope $end
     $scope module i_sub4_1 $end
-     $var wire 32 _! P0 [31:0] $end
-     $var real 64 `! P1 $end
-     $var real 64 d! P3 $end
-     $var wire 1 Q! clk $end
-     $var wire 8 ` in [7:0] $end
+     $var wire 32 a! P0 [31:0] $end
+     $var real 64 b! P1 $end
+     $var real 64 f! P3 $end
+     $var wire 1 U! clk $end
+     $var wire 8 b in [7:0] $end
      $var wire 8 a out [7:0] $end
      $var wire 8 a ff [7:0] $end
-     $var wire 128 { sub5_in[0][0] [127:0] $end
-     $var wire 128 !! sub5_in[0][1] [127:0] $end
-     $var wire 128 %! sub5_in[0][2] [127:0] $end
-     $var wire 128 )! sub5_in[1][0] [127:0] $end
-     $var wire 128 -! sub5_in[1][1] [127:0] $end
-     $var wire 128 1! sub5_in[1][2] [127:0] $end
-     $var wire 8 K! sub5_out[0][0] [7:0] $end
-     $var wire 8 L! sub5_out[0][1] [7:0] $end
-     $var wire 8 M! sub5_out[0][2] [7:0] $end
-     $var wire 8 N! sub5_out[1][0] [7:0] $end
-     $var wire 8 O! sub5_out[1][1] [7:0] $end
-     $var wire 8 P! sub5_out[1][2] [7:0] $end
-     $var wire 32 5! count [31:0] $end
+     $var wire 128 | sub5_in[0][0] [127:0] $end
+     $var wire 128 "! sub5_in[0][1] [127:0] $end
+     $var wire 128 &! sub5_in[0][2] [127:0] $end
+     $var wire 128 *! sub5_in[1][0] [127:0] $end
+     $var wire 128 .! sub5_in[1][1] [127:0] $end
+     $var wire 128 2! sub5_in[1][2] [127:0] $end
+     $var wire 8 O! sub5_out[0][0] [7:0] $end
+     $var wire 8 P! sub5_out[0][1] [7:0] $end
+     $var wire 8 Q! sub5_out[0][2] [7:0] $end
+     $var wire 8 R! sub5_out[1][0] [7:0] $end
+     $var wire 8 S! sub5_out[1][1] [7:0] $end
+     $var wire 8 T! sub5_out[1][2] [7:0] $end
+     $var wire 32 6! count [31:0] $end
      $var wire 32 % driven_from_bind [31:0] $end
      $scope module i_sub4_bound $end
-      $var real 64 `! P1 $end
+      $var real 64 b! P1 $end
       $var wire 32 % driven_from_bind [31:0] $end
      $upscope $end
      $scope module i_sub5 $end
-      $var wire 1 ^' clk $end
-      $var wire 128 ?' in[0][0] [127:0] $end
-      $var wire 128 C' in[0][1] [127:0] $end
-      $var wire 128 G' in[0][2] [127:0] $end
-      $var wire 128 K' in[1][0] [127:0] $end
-      $var wire 128 O' in[1][1] [127:0] $end
-      $var wire 128 S' in[1][2] [127:0] $end
-      $var wire 8 W' out[0][0] [7:0] $end
-      $var wire 8 X' out[0][1] [7:0] $end
-      $var wire 8 Y' out[0][2] [7:0] $end
-      $var wire 8 Z' out[1][0] [7:0] $end
-      $var wire 8 [' out[1][1] [7:0] $end
-      $var wire 8 \' out[1][2] [7:0] $end
-      $var wire 32 ]' count [31:0] $end
-      $var wire 8 /' val0[0] [7:0] $end
-      $var wire 8 0' val0[1] [7:0] $end
-      $var wire 8 1' val1[0] [7:0] $end
-      $var wire 8 2' val1[1] [7:0] $end
-      $var wire 8 3' val2[0] [7:0] $end
-      $var wire 8 4' val2[1] [7:0] $end
-      $var wire 8 5' val3[0] [7:0] $end
-      $var wire 8 6' val3[1] [7:0] $end
+      $var wire 1 b' clk $end
+      $var wire 128 C' in[0][0] [127:0] $end
+      $var wire 128 G' in[0][1] [127:0] $end
+      $var wire 128 K' in[0][2] [127:0] $end
+      $var wire 128 O' in[1][0] [127:0] $end
+      $var wire 128 S' in[1][1] [127:0] $end
+      $var wire 128 W' in[1][2] [127:0] $end
+      $var wire 8 [' out[0][0] [7:0] $end
+      $var wire 8 \' out[0][1] [7:0] $end
+      $var wire 8 ]' out[0][2] [7:0] $end
+      $var wire 8 ^' out[1][0] [7:0] $end
+      $var wire 8 _' out[1][1] [7:0] $end
+      $var wire 8 `' out[1][2] [7:0] $end
+      $var wire 32 a' count [31:0] $end
+      $var wire 8 3' val0[0] [7:0] $end
+      $var wire 8 4' val0[1] [7:0] $end
+      $var wire 8 5' val1[0] [7:0] $end
+      $var wire 8 6' val1[1] [7:0] $end
+      $var wire 8 7' val2[0] [7:0] $end
+      $var wire 8 8' val2[1] [7:0] $end
+      $var wire 8 9' val3[0] [7:0] $end
+      $var wire 8 :' val3[1] [7:0] $end
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+       $var wire 32 c' P0 [31:0] $end
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+       $var wire 32 d' P1 [31:0] $end
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+       $var wire 8 @' out[1] [7:0] $end
+      $upscope $end
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+       $var wire 32 e' P1 [31:0] $end
+       $var wire 8 A' out[0] [7:0] $end
+       $var wire 8 B' out[1] [7:0] $end
+      $upscope $end
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 #174
diff --git a/test_regress/t/t_trace_hier_block_notop_cc_fst.out b/test_regress/t/t_trace_hier_block_notop_cc_fst.out
index f81a91844..f45b848cb 100644
--- a/test_regress/t/t_trace_hier_block_notop_cc_fst.out
+++ b/test_regress/t/t_trace_hier_block_notop_cc_fst.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 14 09:17:05 2026
+Tue Apr 14 17:15:24 2026
 
 $end
 $version
@@ -127,44 +127,44 @@ $attrbegin misc 07 $unit::enum_t 4 enum_val_0 enum_val_1 enum_val_2 enum_val_3 0
       $var real_parameter 64 L P1 $end
       $var real_parameter 64 M P3 $end
       $var wire 1 = clk $end
-      $var wire 8 I in [7:0] $end
+      $var wire 8 N in [7:0] $end
       $var wire 8 B out [7:0] $end
       $var logic 8 B ff [7:0] $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array sub5_in $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [0] $end
-        $var logic 128 N sub5_in[0][0] [127:0] $end
-        $var logic 128 O sub5_in[0][1] [127:0] $end
-        $var logic 128 P sub5_in[0][2] [127:0] $end
+        $var logic 128 O sub5_in[0][0] [127:0] $end
+        $var logic 128 P sub5_in[0][1] [127:0] $end
+        $var logic 128 Q sub5_in[0][2] [127:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [1] $end
-        $var logic 128 Q sub5_in[1][0] [127:0] $end
-        $var logic 128 R sub5_in[1][1] [127:0] $end
-        $var logic 128 S sub5_in[1][2] [127:0] $end
+        $var logic 128 R sub5_in[1][0] [127:0] $end
+        $var logic 128 S sub5_in[1][1] [127:0] $end
+        $var logic 128 T sub5_in[1][2] [127:0] $end
        $upscope $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array sub5_out $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [0] $end
-        $var wire 8 T sub5_out[0][0] [7:0] $end
-        $var wire 8 U sub5_out[0][1] [7:0] $end
-        $var wire 8 V sub5_out[0][2] [7:0] $end
+        $var wire 8 U sub5_out[0][0] [7:0] $end
+        $var wire 8 V sub5_out[0][1] [7:0] $end
+        $var wire 8 W sub5_out[0][2] [7:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [1] $end
-        $var wire 8 W sub5_out[1][0] [7:0] $end
-        $var wire 8 X sub5_out[1][1] [7:0] $end
-        $var wire 8 Y sub5_out[1][2] [7:0] $end
+        $var wire 8 X sub5_out[1][0] [7:0] $end
+        $var wire 8 Y sub5_out[1][1] [7:0] $end
+        $var wire 8 Z sub5_out[1][2] [7:0] $end
        $upscope $end
       $upscope $end
-      $var int 32 Z count [31:0] $end
-      $var int 32 [ driven_from_bind [31:0] $end
+      $var int 32 [ count [31:0] $end
+      $var int 32 \ driven_from_bind [31:0] $end
       $scope module i_sub4_bound $end
        $var real_parameter 64 L P1 $end
-       $var wire 32 [ driven_from_bind [31:0] $end
+       $var wire 32 \ driven_from_bind [31:0] $end
       $upscope $end
       $scope module i_sub5 $end
        $var wire 1 = clk $end
@@ -172,87 +172,87 @@ $attrbegin misc 07 $unit::enum_t 4 enum_val_0 enum_val_1 enum_val_2 enum_val_3 0
        $scope sv_array in $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [0] $end
-         $var wire 128 \ in[0][0] [127:0] $end
-         $var wire 128 ] in[0][1] [127:0] $end
-         $var wire 128 ^ in[0][2] [127:0] $end
+         $var wire 128 ] in[0][0] [127:0] $end
+         $var wire 128 ^ in[0][1] [127:0] $end
+         $var wire 128 _ in[0][2] [127:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [1] $end
-         $var wire 128 _ in[1][0] [127:0] $end
-         $var wire 128 ` in[1][1] [127:0] $end
-         $var wire 128 a in[1][2] [127:0] $end
+         $var wire 128 ` in[1][0] [127:0] $end
+         $var wire 128 a in[1][1] [127:0] $end
+         $var wire 128 b in[1][2] [127:0] $end
         $upscope $end
        $upscope $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array out $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [0] $end
-         $var wire 8 b out[0][0] [7:0] $end
-         $var wire 8 c out[0][1] [7:0] $end
-         $var wire 8 d out[0][2] [7:0] $end
+         $var wire 8 c out[0][0] [7:0] $end
+         $var wire 8 d out[0][1] [7:0] $end
+         $var wire 8 e out[0][2] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [1] $end
-         $var wire 8 e out[1][0] [7:0] $end
-         $var wire 8 f out[1][1] [7:0] $end
-         $var wire 8 g out[1][2] [7:0] $end
+         $var wire 8 f out[1][0] [7:0] $end
+         $var wire 8 g out[1][1] [7:0] $end
+         $var wire 8 h out[1][2] [7:0] $end
         $upscope $end
        $upscope $end
-       $var int 32 h count [31:0] $end
+       $var int 32 i count [31:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array val0 $end
-        $var wire 8 i val0[0] [7:0] $end
-        $var wire 8 j val0[1] [7:0] $end
+        $var wire 8 j val0[0] [7:0] $end
+        $var wire 8 k val0[1] [7:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array val1 $end
-        $var wire 8 k val1[0] [7:0] $end
-        $var wire 8 l val1[1] [7:0] $end
+        $var wire 8 l val1[0] [7:0] $end
+        $var wire 8 m val1[1] [7:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array val2 $end
-        $var wire 8 m val2[0] [7:0] $end
-        $var wire 8 n val2[1] [7:0] $end
+        $var wire 8 n val2[0] [7:0] $end
+        $var wire 8 o val2[1] [7:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array val3 $end
-        $var wire 8 o val3[0] [7:0] $end
-        $var wire 8 p val3[1] [7:0] $end
+        $var wire 8 p val3[0] [7:0] $end
+        $var wire 8 q val3[1] [7:0] $end
        $upscope $end
        $scope module i_sub0 $end
-        $var parameter 32 q P0 [31:0] $end
-        $var parameter 32 r P1 [31:0] $end
+        $var parameter 32 r P0 [31:0] $end
+        $var parameter 32 s P1 [31:0] $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array out $end
-         $var wire 8 s out[0] [7:0] $end
-         $var wire 8 t out[1] [7:0] $end
+         $var wire 8 t out[0] [7:0] $end
+         $var wire 8 u out[1] [7:0] $end
         $upscope $end
        $upscope $end
        $scope module i_sub1 $end
-        $var parameter 32 q P0 [31:0] $end
-        $var parameter 32 r P1 [31:0] $end
+        $var parameter 32 r P0 [31:0] $end
+        $var parameter 32 s P1 [31:0] $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array out $end
-         $var wire 8 u out[0] [7:0] $end
-         $var wire 8 v out[1] [7:0] $end
+         $var wire 8 v out[0] [7:0] $end
+         $var wire 8 w out[1] [7:0] $end
         $upscope $end
        $upscope $end
        $scope module i_sub2 $end
-        $var parameter 32 q P0 [31:0] $end
-        $var parameter 32 r P1 [31:0] $end
+        $var parameter 32 r P0 [31:0] $end
+        $var parameter 32 s P1 [31:0] $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array out $end
-         $var wire 8 w out[0] [7:0] $end
-         $var wire 8 x out[1] [7:0] $end
+         $var wire 8 x out[0] [7:0] $end
+         $var wire 8 y out[1] [7:0] $end
         $upscope $end
        $upscope $end
        $scope module i_sub3 $end
-        $var parameter 32 q P0 [31:0] $end
-        $var parameter 32 y P1 [31:0] $end
+        $var parameter 32 r P0 [31:0] $end
+        $var parameter 32 z P1 [31:0] $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array out $end
-         $var wire 8 z out[0] [7:0] $end
-         $var wire 8 { out[1] [7:0] $end
+         $var wire 8 { out[0] [7:0] $end
+         $var wire 8 | out[1] [7:0] $end
         $upscope $end
        $upscope $end
       $upscope $end
@@ -260,46 +260,46 @@ $attrbegin misc 07 $unit::enum_t 4 enum_val_0 enum_val_1 enum_val_2 enum_val_3 0
      $scope module i_sub4_1 $end
       $var parameter 32 K P0 [31:0] $end
       $var real_parameter 64 L P1 $end
-      $var real_parameter 64 | P3 $end
+      $var real_parameter 64 } P3 $end
       $var wire 1 = clk $end
-      $var wire 8 I in [7:0] $end
+      $var wire 8 N in [7:0] $end
       $var wire 8 J out [7:0] $end
       $var logic 8 J ff [7:0] $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array sub5_in $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [0] $end
-        $var logic 128 } sub5_in[0][0] [127:0] $end
-        $var logic 128 ~ sub5_in[0][1] [127:0] $end
-        $var logic 128 !! sub5_in[0][2] [127:0] $end
+        $var logic 128 ~ sub5_in[0][0] [127:0] $end
+        $var logic 128 !! sub5_in[0][1] [127:0] $end
+        $var logic 128 "! sub5_in[0][2] [127:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [1] $end
-        $var logic 128 "! sub5_in[1][0] [127:0] $end
-        $var logic 128 #! sub5_in[1][1] [127:0] $end
-        $var logic 128 $! sub5_in[1][2] [127:0] $end
+        $var logic 128 #! sub5_in[1][0] [127:0] $end
+        $var logic 128 $! sub5_in[1][1] [127:0] $end
+        $var logic 128 %! sub5_in[1][2] [127:0] $end
        $upscope $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array sub5_out $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [0] $end
-        $var wire 8 %! sub5_out[0][0] [7:0] $end
-        $var wire 8 &! sub5_out[0][1] [7:0] $end
-        $var wire 8 '! sub5_out[0][2] [7:0] $end
+        $var wire 8 &! sub5_out[0][0] [7:0] $end
+        $var wire 8 '! sub5_out[0][1] [7:0] $end
+        $var wire 8 (! sub5_out[0][2] [7:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [1] $end
-        $var wire 8 (! sub5_out[1][0] [7:0] $end
-        $var wire 8 )! sub5_out[1][1] [7:0] $end
-        $var wire 8 *! sub5_out[1][2] [7:0] $end
+        $var wire 8 )! sub5_out[1][0] [7:0] $end
+        $var wire 8 *! sub5_out[1][1] [7:0] $end
+        $var wire 8 +! sub5_out[1][2] [7:0] $end
        $upscope $end
       $upscope $end
-      $var int 32 +! count [31:0] $end
-      $var int 32 ,! driven_from_bind [31:0] $end
+      $var int 32 ,! count [31:0] $end
+      $var int 32 -! driven_from_bind [31:0] $end
       $scope module i_sub4_bound $end
        $var real_parameter 64 L P1 $end
-       $var wire 32 ,! driven_from_bind [31:0] $end
+       $var wire 32 -! driven_from_bind [31:0] $end
       $upscope $end
       $scope module i_sub5 $end
        $var wire 1 = clk $end
@@ -307,87 +307,87 @@ $attrbegin misc 07 $unit::enum_t 4 enum_val_0 enum_val_1 enum_val_2 enum_val_3 0
        $scope sv_array in $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [0] $end
-         $var wire 128 -! in[0][0] [127:0] $end
-         $var wire 128 .! in[0][1] [127:0] $end
-         $var wire 128 /! in[0][2] [127:0] $end
+         $var wire 128 .! in[0][0] [127:0] $end
+         $var wire 128 /! in[0][1] [127:0] $end
+         $var wire 128 0! in[0][2] [127:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [1] $end
-         $var wire 128 0! in[1][0] [127:0] $end
-         $var wire 128 1! in[1][1] [127:0] $end
-         $var wire 128 2! in[1][2] [127:0] $end
+         $var wire 128 1! in[1][0] [127:0] $end
+         $var wire 128 2! in[1][1] [127:0] $end
+         $var wire 128 3! in[1][2] [127:0] $end
         $upscope $end
        $upscope $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array out $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [0] $end
-         $var wire 8 3! out[0][0] [7:0] $end
-         $var wire 8 4! out[0][1] [7:0] $end
-         $var wire 8 5! out[0][2] [7:0] $end
+         $var wire 8 4! out[0][0] [7:0] $end
+         $var wire 8 5! out[0][1] [7:0] $end
+         $var wire 8 6! out[0][2] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [1] $end
-         $var wire 8 6! out[1][0] [7:0] $end
-         $var wire 8 7! out[1][1] [7:0] $end
-         $var wire 8 8! out[1][2] [7:0] $end
+         $var wire 8 7! out[1][0] [7:0] $end
+         $var wire 8 8! out[1][1] [7:0] $end
+         $var wire 8 9! out[1][2] [7:0] $end
         $upscope $end
        $upscope $end
-       $var int 32 9! count [31:0] $end
+       $var int 32 :! count [31:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array val0 $end
-        $var wire 8 :! val0[0] [7:0] $end
-        $var wire 8 ;! val0[1] [7:0] $end
+        $var wire 8 ;! val0[0] [7:0] $end
+        $var wire 8 <! val0[1] [7:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array val1 $end
-        $var wire 8 <! val1[0] [7:0] $end
-        $var wire 8 =! val1[1] [7:0] $end
+        $var wire 8 =! val1[0] [7:0] $end
+        $var wire 8 >! val1[1] [7:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array val2 $end
-        $var wire 8 >! val2[0] [7:0] $end
-        $var wire 8 ?! val2[1] [7:0] $end
+        $var wire 8 ?! val2[0] [7:0] $end
+        $var wire 8 @! val2[1] [7:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array val3 $end
-        $var wire 8 @! val3[0] [7:0] $end
-        $var wire 8 A! val3[1] [7:0] $end
+        $var wire 8 A! val3[0] [7:0] $end
+        $var wire 8 B! val3[1] [7:0] $end
        $upscope $end
        $scope module i_sub0 $end
-        $var parameter 32 q P0 [31:0] $end
-        $var parameter 32 r P1 [31:0] $end
+        $var parameter 32 r P0 [31:0] $end
+        $var parameter 32 s P1 [31:0] $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array out $end
-         $var wire 8 B! out[0] [7:0] $end
-         $var wire 8 C! out[1] [7:0] $end
+         $var wire 8 C! out[0] [7:0] $end
+         $var wire 8 D! out[1] [7:0] $end
         $upscope $end
        $upscope $end
        $scope module i_sub1 $end
-        $var parameter 32 q P0 [31:0] $end
-        $var parameter 32 r P1 [31:0] $end
+        $var parameter 32 r P0 [31:0] $end
+        $var parameter 32 s P1 [31:0] $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array out $end
-         $var wire 8 D! out[0] [7:0] $end
-         $var wire 8 E! out[1] [7:0] $end
+         $var wire 8 E! out[0] [7:0] $end
+         $var wire 8 F! out[1] [7:0] $end
         $upscope $end
        $upscope $end
        $scope module i_sub2 $end
-        $var parameter 32 q P0 [31:0] $end
-        $var parameter 32 r P1 [31:0] $end
+        $var parameter 32 r P0 [31:0] $end
+        $var parameter 32 s P1 [31:0] $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array out $end
-         $var wire 8 F! out[0] [7:0] $end
-         $var wire 8 G! out[1] [7:0] $end
+         $var wire 8 G! out[0] [7:0] $end
+         $var wire 8 H! out[1] [7:0] $end
         $upscope $end
        $upscope $end
        $scope module i_sub3 $end
-        $var parameter 32 q P0 [31:0] $end
-        $var parameter 32 y P1 [31:0] $end
+        $var parameter 32 r P0 [31:0] $end
+        $var parameter 32 z P1 [31:0] $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array out $end
-         $var wire 8 H! out[0] [7:0] $end
-         $var wire 8 I! out[1] [7:0] $end
+         $var wire 8 I! out[0] [7:0] $end
+         $var wire 8 J! out[1] [7:0] $end
         $upscope $end
        $upscope $end
       $upscope $end
@@ -397,8 +397,8 @@ $attrbegin misc 07 $unit::enum_t 4 enum_val_0 enum_val_1 enum_val_2 enum_val_3 0
      $var parameter 8 D P0 [7:0] $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array UNPACKED_ARRAY $end
-      $var parameter 32 J! UNPACKED_ARRAY[0] [31:0] $end
-      $var parameter 32 K! UNPACKED_ARRAY[1] [31:0] $end
+      $var parameter 32 K! UNPACKED_ARRAY[0] [31:0] $end
+      $var parameter 32 L! UNPACKED_ARRAY[1] [31:0] $end
      $upscope $end
      $var parameter 16 G UNUSED [15:0] $end
      $attrbegin misc 07 "" 4 $end
@@ -406,52 +406,52 @@ $attrbegin misc 07 $unit::enum_t 4 enum_val_0 enum_val_1 enum_val_2 enum_val_3 0
      $var wire 1 = clk $end
      $var wire 8 @ in [7:0] $end
      $var wire 8 C out [7:0] $end
-     $var logic 8 L! ff [7:0] $end
+     $var logic 8 M! ff [7:0] $end
      $var wire 8 C out4 [7:0] $end
-     $var wire 8 M! out4_2 [7:0] $end
+     $var wire 8 N! out4_2 [7:0] $end
      $scope module i_sub4_0 $end
       $var parameter 32 K P0 [31:0] $end
       $var real_parameter 64 L P1 $end
       $var real_parameter 64 M P3 $end
       $var wire 1 = clk $end
-      $var wire 8 L! in [7:0] $end
+      $var wire 8 O! in [7:0] $end
       $var wire 8 C out [7:0] $end
       $var logic 8 C ff [7:0] $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array sub5_in $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [0] $end
-        $var logic 128 N! sub5_in[0][0] [127:0] $end
-        $var logic 128 O! sub5_in[0][1] [127:0] $end
-        $var logic 128 P! sub5_in[0][2] [127:0] $end
+        $var logic 128 P! sub5_in[0][0] [127:0] $end
+        $var logic 128 Q! sub5_in[0][1] [127:0] $end
+        $var logic 128 R! sub5_in[0][2] [127:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [1] $end
-        $var logic 128 Q! sub5_in[1][0] [127:0] $end
-        $var logic 128 R! sub5_in[1][1] [127:0] $end
-        $var logic 128 S! sub5_in[1][2] [127:0] $end
+        $var logic 128 S! sub5_in[1][0] [127:0] $end
+        $var logic 128 T! sub5_in[1][1] [127:0] $end
+        $var logic 128 U! sub5_in[1][2] [127:0] $end
        $upscope $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array sub5_out $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [0] $end
-        $var wire 8 T! sub5_out[0][0] [7:0] $end
-        $var wire 8 U! sub5_out[0][1] [7:0] $end
-        $var wire 8 V! sub5_out[0][2] [7:0] $end
+        $var wire 8 V! sub5_out[0][0] [7:0] $end
+        $var wire 8 W! sub5_out[0][1] [7:0] $end
+        $var wire 8 X! sub5_out[0][2] [7:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [1] $end
-        $var wire 8 W! sub5_out[1][0] [7:0] $end
-        $var wire 8 X! sub5_out[1][1] [7:0] $end
-        $var wire 8 Y! sub5_out[1][2] [7:0] $end
+        $var wire 8 Y! sub5_out[1][0] [7:0] $end
+        $var wire 8 Z! sub5_out[1][1] [7:0] $end
+        $var wire 8 [! sub5_out[1][2] [7:0] $end
        $upscope $end
       $upscope $end
-      $var int 32 Z! count [31:0] $end
-      $var int 32 [! driven_from_bind [31:0] $end
+      $var int 32 \! count [31:0] $end
+      $var int 32 ]! driven_from_bind [31:0] $end
       $scope module i_sub4_bound $end
        $var real_parameter 64 L P1 $end
-       $var wire 32 [! driven_from_bind [31:0] $end
+       $var wire 32 ]! driven_from_bind [31:0] $end
       $upscope $end
       $scope module i_sub5 $end
        $var wire 1 = clk $end
@@ -459,134 +459,134 @@ $attrbegin misc 07 $unit::enum_t 4 enum_val_0 enum_val_1 enum_val_2 enum_val_3 0
        $scope sv_array in $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [0] $end
-         $var wire 128 \! in[0][0] [127:0] $end
-         $var wire 128 ]! in[0][1] [127:0] $end
-         $var wire 128 ^! in[0][2] [127:0] $end
+         $var wire 128 ^! in[0][0] [127:0] $end
+         $var wire 128 _! in[0][1] [127:0] $end
+         $var wire 128 `! in[0][2] [127:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [1] $end
-         $var wire 128 _! in[1][0] [127:0] $end
-         $var wire 128 `! in[1][1] [127:0] $end
-         $var wire 128 a! in[1][2] [127:0] $end
+         $var wire 128 a! in[1][0] [127:0] $end
+         $var wire 128 b! in[1][1] [127:0] $end
+         $var wire 128 c! in[1][2] [127:0] $end
         $upscope $end
        $upscope $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array out $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [0] $end
-         $var wire 8 b! out[0][0] [7:0] $end
-         $var wire 8 c! out[0][1] [7:0] $end
-         $var wire 8 d! out[0][2] [7:0] $end
+         $var wire 8 d! out[0][0] [7:0] $end
+         $var wire 8 e! out[0][1] [7:0] $end
+         $var wire 8 f! out[0][2] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [1] $end
-         $var wire 8 e! out[1][0] [7:0] $end
-         $var wire 8 f! out[1][1] [7:0] $end
-         $var wire 8 g! out[1][2] [7:0] $end
+         $var wire 8 g! out[1][0] [7:0] $end
+         $var wire 8 h! out[1][1] [7:0] $end
+         $var wire 8 i! out[1][2] [7:0] $end
         $upscope $end
        $upscope $end
-       $var int 32 h! count [31:0] $end
+       $var int 32 j! count [31:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array val0 $end
-        $var wire 8 i! val0[0] [7:0] $end
-        $var wire 8 j! val0[1] [7:0] $end
+        $var wire 8 k! val0[0] [7:0] $end
+        $var wire 8 l! val0[1] [7:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array val1 $end
-        $var wire 8 k! val1[0] [7:0] $end
-        $var wire 8 l! val1[1] [7:0] $end
+        $var wire 8 m! val1[0] [7:0] $end
+        $var wire 8 n! val1[1] [7:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array val2 $end
-        $var wire 8 m! val2[0] [7:0] $end
-        $var wire 8 n! val2[1] [7:0] $end
+        $var wire 8 o! val2[0] [7:0] $end
+        $var wire 8 p! val2[1] [7:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array val3 $end
-        $var wire 8 o! val3[0] [7:0] $end
-        $var wire 8 p! val3[1] [7:0] $end
+        $var wire 8 q! val3[0] [7:0] $end
+        $var wire 8 r! val3[1] [7:0] $end
        $upscope $end
        $scope module i_sub0 $end
-        $var parameter 32 q P0 [31:0] $end
-        $var parameter 32 r P1 [31:0] $end
-        $attrbegin array unpacked bounds 1 $end
-        $scope sv_array out $end
-         $var wire 8 q! out[0] [7:0] $end
-         $var wire 8 r! out[1] [7:0] $end
-        $upscope $end
-       $upscope $end
-       $scope module i_sub1 $end
-        $var parameter 32 q P0 [31:0] $end
-        $var parameter 32 r P1 [31:0] $end
+        $var parameter 32 r P0 [31:0] $end
+        $var parameter 32 s P1 [31:0] $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array out $end
          $var wire 8 s! out[0] [7:0] $end
          $var wire 8 t! out[1] [7:0] $end
         $upscope $end
        $upscope $end
-       $scope module i_sub2 $end
-        $var parameter 32 q P0 [31:0] $end
-        $var parameter 32 r P1 [31:0] $end
+       $scope module i_sub1 $end
+        $var parameter 32 r P0 [31:0] $end
+        $var parameter 32 s P1 [31:0] $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array out $end
          $var wire 8 u! out[0] [7:0] $end
          $var wire 8 v! out[1] [7:0] $end
         $upscope $end
        $upscope $end
-       $scope module i_sub3 $end
-        $var parameter 32 q P0 [31:0] $end
-        $var parameter 32 y P1 [31:0] $end
+       $scope module i_sub2 $end
+        $var parameter 32 r P0 [31:0] $end
+        $var parameter 32 s P1 [31:0] $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array out $end
          $var wire 8 w! out[0] [7:0] $end
          $var wire 8 x! out[1] [7:0] $end
         $upscope $end
        $upscope $end
+       $scope module i_sub3 $end
+        $var parameter 32 r P0 [31:0] $end
+        $var parameter 32 z P1 [31:0] $end
+        $attrbegin array unpacked bounds 1 $end
+        $scope sv_array out $end
+         $var wire 8 y! out[0] [7:0] $end
+         $var wire 8 z! out[1] [7:0] $end
+        $upscope $end
+       $upscope $end
       $upscope $end
      $upscope $end
      $scope module i_sub4_1 $end
       $var parameter 32 K P0 [31:0] $end
       $var real_parameter 64 L P1 $end
-      $var real_parameter 64 | P3 $end
+      $var real_parameter 64 } P3 $end
       $var wire 1 = clk $end
-      $var wire 8 L! in [7:0] $end
-      $var wire 8 M! out [7:0] $end
-      $var logic 8 M! ff [7:0] $end
+      $var wire 8 O! in [7:0] $end
+      $var wire 8 N! out [7:0] $end
+      $var logic 8 N! ff [7:0] $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array sub5_in $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [0] $end
-        $var logic 128 y! sub5_in[0][0] [127:0] $end
-        $var logic 128 z! sub5_in[0][1] [127:0] $end
-        $var logic 128 {! sub5_in[0][2] [127:0] $end
+        $var logic 128 {! sub5_in[0][0] [127:0] $end
+        $var logic 128 |! sub5_in[0][1] [127:0] $end
+        $var logic 128 }! sub5_in[0][2] [127:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [1] $end
-        $var logic 128 |! sub5_in[1][0] [127:0] $end
-        $var logic 128 }! sub5_in[1][1] [127:0] $end
-        $var logic 128 ~! sub5_in[1][2] [127:0] $end
+        $var logic 128 ~! sub5_in[1][0] [127:0] $end
+        $var logic 128 !" sub5_in[1][1] [127:0] $end
+        $var logic 128 "" sub5_in[1][2] [127:0] $end
        $upscope $end
       $upscope $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array sub5_out $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [0] $end
-        $var wire 8 !" sub5_out[0][0] [7:0] $end
-        $var wire 8 "" sub5_out[0][1] [7:0] $end
-        $var wire 8 #" sub5_out[0][2] [7:0] $end
+        $var wire 8 #" sub5_out[0][0] [7:0] $end
+        $var wire 8 $" sub5_out[0][1] [7:0] $end
+        $var wire 8 %" sub5_out[0][2] [7:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 2 $end
        $scope sv_array [1] $end
-        $var wire 8 $" sub5_out[1][0] [7:0] $end
-        $var wire 8 %" sub5_out[1][1] [7:0] $end
-        $var wire 8 &" sub5_out[1][2] [7:0] $end
+        $var wire 8 &" sub5_out[1][0] [7:0] $end
+        $var wire 8 '" sub5_out[1][1] [7:0] $end
+        $var wire 8 (" sub5_out[1][2] [7:0] $end
        $upscope $end
       $upscope $end
-      $var int 32 '" count [31:0] $end
-      $var int 32 (" driven_from_bind [31:0] $end
+      $var int 32 )" count [31:0] $end
+      $var int 32 *" driven_from_bind [31:0] $end
       $scope module i_sub4_bound $end
        $var real_parameter 64 L P1 $end
-       $var wire 32 (" driven_from_bind [31:0] $end
+       $var wire 32 *" driven_from_bind [31:0] $end
       $upscope $end
       $scope module i_sub5 $end
        $var wire 1 = clk $end
@@ -594,89 +594,89 @@ $attrbegin misc 07 $unit::enum_t 4 enum_val_0 enum_val_1 enum_val_2 enum_val_3 0
        $scope sv_array in $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [0] $end
-         $var wire 128 )" in[0][0] [127:0] $end
-         $var wire 128 *" in[0][1] [127:0] $end
-         $var wire 128 +" in[0][2] [127:0] $end
+         $var wire 128 +" in[0][0] [127:0] $end
+         $var wire 128 ," in[0][1] [127:0] $end
+         $var wire 128 -" in[0][2] [127:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [1] $end
-         $var wire 128 ," in[1][0] [127:0] $end
-         $var wire 128 -" in[1][1] [127:0] $end
-         $var wire 128 ." in[1][2] [127:0] $end
+         $var wire 128 ." in[1][0] [127:0] $end
+         $var wire 128 /" in[1][1] [127:0] $end
+         $var wire 128 0" in[1][2] [127:0] $end
         $upscope $end
        $upscope $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array out $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [0] $end
-         $var wire 8 /" out[0][0] [7:0] $end
-         $var wire 8 0" out[0][1] [7:0] $end
-         $var wire 8 1" out[0][2] [7:0] $end
+         $var wire 8 1" out[0][0] [7:0] $end
+         $var wire 8 2" out[0][1] [7:0] $end
+         $var wire 8 3" out[0][2] [7:0] $end
         $upscope $end
         $attrbegin array unpacked bounds 2 $end
         $scope sv_array [1] $end
-         $var wire 8 2" out[1][0] [7:0] $end
-         $var wire 8 3" out[1][1] [7:0] $end
-         $var wire 8 4" out[1][2] [7:0] $end
+         $var wire 8 4" out[1][0] [7:0] $end
+         $var wire 8 5" out[1][1] [7:0] $end
+         $var wire 8 6" out[1][2] [7:0] $end
         $upscope $end
        $upscope $end
-       $var int 32 5" count [31:0] $end
+       $var int 32 7" count [31:0] $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array val0 $end
-        $var wire 8 6" val0[0] [7:0] $end
-        $var wire 8 7" val0[1] [7:0] $end
+        $var wire 8 8" val0[0] [7:0] $end
+        $var wire 8 9" val0[1] [7:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array val1 $end
-        $var wire 8 8" val1[0] [7:0] $end
-        $var wire 8 9" val1[1] [7:0] $end
+        $var wire 8 :" val1[0] [7:0] $end
+        $var wire 8 ;" val1[1] [7:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array val2 $end
-        $var wire 8 :" val2[0] [7:0] $end
-        $var wire 8 ;" val2[1] [7:0] $end
+        $var wire 8 <" val2[0] [7:0] $end
+        $var wire 8 =" val2[1] [7:0] $end
        $upscope $end
        $attrbegin array unpacked bounds 1 $end
        $scope sv_array val3 $end
-        $var wire 8 <" val3[0] [7:0] $end
-        $var wire 8 =" val3[1] [7:0] $end
+        $var wire 8 >" val3[0] [7:0] $end
+        $var wire 8 ?" val3[1] [7:0] $end
        $upscope $end
        $scope module i_sub0 $end
-        $var parameter 32 q P0 [31:0] $end
-        $var parameter 32 r P1 [31:0] $end
-        $attrbegin array unpacked bounds 1 $end
-        $scope sv_array out $end
-         $var wire 8 >" out[0] [7:0] $end
-         $var wire 8 ?" out[1] [7:0] $end
-        $upscope $end
-       $upscope $end
-       $scope module i_sub1 $end
-        $var parameter 32 q P0 [31:0] $end
-        $var parameter 32 r P1 [31:0] $end
+        $var parameter 32 r P0 [31:0] $end
+        $var parameter 32 s P1 [31:0] $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array out $end
          $var wire 8 @" out[0] [7:0] $end
          $var wire 8 A" out[1] [7:0] $end
         $upscope $end
        $upscope $end
-       $scope module i_sub2 $end
-        $var parameter 32 q P0 [31:0] $end
-        $var parameter 32 r P1 [31:0] $end
+       $scope module i_sub1 $end
+        $var parameter 32 r P0 [31:0] $end
+        $var parameter 32 s P1 [31:0] $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array out $end
          $var wire 8 B" out[0] [7:0] $end
          $var wire 8 C" out[1] [7:0] $end
         $upscope $end
        $upscope $end
-       $scope module i_sub3 $end
-        $var parameter 32 q P0 [31:0] $end
-        $var parameter 32 y P1 [31:0] $end
+       $scope module i_sub2 $end
+        $var parameter 32 r P0 [31:0] $end
+        $var parameter 32 s P1 [31:0] $end
         $attrbegin array unpacked bounds 1 $end
         $scope sv_array out $end
          $var wire 8 D" out[0] [7:0] $end
          $var wire 8 E" out[1] [7:0] $end
         $upscope $end
        $upscope $end
+       $scope module i_sub3 $end
+        $var parameter 32 r P0 [31:0] $end
+        $var parameter 32 z P1 [31:0] $end
+        $attrbegin array unpacked bounds 1 $end
+        $scope sv_array out $end
+         $var wire 8 F" out[0] [7:0] $end
+         $var wire 8 G" out[1] [7:0] $end
+        $upscope $end
+       $upscope $end
       $upscope $end
      $upscope $end
     $upscope $end
@@ -699,574 +699,574 @@ $attrbegin misc 07 $unit::enum_t 4 enum_val_0 enum_val_1 enum_val_2 enum_val_3 0
    $upscope $end
   $upscope $end
   $scope module i_sub3 $end
-   $var parameter 8 F" P0 [7:0] $end
+   $var parameter 8 H" P0 [7:0] $end
    $attrbegin array unpacked bounds 1 $end
    $scope sv_array UNPACKED_ARRAY $end
-    $var parameter 32 G" UNPACKED_ARRAY[0] [31:0] $end
-    $var parameter 32 H" UNPACKED_ARRAY[1] [31:0] $end
+    $var parameter 32 I" UNPACKED_ARRAY[0] [31:0] $end
+    $var parameter 32 J" UNPACKED_ARRAY[1] [31:0] $end
    $upscope $end
-   $var parameter 16 I" UNUSED [15:0] $end
+   $var parameter 16 K" UNUSED [15:0] $end
    $attrbegin misc 07 "" 1 $end
-   $var parameter 2 J" ENUM [1:0] $end
+   $var parameter 2 L" ENUM [1:0] $end
    $var wire 1 ! clk $end
    $var wire 8 ' in [7:0] $end
    $var wire 8 ( out [7:0] $end
-   $var logic 8 K" ff [7:0] $end
+   $var logic 8 M" ff [7:0] $end
    $var wire 8 ( out4 [7:0] $end
-   $var wire 8 L" out4_2 [7:0] $end
+   $var wire 8 N" out4_2 [7:0] $end
    $scope module i_sub4_0 $end
-    $var parameter 32 M" P0 [31:0] $end
-    $var real_parameter 64 N" P1 $end
-    $var real_parameter 64 O" P3 $end
+    $var parameter 32 O" P0 [31:0] $end
+    $var real_parameter 64 P" P1 $end
+    $var real_parameter 64 Q" P3 $end
     $var wire 1 ! clk $end
-    $var wire 8 K" in [7:0] $end
+    $var wire 8 R" in [7:0] $end
     $var wire 8 ( out [7:0] $end
     $var logic 8 ( ff [7:0] $end
     $attrbegin array unpacked bounds 1 $end
     $scope sv_array sub5_in $end
      $attrbegin array unpacked bounds 2 $end
      $scope sv_array [0] $end
-      $var logic 128 P" sub5_in[0][0] [127:0] $end
-      $var logic 128 Q" sub5_in[0][1] [127:0] $end
-      $var logic 128 R" sub5_in[0][2] [127:0] $end
+      $var logic 128 S" sub5_in[0][0] [127:0] $end
+      $var logic 128 T" sub5_in[0][1] [127:0] $end
+      $var logic 128 U" sub5_in[0][2] [127:0] $end
      $upscope $end
      $attrbegin array unpacked bounds 2 $end
      $scope sv_array [1] $end
-      $var logic 128 S" sub5_in[1][0] [127:0] $end
-      $var logic 128 T" sub5_in[1][1] [127:0] $end
-      $var logic 128 U" sub5_in[1][2] [127:0] $end
+      $var logic 128 V" sub5_in[1][0] [127:0] $end
+      $var logic 128 W" sub5_in[1][1] [127:0] $end
+      $var logic 128 X" sub5_in[1][2] [127:0] $end
      $upscope $end
     $upscope $end
     $attrbegin array unpacked bounds 1 $end
     $scope sv_array sub5_out $end
      $attrbegin array unpacked bounds 2 $end
      $scope sv_array [0] $end
-      $var wire 8 V" sub5_out[0][0] [7:0] $end
-      $var wire 8 W" sub5_out[0][1] [7:0] $end
-      $var wire 8 X" sub5_out[0][2] [7:0] $end
+      $var wire 8 Y" sub5_out[0][0] [7:0] $end
+      $var wire 8 Z" sub5_out[0][1] [7:0] $end
+      $var wire 8 [" sub5_out[0][2] [7:0] $end
      $upscope $end
      $attrbegin array unpacked bounds 2 $end
      $scope sv_array [1] $end
-      $var wire 8 Y" sub5_out[1][0] [7:0] $end
-      $var wire 8 Z" sub5_out[1][1] [7:0] $end
-      $var wire 8 [" sub5_out[1][2] [7:0] $end
+      $var wire 8 \" sub5_out[1][0] [7:0] $end
+      $var wire 8 ]" sub5_out[1][1] [7:0] $end
+      $var wire 8 ^" sub5_out[1][2] [7:0] $end
      $upscope $end
     $upscope $end
-    $var int 32 \" count [31:0] $end
-    $var int 32 ]" driven_from_bind [31:0] $end
+    $var int 32 _" count [31:0] $end
+    $var int 32 `" driven_from_bind [31:0] $end
     $scope module i_sub4_bound $end
-     $var real_parameter 64 N" P1 $end
-     $var wire 32 ]" driven_from_bind [31:0] $end
+     $var real_parameter 64 P" P1 $end
+     $var wire 32 `" driven_from_bind [31:0] $end
     $upscope $end
     $scope module i_sub5 $end
-     $var wire 1 ^" clk $end
+     $var wire 1 a" clk $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array in $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [0] $end
-       $var wire 128 _" in[0][0] [127:0] $end
-       $var wire 128 `" in[0][1] [127:0] $end
-       $var wire 128 a" in[0][2] [127:0] $end
+       $var wire 128 b" in[0][0] [127:0] $end
+       $var wire 128 c" in[0][1] [127:0] $end
+       $var wire 128 d" in[0][2] [127:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [1] $end
-       $var wire 128 b" in[1][0] [127:0] $end
-       $var wire 128 c" in[1][1] [127:0] $end
-       $var wire 128 d" in[1][2] [127:0] $end
+       $var wire 128 e" in[1][0] [127:0] $end
+       $var wire 128 f" in[1][1] [127:0] $end
+       $var wire 128 g" in[1][2] [127:0] $end
       $upscope $end
      $upscope $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array out $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [0] $end
-       $var wire 8 e" out[0][0] [7:0] $end
-       $var wire 8 f" out[0][1] [7:0] $end
-       $var wire 8 g" out[0][2] [7:0] $end
+       $var wire 8 h" out[0][0] [7:0] $end
+       $var wire 8 i" out[0][1] [7:0] $end
+       $var wire 8 j" out[0][2] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [1] $end
-       $var wire 8 h" out[1][0] [7:0] $end
-       $var wire 8 i" out[1][1] [7:0] $end
-       $var wire 8 j" out[1][2] [7:0] $end
+       $var wire 8 k" out[1][0] [7:0] $end
+       $var wire 8 l" out[1][1] [7:0] $end
+       $var wire 8 m" out[1][2] [7:0] $end
       $upscope $end
      $upscope $end
-     $var int 32 k" count [31:0] $end
+     $var int 32 n" count [31:0] $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array val0 $end
-      $var wire 8 l" val0[0] [7:0] $end
-      $var wire 8 m" val0[1] [7:0] $end
+      $var wire 8 o" val0[0] [7:0] $end
+      $var wire 8 p" val0[1] [7:0] $end
      $upscope $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array val1 $end
-      $var wire 8 n" val1[0] [7:0] $end
-      $var wire 8 o" val1[1] [7:0] $end
+      $var wire 8 q" val1[0] [7:0] $end
+      $var wire 8 r" val1[1] [7:0] $end
      $upscope $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array val2 $end
-      $var wire 8 p" val2[0] [7:0] $end
-      $var wire 8 q" val2[1] [7:0] $end
+      $var wire 8 s" val2[0] [7:0] $end
+      $var wire 8 t" val2[1] [7:0] $end
      $upscope $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array val3 $end
-      $var wire 8 r" val3[0] [7:0] $end
-      $var wire 8 s" val3[1] [7:0] $end
+      $var wire 8 u" val3[0] [7:0] $end
+      $var wire 8 v" val3[1] [7:0] $end
      $upscope $end
      $scope module i_sub0 $end
-      $var parameter 32 t" P0 [31:0] $end
-      $var parameter 32 u" P1 [31:0] $end
+      $var parameter 32 w" P0 [31:0] $end
+      $var parameter 32 x" P1 [31:0] $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array out $end
-       $var wire 8 v" out[0] [7:0] $end
-       $var wire 8 w" out[1] [7:0] $end
+       $var wire 8 y" out[0] [7:0] $end
+       $var wire 8 z" out[1] [7:0] $end
       $upscope $end
      $upscope $end
      $scope module i_sub1 $end
-      $var parameter 32 t" P0 [31:0] $end
-      $var parameter 32 u" P1 [31:0] $end
+      $var parameter 32 w" P0 [31:0] $end
+      $var parameter 32 x" P1 [31:0] $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array out $end
-       $var wire 8 x" out[0] [7:0] $end
-       $var wire 8 y" out[1] [7:0] $end
+       $var wire 8 {" out[0] [7:0] $end
+       $var wire 8 |" out[1] [7:0] $end
       $upscope $end
      $upscope $end
      $scope module i_sub2 $end
-      $var parameter 32 t" P0 [31:0] $end
-      $var parameter 32 u" P1 [31:0] $end
-      $attrbegin array unpacked bounds 1 $end
-      $scope sv_array out $end
-       $var wire 8 z" out[0] [7:0] $end
-       $var wire 8 {" out[1] [7:0] $end
-      $upscope $end
-     $upscope $end
-     $scope module i_sub3 $end
-      $var parameter 32 t" P0 [31:0] $end
-      $var parameter 32 |" P1 [31:0] $end
+      $var parameter 32 w" P0 [31:0] $end
+      $var parameter 32 x" P1 [31:0] $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array out $end
        $var wire 8 }" out[0] [7:0] $end
        $var wire 8 ~" out[1] [7:0] $end
       $upscope $end
      $upscope $end
+     $scope module i_sub3 $end
+      $var parameter 32 w" P0 [31:0] $end
+      $var parameter 32 !# P1 [31:0] $end
+      $attrbegin array unpacked bounds 1 $end
+      $scope sv_array out $end
+       $var wire 8 "# out[0] [7:0] $end
+       $var wire 8 ## out[1] [7:0] $end
+      $upscope $end
+     $upscope $end
     $upscope $end
    $upscope $end
    $scope module i_sub4_1 $end
-    $var parameter 32 M" P0 [31:0] $end
-    $var real_parameter 64 N" P1 $end
-    $var real_parameter 64 !# P3 $end
+    $var parameter 32 O" P0 [31:0] $end
+    $var real_parameter 64 P" P1 $end
+    $var real_parameter 64 $# P3 $end
     $var wire 1 ! clk $end
-    $var wire 8 K" in [7:0] $end
-    $var wire 8 L" out [7:0] $end
-    $var logic 8 L" ff [7:0] $end
+    $var wire 8 R" in [7:0] $end
+    $var wire 8 N" out [7:0] $end
+    $var logic 8 N" ff [7:0] $end
     $attrbegin array unpacked bounds 1 $end
     $scope sv_array sub5_in $end
      $attrbegin array unpacked bounds 2 $end
      $scope sv_array [0] $end
-      $var logic 128 "# sub5_in[0][0] [127:0] $end
-      $var logic 128 ## sub5_in[0][1] [127:0] $end
-      $var logic 128 $# sub5_in[0][2] [127:0] $end
+      $var logic 128 %# sub5_in[0][0] [127:0] $end
+      $var logic 128 &# sub5_in[0][1] [127:0] $end
+      $var logic 128 '# sub5_in[0][2] [127:0] $end
      $upscope $end
      $attrbegin array unpacked bounds 2 $end
      $scope sv_array [1] $end
-      $var logic 128 %# sub5_in[1][0] [127:0] $end
-      $var logic 128 &# sub5_in[1][1] [127:0] $end
-      $var logic 128 '# sub5_in[1][2] [127:0] $end
+      $var logic 128 (# sub5_in[1][0] [127:0] $end
+      $var logic 128 )# sub5_in[1][1] [127:0] $end
+      $var logic 128 *# sub5_in[1][2] [127:0] $end
      $upscope $end
     $upscope $end
     $attrbegin array unpacked bounds 1 $end
     $scope sv_array sub5_out $end
      $attrbegin array unpacked bounds 2 $end
      $scope sv_array [0] $end
-      $var wire 8 (# sub5_out[0][0] [7:0] $end
-      $var wire 8 )# sub5_out[0][1] [7:0] $end
-      $var wire 8 *# sub5_out[0][2] [7:0] $end
+      $var wire 8 +# sub5_out[0][0] [7:0] $end
+      $var wire 8 ,# sub5_out[0][1] [7:0] $end
+      $var wire 8 -# sub5_out[0][2] [7:0] $end
      $upscope $end
      $attrbegin array unpacked bounds 2 $end
      $scope sv_array [1] $end
-      $var wire 8 +# sub5_out[1][0] [7:0] $end
-      $var wire 8 ,# sub5_out[1][1] [7:0] $end
-      $var wire 8 -# sub5_out[1][2] [7:0] $end
+      $var wire 8 .# sub5_out[1][0] [7:0] $end
+      $var wire 8 /# sub5_out[1][1] [7:0] $end
+      $var wire 8 0# sub5_out[1][2] [7:0] $end
      $upscope $end
     $upscope $end
-    $var int 32 .# count [31:0] $end
-    $var int 32 /# driven_from_bind [31:0] $end
+    $var int 32 1# count [31:0] $end
+    $var int 32 2# driven_from_bind [31:0] $end
     $scope module i_sub4_bound $end
-     $var real_parameter 64 N" P1 $end
-     $var wire 32 /# driven_from_bind [31:0] $end
+     $var real_parameter 64 P" P1 $end
+     $var wire 32 2# driven_from_bind [31:0] $end
     $upscope $end
     $scope module i_sub5 $end
-     $var wire 1 0# clk $end
+     $var wire 1 3# clk $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array in $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [0] $end
-       $var wire 128 1# in[0][0] [127:0] $end
-       $var wire 128 2# in[0][1] [127:0] $end
-       $var wire 128 3# in[0][2] [127:0] $end
+       $var wire 128 4# in[0][0] [127:0] $end
+       $var wire 128 5# in[0][1] [127:0] $end
+       $var wire 128 6# in[0][2] [127:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [1] $end
-       $var wire 128 4# in[1][0] [127:0] $end
-       $var wire 128 5# in[1][1] [127:0] $end
-       $var wire 128 6# in[1][2] [127:0] $end
+       $var wire 128 7# in[1][0] [127:0] $end
+       $var wire 128 8# in[1][1] [127:0] $end
+       $var wire 128 9# in[1][2] [127:0] $end
       $upscope $end
      $upscope $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array out $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [0] $end
-       $var wire 8 7# out[0][0] [7:0] $end
-       $var wire 8 8# out[0][1] [7:0] $end
-       $var wire 8 9# out[0][2] [7:0] $end
+       $var wire 8 :# out[0][0] [7:0] $end
+       $var wire 8 ;# out[0][1] [7:0] $end
+       $var wire 8 <# out[0][2] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [1] $end
-       $var wire 8 :# out[1][0] [7:0] $end
-       $var wire 8 ;# out[1][1] [7:0] $end
-       $var wire 8 <# out[1][2] [7:0] $end
+       $var wire 8 =# out[1][0] [7:0] $end
+       $var wire 8 ># out[1][1] [7:0] $end
+       $var wire 8 ?# out[1][2] [7:0] $end
       $upscope $end
      $upscope $end
-     $var int 32 =# count [31:0] $end
+     $var int 32 @# count [31:0] $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array val0 $end
-      $var wire 8 ># val0[0] [7:0] $end
-      $var wire 8 ?# val0[1] [7:0] $end
+      $var wire 8 A# val0[0] [7:0] $end
+      $var wire 8 B# val0[1] [7:0] $end
      $upscope $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array val1 $end
-      $var wire 8 @# val1[0] [7:0] $end
-      $var wire 8 A# val1[1] [7:0] $end
+      $var wire 8 C# val1[0] [7:0] $end
+      $var wire 8 D# val1[1] [7:0] $end
      $upscope $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array val2 $end
-      $var wire 8 B# val2[0] [7:0] $end
-      $var wire 8 C# val2[1] [7:0] $end
+      $var wire 8 E# val2[0] [7:0] $end
+      $var wire 8 F# val2[1] [7:0] $end
      $upscope $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array val3 $end
-      $var wire 8 D# val3[0] [7:0] $end
-      $var wire 8 E# val3[1] [7:0] $end
+      $var wire 8 G# val3[0] [7:0] $end
+      $var wire 8 H# val3[1] [7:0] $end
      $upscope $end
      $scope module i_sub0 $end
-      $var parameter 32 F# P0 [31:0] $end
-      $var parameter 32 G# P1 [31:0] $end
+      $var parameter 32 I# P0 [31:0] $end
+      $var parameter 32 J# P1 [31:0] $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array out $end
-       $var wire 8 H# out[0] [7:0] $end
-       $var wire 8 I# out[1] [7:0] $end
+       $var wire 8 K# out[0] [7:0] $end
+       $var wire 8 L# out[1] [7:0] $end
       $upscope $end
      $upscope $end
      $scope module i_sub1 $end
-      $var parameter 32 F# P0 [31:0] $end
-      $var parameter 32 G# P1 [31:0] $end
+      $var parameter 32 I# P0 [31:0] $end
+      $var parameter 32 J# P1 [31:0] $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array out $end
-       $var wire 8 J# out[0] [7:0] $end
-       $var wire 8 K# out[1] [7:0] $end
+       $var wire 8 M# out[0] [7:0] $end
+       $var wire 8 N# out[1] [7:0] $end
       $upscope $end
      $upscope $end
      $scope module i_sub2 $end
-      $var parameter 32 F# P0 [31:0] $end
-      $var parameter 32 G# P1 [31:0] $end
-      $attrbegin array unpacked bounds 1 $end
-      $scope sv_array out $end
-       $var wire 8 L# out[0] [7:0] $end
-       $var wire 8 M# out[1] [7:0] $end
-      $upscope $end
-     $upscope $end
-     $scope module i_sub3 $end
-      $var parameter 32 F# P0 [31:0] $end
-      $var parameter 32 N# P1 [31:0] $end
+      $var parameter 32 I# P0 [31:0] $end
+      $var parameter 32 J# P1 [31:0] $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array out $end
        $var wire 8 O# out[0] [7:0] $end
        $var wire 8 P# out[1] [7:0] $end
       $upscope $end
      $upscope $end
+     $scope module i_sub3 $end
+      $var parameter 32 I# P0 [31:0] $end
+      $var parameter 32 Q# P1 [31:0] $end
+      $attrbegin array unpacked bounds 1 $end
+      $scope sv_array out $end
+       $var wire 8 R# out[0] [7:0] $end
+       $var wire 8 S# out[1] [7:0] $end
+      $upscope $end
+     $upscope $end
     $upscope $end
    $upscope $end
   $upscope $end
   $scope module i_sub3_2 $end
-   $var parameter 8 F" P0 [7:0] $end
+   $var parameter 8 H" P0 [7:0] $end
    $attrbegin array unpacked bounds 1 $end
    $scope sv_array UNPACKED_ARRAY $end
-    $var parameter 32 Q# UNPACKED_ARRAY[0] [31:0] $end
-    $var parameter 32 R# UNPACKED_ARRAY[1] [31:0] $end
+    $var parameter 32 T# UNPACKED_ARRAY[0] [31:0] $end
+    $var parameter 32 U# UNPACKED_ARRAY[1] [31:0] $end
    $upscope $end
-   $var parameter 16 I" UNUSED [15:0] $end
+   $var parameter 16 K" UNUSED [15:0] $end
    $attrbegin misc 07 "" 1 $end
-   $var parameter 2 J" ENUM [1:0] $end
+   $var parameter 2 L" ENUM [1:0] $end
    $var wire 1 ! clk $end
    $var wire 8 ' in [7:0] $end
    $var wire 8 ) out [7:0] $end
-   $var logic 8 S# ff [7:0] $end
+   $var logic 8 V# ff [7:0] $end
    $var wire 8 ) out4 [7:0] $end
-   $var wire 8 T# out4_2 [7:0] $end
+   $var wire 8 W# out4_2 [7:0] $end
    $scope module i_sub4_0 $end
-    $var parameter 32 M" P0 [31:0] $end
-    $var real_parameter 64 N" P1 $end
-    $var real_parameter 64 O" P3 $end
+    $var parameter 32 O" P0 [31:0] $end
+    $var real_parameter 64 P" P1 $end
+    $var real_parameter 64 Q" P3 $end
     $var wire 1 ! clk $end
-    $var wire 8 S# in [7:0] $end
+    $var wire 8 X# in [7:0] $end
     $var wire 8 ) out [7:0] $end
     $var logic 8 ) ff [7:0] $end
     $attrbegin array unpacked bounds 1 $end
     $scope sv_array sub5_in $end
      $attrbegin array unpacked bounds 2 $end
      $scope sv_array [0] $end
-      $var logic 128 U# sub5_in[0][0] [127:0] $end
-      $var logic 128 V# sub5_in[0][1] [127:0] $end
-      $var logic 128 W# sub5_in[0][2] [127:0] $end
+      $var logic 128 Y# sub5_in[0][0] [127:0] $end
+      $var logic 128 Z# sub5_in[0][1] [127:0] $end
+      $var logic 128 [# sub5_in[0][2] [127:0] $end
      $upscope $end
      $attrbegin array unpacked bounds 2 $end
      $scope sv_array [1] $end
-      $var logic 128 X# sub5_in[1][0] [127:0] $end
-      $var logic 128 Y# sub5_in[1][1] [127:0] $end
-      $var logic 128 Z# sub5_in[1][2] [127:0] $end
+      $var logic 128 \# sub5_in[1][0] [127:0] $end
+      $var logic 128 ]# sub5_in[1][1] [127:0] $end
+      $var logic 128 ^# sub5_in[1][2] [127:0] $end
      $upscope $end
     $upscope $end
     $attrbegin array unpacked bounds 1 $end
     $scope sv_array sub5_out $end
      $attrbegin array unpacked bounds 2 $end
      $scope sv_array [0] $end
-      $var wire 8 [# sub5_out[0][0] [7:0] $end
-      $var wire 8 \# sub5_out[0][1] [7:0] $end
-      $var wire 8 ]# sub5_out[0][2] [7:0] $end
+      $var wire 8 _# sub5_out[0][0] [7:0] $end
+      $var wire 8 `# sub5_out[0][1] [7:0] $end
+      $var wire 8 a# sub5_out[0][2] [7:0] $end
      $upscope $end
      $attrbegin array unpacked bounds 2 $end
      $scope sv_array [1] $end
-      $var wire 8 ^# sub5_out[1][0] [7:0] $end
-      $var wire 8 _# sub5_out[1][1] [7:0] $end
-      $var wire 8 `# sub5_out[1][2] [7:0] $end
+      $var wire 8 b# sub5_out[1][0] [7:0] $end
+      $var wire 8 c# sub5_out[1][1] [7:0] $end
+      $var wire 8 d# sub5_out[1][2] [7:0] $end
      $upscope $end
     $upscope $end
-    $var int 32 a# count [31:0] $end
-    $var int 32 b# driven_from_bind [31:0] $end
+    $var int 32 e# count [31:0] $end
+    $var int 32 f# driven_from_bind [31:0] $end
     $scope module i_sub4_bound $end
-     $var real_parameter 64 N" P1 $end
-     $var wire 32 b# driven_from_bind [31:0] $end
+     $var real_parameter 64 P" P1 $end
+     $var wire 32 f# driven_from_bind [31:0] $end
     $upscope $end
     $scope module i_sub5 $end
-     $var wire 1 c# clk $end
+     $var wire 1 g# clk $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array in $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [0] $end
-       $var wire 128 d# in[0][0] [127:0] $end
-       $var wire 128 e# in[0][1] [127:0] $end
-       $var wire 128 f# in[0][2] [127:0] $end
+       $var wire 128 h# in[0][0] [127:0] $end
+       $var wire 128 i# in[0][1] [127:0] $end
+       $var wire 128 j# in[0][2] [127:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [1] $end
-       $var wire 128 g# in[1][0] [127:0] $end
-       $var wire 128 h# in[1][1] [127:0] $end
-       $var wire 128 i# in[1][2] [127:0] $end
+       $var wire 128 k# in[1][0] [127:0] $end
+       $var wire 128 l# in[1][1] [127:0] $end
+       $var wire 128 m# in[1][2] [127:0] $end
       $upscope $end
      $upscope $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array out $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [0] $end
-       $var wire 8 j# out[0][0] [7:0] $end
-       $var wire 8 k# out[0][1] [7:0] $end
-       $var wire 8 l# out[0][2] [7:0] $end
+       $var wire 8 n# out[0][0] [7:0] $end
+       $var wire 8 o# out[0][1] [7:0] $end
+       $var wire 8 p# out[0][2] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [1] $end
-       $var wire 8 m# out[1][0] [7:0] $end
-       $var wire 8 n# out[1][1] [7:0] $end
-       $var wire 8 o# out[1][2] [7:0] $end
+       $var wire 8 q# out[1][0] [7:0] $end
+       $var wire 8 r# out[1][1] [7:0] $end
+       $var wire 8 s# out[1][2] [7:0] $end
       $upscope $end
      $upscope $end
-     $var int 32 p# count [31:0] $end
+     $var int 32 t# count [31:0] $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array val0 $end
-      $var wire 8 q# val0[0] [7:0] $end
-      $var wire 8 r# val0[1] [7:0] $end
+      $var wire 8 u# val0[0] [7:0] $end
+      $var wire 8 v# val0[1] [7:0] $end
      $upscope $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array val1 $end
-      $var wire 8 s# val1[0] [7:0] $end
-      $var wire 8 t# val1[1] [7:0] $end
+      $var wire 8 w# val1[0] [7:0] $end
+      $var wire 8 x# val1[1] [7:0] $end
      $upscope $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array val2 $end
-      $var wire 8 u# val2[0] [7:0] $end
-      $var wire 8 v# val2[1] [7:0] $end
+      $var wire 8 y# val2[0] [7:0] $end
+      $var wire 8 z# val2[1] [7:0] $end
      $upscope $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array val3 $end
-      $var wire 8 w# val3[0] [7:0] $end
-      $var wire 8 x# val3[1] [7:0] $end
+      $var wire 8 {# val3[0] [7:0] $end
+      $var wire 8 |# val3[1] [7:0] $end
      $upscope $end
      $scope module i_sub0 $end
-      $var parameter 32 y# P0 [31:0] $end
-      $var parameter 32 z# P1 [31:0] $end
-      $attrbegin array unpacked bounds 1 $end
-      $scope sv_array out $end
-       $var wire 8 {# out[0] [7:0] $end
-       $var wire 8 |# out[1] [7:0] $end
-      $upscope $end
-     $upscope $end
-     $scope module i_sub1 $end
-      $var parameter 32 y# P0 [31:0] $end
-      $var parameter 32 z# P1 [31:0] $end
-      $attrbegin array unpacked bounds 1 $end
-      $scope sv_array out $end
-       $var wire 8 }# out[0] [7:0] $end
-       $var wire 8 ~# out[1] [7:0] $end
-      $upscope $end
-     $upscope $end
-     $scope module i_sub2 $end
-      $var parameter 32 y# P0 [31:0] $end
-      $var parameter 32 z# P1 [31:0] $end
+      $var parameter 32 }# P0 [31:0] $end
+      $var parameter 32 ~# P1 [31:0] $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array out $end
        $var wire 8 !$ out[0] [7:0] $end
        $var wire 8 "$ out[1] [7:0] $end
       $upscope $end
      $upscope $end
-     $scope module i_sub3 $end
-      $var parameter 32 y# P0 [31:0] $end
-      $var parameter 32 #$ P1 [31:0] $end
+     $scope module i_sub1 $end
+      $var parameter 32 }# P0 [31:0] $end
+      $var parameter 32 ~# P1 [31:0] $end
       $attrbegin array unpacked bounds 1 $end
       $scope sv_array out $end
-       $var wire 8 $$ out[0] [7:0] $end
-       $var wire 8 %$ out[1] [7:0] $end
+       $var wire 8 #$ out[0] [7:0] $end
+       $var wire 8 $$ out[1] [7:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module i_sub2 $end
+      $var parameter 32 }# P0 [31:0] $end
+      $var parameter 32 ~# P1 [31:0] $end
+      $attrbegin array unpacked bounds 1 $end
+      $scope sv_array out $end
+       $var wire 8 %$ out[0] [7:0] $end
+       $var wire 8 &$ out[1] [7:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module i_sub3 $end
+      $var parameter 32 }# P0 [31:0] $end
+      $var parameter 32 '$ P1 [31:0] $end
+      $attrbegin array unpacked bounds 1 $end
+      $scope sv_array out $end
+       $var wire 8 ($ out[0] [7:0] $end
+       $var wire 8 )$ out[1] [7:0] $end
       $upscope $end
      $upscope $end
     $upscope $end
    $upscope $end
    $scope module i_sub4_1 $end
-    $var parameter 32 M" P0 [31:0] $end
-    $var real_parameter 64 N" P1 $end
-    $var real_parameter 64 !# P3 $end
+    $var parameter 32 O" P0 [31:0] $end
+    $var real_parameter 64 P" P1 $end
+    $var real_parameter 64 $# P3 $end
     $var wire 1 ! clk $end
-    $var wire 8 S# in [7:0] $end
-    $var wire 8 T# out [7:0] $end
-    $var logic 8 T# ff [7:0] $end
+    $var wire 8 X# in [7:0] $end
+    $var wire 8 W# out [7:0] $end
+    $var logic 8 W# ff [7:0] $end
     $attrbegin array unpacked bounds 1 $end
     $scope sv_array sub5_in $end
      $attrbegin array unpacked bounds 2 $end
      $scope sv_array [0] $end
-      $var logic 128 &$ sub5_in[0][0] [127:0] $end
-      $var logic 128 '$ sub5_in[0][1] [127:0] $end
-      $var logic 128 ($ sub5_in[0][2] [127:0] $end
+      $var logic 128 *$ sub5_in[0][0] [127:0] $end
+      $var logic 128 +$ sub5_in[0][1] [127:0] $end
+      $var logic 128 ,$ sub5_in[0][2] [127:0] $end
      $upscope $end
      $attrbegin array unpacked bounds 2 $end
      $scope sv_array [1] $end
-      $var logic 128 )$ sub5_in[1][0] [127:0] $end
-      $var logic 128 *$ sub5_in[1][1] [127:0] $end
-      $var logic 128 +$ sub5_in[1][2] [127:0] $end
+      $var logic 128 -$ sub5_in[1][0] [127:0] $end
+      $var logic 128 .$ sub5_in[1][1] [127:0] $end
+      $var logic 128 /$ sub5_in[1][2] [127:0] $end
      $upscope $end
     $upscope $end
     $attrbegin array unpacked bounds 1 $end
     $scope sv_array sub5_out $end
      $attrbegin array unpacked bounds 2 $end
      $scope sv_array [0] $end
-      $var wire 8 ,$ sub5_out[0][0] [7:0] $end
-      $var wire 8 -$ sub5_out[0][1] [7:0] $end
-      $var wire 8 .$ sub5_out[0][2] [7:0] $end
+      $var wire 8 0$ sub5_out[0][0] [7:0] $end
+      $var wire 8 1$ sub5_out[0][1] [7:0] $end
+      $var wire 8 2$ sub5_out[0][2] [7:0] $end
      $upscope $end
      $attrbegin array unpacked bounds 2 $end
      $scope sv_array [1] $end
-      $var wire 8 /$ sub5_out[1][0] [7:0] $end
-      $var wire 8 0$ sub5_out[1][1] [7:0] $end
-      $var wire 8 1$ sub5_out[1][2] [7:0] $end
+      $var wire 8 3$ sub5_out[1][0] [7:0] $end
+      $var wire 8 4$ sub5_out[1][1] [7:0] $end
+      $var wire 8 5$ sub5_out[1][2] [7:0] $end
      $upscope $end
     $upscope $end
-    $var int 32 2$ count [31:0] $end
-    $var int 32 3$ driven_from_bind [31:0] $end
+    $var int 32 6$ count [31:0] $end
+    $var int 32 7$ driven_from_bind [31:0] $end
     $scope module i_sub4_bound $end
-     $var real_parameter 64 N" P1 $end
-     $var wire 32 3$ driven_from_bind [31:0] $end
+     $var real_parameter 64 P" P1 $end
+     $var wire 32 7$ driven_from_bind [31:0] $end
     $upscope $end
     $scope module i_sub5 $end
-     $var wire 1 4$ clk $end
+     $var wire 1 8$ clk $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array in $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [0] $end
-       $var wire 128 5$ in[0][0] [127:0] $end
-       $var wire 128 6$ in[0][1] [127:0] $end
-       $var wire 128 7$ in[0][2] [127:0] $end
+       $var wire 128 9$ in[0][0] [127:0] $end
+       $var wire 128 :$ in[0][1] [127:0] $end
+       $var wire 128 ;$ in[0][2] [127:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [1] $end
-       $var wire 128 8$ in[1][0] [127:0] $end
-       $var wire 128 9$ in[1][1] [127:0] $end
-       $var wire 128 :$ in[1][2] [127:0] $end
+       $var wire 128 <$ in[1][0] [127:0] $end
+       $var wire 128 =$ in[1][1] [127:0] $end
+       $var wire 128 >$ in[1][2] [127:0] $end
       $upscope $end
      $upscope $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array out $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [0] $end
-       $var wire 8 ;$ out[0][0] [7:0] $end
-       $var wire 8 <$ out[0][1] [7:0] $end
-       $var wire 8 =$ out[0][2] [7:0] $end
+       $var wire 8 ?$ out[0][0] [7:0] $end
+       $var wire 8 @$ out[0][1] [7:0] $end
+       $var wire 8 A$ out[0][2] [7:0] $end
       $upscope $end
       $attrbegin array unpacked bounds 2 $end
       $scope sv_array [1] $end
-       $var wire 8 >$ out[1][0] [7:0] $end
-       $var wire 8 ?$ out[1][1] [7:0] $end
-       $var wire 8 @$ out[1][2] [7:0] $end
+       $var wire 8 B$ out[1][0] [7:0] $end
+       $var wire 8 C$ out[1][1] [7:0] $end
+       $var wire 8 D$ out[1][2] [7:0] $end
       $upscope $end
      $upscope $end
-     $var int 32 A$ count [31:0] $end
+     $var int 32 E$ count [31:0] $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array val0 $end
-      $var wire 8 B$ val0[0] [7:0] $end
-      $var wire 8 C$ val0[1] [7:0] $end
+      $var wire 8 F$ val0[0] [7:0] $end
+      $var wire 8 G$ val0[1] [7:0] $end
      $upscope $end
      $attrbegin array unpacked bounds 1 $end
      $scope sv_array val1 $end
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-      $var wire 8 E$ val1[1] [7:0] $end
+      $var wire 8 H$ val1[0] [7:0] $end
+      $var wire 8 I$ val1[1] [7:0] $end
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-      $var wire 8 F$ val2[0] [7:0] $end
-      $var wire 8 G$ val2[1] [7:0] $end
+      $var wire 8 J$ val2[0] [7:0] $end
+      $var wire 8 K$ val2[1] [7:0] $end
      $upscope $end
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-      $var wire 8 I$ val3[1] [7:0] $end
+      $var wire 8 L$ val3[0] [7:0] $end
+      $var wire 8 M$ val3[1] [7:0] $end
      $upscope $end
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-      $var parameter 32 J$ P0 [31:0] $end
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-       $var wire 8 O$ out[1] [7:0] $end
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-     $upscope $end
-     $scope module i_sub2 $end
-      $var parameter 32 J$ P0 [31:0] $end
-      $var parameter 32 K$ P1 [31:0] $end
+      $var parameter 32 N$ P0 [31:0] $end
+      $var parameter 32 O$ P1 [31:0] $end
       $attrbegin array unpacked bounds 1 $end
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        $var wire 8 Q$ out[1] [7:0] $end
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-     $scope module i_sub3 $end
-      $var parameter 32 J$ P0 [31:0] $end
-      $var parameter 32 R$ P1 [31:0] $end
+     $scope module i_sub1 $end
+      $var parameter 32 N$ P0 [31:0] $end
+      $var parameter 32 O$ P1 [31:0] $end
       $attrbegin array unpacked bounds 1 $end
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-       $var wire 8 S$ out[0] [7:0] $end
-       $var wire 8 T$ out[1] [7:0] $end
+       $var wire 8 R$ out[0] [7:0] $end
+       $var wire 8 S$ out[1] [7:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module i_sub2 $end
+      $var parameter 32 N$ P0 [31:0] $end
+      $var parameter 32 O$ P1 [31:0] $end
+      $attrbegin array unpacked bounds 1 $end
+      $scope sv_array out $end
+       $var wire 8 T$ out[0] [7:0] $end
+       $var wire 8 U$ out[1] [7:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module i_sub3 $end
+      $var parameter 32 N$ P0 [31:0] $end
+      $var parameter 32 V$ P1 [31:0] $end
+      $attrbegin array unpacked bounds 1 $end
+      $scope sv_array out $end
+       $var wire 8 W$ out[0] [7:0] $end
+       $var wire 8 X$ out[1] [7:0] $end
       $upscope $end
      $upscope $end
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diff --git a/test_regress/t/t_trace_hier_block_notop_cc_vcd.out b/test_regress/t/t_trace_hier_block_notop_cc_vcd.out
index c5f91c035..3e537edfc 100644
--- a/test_regress/t/t_trace_hier_block_notop_cc_vcd.out
+++ b/test_regress/t/t_trace_hier_block_notop_cc_vcd.out
@@ -1,35 +1,35 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module $rootio $end
-  $var wire 1 Q! clk $end
+  $var wire 1 U! clk $end
  $upscope $end
  $scope module stateless_pkg $end
-  $var wire 32 h! ONE [31:0] $end
+  $var wire 32 j! ONE [31:0] $end
  $upscope $end
  $scope module t $end
-  $var wire 32 T! PARAM_A [31:0] $end
-  $var wire 32 U! PARAM_B [31:0] $end
-  $var wire 1 Q! clk $end
-  $var wire 8 6! out0 [7:0] $end
-  $var wire 8 7! out1 [7:0] $end
-  $var wire 8 8! out2 [7:0] $end
-  $var wire 8 R! out3 [7:0] $end
+  $var wire 32 V! PARAM_A [31:0] $end
+  $var wire 32 W! PARAM_B [31:0] $end
+  $var wire 1 U! clk $end
+  $var wire 8 :! out0 [7:0] $end
+  $var wire 8 ;! out1 [7:0] $end
+  $var wire 8 <! out2 [7:0] $end
+  $var wire 8 7! out3 [7:0] $end
   $var wire 8 & out3_2 [7:0] $end
   $var wire 8 ' out5 [7:0] $end
   $var wire 8 ( out6 [7:0] $end
   $var wire 32 ) count [31:0] $end
   $scope module i_delay0 $end
-   $var wire 32 V! N [31:0] $end
-   $var wire 32 W! WIDTH [31:0] $end
-   $var wire 1 Q! clk $end
-   $var wire 8 R! in [7:0] $end
+   $var wire 32 X! N [31:0] $end
+   $var wire 32 Y! WIDTH [31:0] $end
+   $var wire 1 U! clk $end
+   $var wire 8 7! in [7:0] $end
    $var wire 8 ' out [7:0] $end
    $var wire 8 * tmp [7:0] $end
    $scope module genblk1 $end
     $scope module i_delay $end
-     $var wire 32 X! N [31:0] $end
-     $var wire 32 W! WIDTH [31:0] $end
-     $var wire 1 Q! clk $end
+     $var wire 32 Z! N [31:0] $end
+     $var wire 32 Y! WIDTH [31:0] $end
+     $var wire 1 U! clk $end
      $var wire 8 * in [7:0] $end
      $var wire 8 ' out [7:0] $end
      $var wire 8 ' tmp [7:0] $end
@@ -37,25 +37,25 @@ $timescale 1ps $end
    $upscope $end
   $upscope $end
   $scope module i_delay1 $end
-   $var wire 32 Y! N [31:0] $end
-   $var wire 32 W! WIDTH [31:0] $end
-   $var wire 1 Q! clk $end
+   $var wire 32 [! N [31:0] $end
+   $var wire 32 Y! WIDTH [31:0] $end
+   $var wire 1 U! clk $end
    $var wire 8 ' in [7:0] $end
    $var wire 8 ( out [7:0] $end
    $var wire 8 + tmp [7:0] $end
    $scope module genblk1 $end
     $scope module i_delay $end
-     $var wire 32 V! N [31:0] $end
-     $var wire 32 W! WIDTH [31:0] $end
-     $var wire 1 Q! clk $end
+     $var wire 32 X! N [31:0] $end
+     $var wire 32 Y! WIDTH [31:0] $end
+     $var wire 1 U! clk $end
      $var wire 8 + in [7:0] $end
      $var wire 8 ( out [7:0] $end
      $var wire 8 , tmp [7:0] $end
      $scope module genblk1 $end
       $scope module i_delay $end
-       $var wire 32 X! N [31:0] $end
-       $var wire 32 W! WIDTH [31:0] $end
-       $var wire 1 Q! clk $end
+       $var wire 32 Z! N [31:0] $end
+       $var wire 32 Y! WIDTH [31:0] $end
+       $var wire 1 U! clk $end
        $var wire 8 , in [7:0] $end
        $var wire 8 ( out [7:0] $end
        $var wire 8 ( tmp [7:0] $end
@@ -65,470 +65,470 @@ $timescale 1ps $end
    $upscope $end
   $upscope $end
   $scope module i_sub0 $end
-   $var wire 1 Q! clk $end
-   $var wire 8 R! in [7:0] $end
-   $var wire 8 6! out [7:0] $end
+   $var wire 1 U! clk $end
+   $var wire 8 7! in [7:0] $end
+   $var wire 8 :! out [7:0] $end
    $scope module i_sub0 $end
-    $var wire 1 i! clk $end
-    $var wire 8 j! in [7:0] $end
-    $var wire 8 k! out [7:0] $end
-    $var wire 8 l! ff [7:0] $end
+    $var wire 1 k! clk $end
+    $var wire 8 l! in [7:0] $end
+    $var wire 8 m! out [7:0] $end
+    $var wire 8 n! ff [7:0] $end
    $upscope $end
   $upscope $end
   $scope module i_sub1 $end
-   $var wire 1 m! clk $end
-   $var wire 8 n! in [11:4] $end
-   $var wire 8 o! out [7:0] $end
-   $var wire 8 p! ff [7:0] $end
-   $var wire 2 q! enum_v [1:0] $end
+   $var wire 1 o! clk $end
+   $var wire 8 p! in [11:4] $end
+   $var wire 8 q! out [7:0] $end
+   $var wire 8 r! ff [7:0] $end
+   $var wire 2 s! enum_v [1:0] $end
   $upscope $end
   $scope module i_sub2 $end
-   $var wire 1 >% clk $end
-   $var wire 8 ?% in [7:0] $end
-   $var wire 8 @% out [7:0] $end
-   $var wire 8 X" ff [7:0] $end
-   $var wire 2 Y" alt_enum_v [1:0] $end
+   $var wire 1 B% clk $end
+   $var wire 8 C% in [7:0] $end
+   $var wire 8 D% out [7:0] $end
+   $var wire 8 Z" ff [7:0] $end
+   $var wire 2 [" alt_enum_v [1:0] $end
    $scope module i_sub3 $end
-    $var wire 8 X" in_wire [7:0] $end
-    $var wire 8 Z" out_1 [7:0] $end
-    $var wire 8 [" out_2 [7:0] $end
+    $var wire 8 Z" in_wire [7:0] $end
+    $var wire 8 \" out_1 [7:0] $end
+    $var wire 8 ]" out_2 [7:0] $end
     $scope module i_sub3 $end
-     $var wire 8 A% P0 [7:0] $end
-     $var wire 32 B% UNPACKED_ARRAY[0] [31:0] $end
-     $var wire 32 C% UNPACKED_ARRAY[1] [31:0] $end
-     $var wire 16 D% UNUSED [15:0] $end
-     $var wire 2 E% ENUM [1:0] $end
-     $var wire 1 >% clk $end
-     $var wire 8 X" in [7:0] $end
-     $var wire 8 Z" out [7:0] $end
-     $var wire 8 \" ff [7:0] $end
-     $var wire 8 Z" out4 [7:0] $end
-     $var wire 8 ]" out4_2 [7:0] $end
+     $var wire 8 E% P0 [7:0] $end
+     $var wire 32 F% UNPACKED_ARRAY[0] [31:0] $end
+     $var wire 32 G% UNPACKED_ARRAY[1] [31:0] $end
+     $var wire 16 H% UNUSED [15:0] $end
+     $var wire 2 I% ENUM [1:0] $end
+     $var wire 1 B% clk $end
+     $var wire 8 Z" in [7:0] $end
+     $var wire 8 \" out [7:0] $end
+     $var wire 8 ^" ff [7:0] $end
+     $var wire 8 \" out4 [7:0] $end
+     $var wire 8 _" out4_2 [7:0] $end
      $scope module i_sub4_0 $end
-      $var wire 32 F% P0 [31:0] $end
-      $var real 64 G% P1 $end
-      $var real 64 I% P3 $end
-      $var wire 1 >% clk $end
-      $var wire 8 \" in [7:0] $end
-      $var wire 8 Z" out [7:0] $end
-      $var wire 8 Z" ff [7:0] $end
-      $var wire 128 ^" sub5_in[0][0] [127:0] $end
-      $var wire 128 b" sub5_in[0][1] [127:0] $end
-      $var wire 128 f" sub5_in[0][2] [127:0] $end
-      $var wire 128 j" sub5_in[1][0] [127:0] $end
-      $var wire 128 n" sub5_in[1][1] [127:0] $end
-      $var wire 128 r" sub5_in[1][2] [127:0] $end
-      $var wire 8 v" sub5_out[0][0] [7:0] $end
-      $var wire 8 w" sub5_out[0][1] [7:0] $end
-      $var wire 8 x" sub5_out[0][2] [7:0] $end
-      $var wire 8 y" sub5_out[1][0] [7:0] $end
-      $var wire 8 z" sub5_out[1][1] [7:0] $end
-      $var wire 8 {" sub5_out[1][2] [7:0] $end
-      $var wire 32 |" count [31:0] $end
-      $var wire 32 r! driven_from_bind [31:0] $end
+      $var wire 32 J% P0 [31:0] $end
+      $var real 64 K% P1 $end
+      $var real 64 M% P3 $end
+      $var wire 1 B% clk $end
+      $var wire 8 `" in [7:0] $end
+      $var wire 8 \" out [7:0] $end
+      $var wire 8 \" ff [7:0] $end
+      $var wire 128 a" sub5_in[0][0] [127:0] $end
+      $var wire 128 e" sub5_in[0][1] [127:0] $end
+      $var wire 128 i" sub5_in[0][2] [127:0] $end
+      $var wire 128 m" sub5_in[1][0] [127:0] $end
+      $var wire 128 q" sub5_in[1][1] [127:0] $end
+      $var wire 128 u" sub5_in[1][2] [127:0] $end
+      $var wire 8 y" sub5_out[0][0] [7:0] $end
+      $var wire 8 z" sub5_out[0][1] [7:0] $end
+      $var wire 8 {" sub5_out[0][2] [7:0] $end
+      $var wire 8 |" sub5_out[1][0] [7:0] $end
+      $var wire 8 }" sub5_out[1][1] [7:0] $end
+      $var wire 8 ~" sub5_out[1][2] [7:0] $end
+      $var wire 32 !# count [31:0] $end
+      $var wire 32 t! driven_from_bind [31:0] $end
       $scope module i_sub4_bound $end
-       $var real 64 G% P1 $end
-       $var wire 32 r! driven_from_bind [31:0] $end
+       $var real 64 K% P1 $end
+       $var wire 32 t! driven_from_bind [31:0] $end
       $upscope $end
       $scope module i_sub5 $end
-       $var wire 1 >% clk $end
-       $var wire 128 }" in[0][0] [127:0] $end
-       $var wire 128 ## in[0][1] [127:0] $end
-       $var wire 128 '# in[0][2] [127:0] $end
-       $var wire 128 +# in[1][0] [127:0] $end
-       $var wire 128 /# in[1][1] [127:0] $end
-       $var wire 128 3# in[1][2] [127:0] $end
-       $var wire 8 7# out[0][0] [7:0] $end
-       $var wire 8 8# out[0][1] [7:0] $end
-       $var wire 8 9# out[0][2] [7:0] $end
-       $var wire 8 :# out[1][0] [7:0] $end
-       $var wire 8 ;# out[1][1] [7:0] $end
-       $var wire 8 <# out[1][2] [7:0] $end
-       $var wire 32 =# count [31:0] $end
-       $var wire 8 s! val0[0] [7:0] $end
-       $var wire 8 t! val0[1] [7:0] $end
-       $var wire 8 u! val1[0] [7:0] $end
-       $var wire 8 v! val1[1] [7:0] $end
-       $var wire 8 w! val2[0] [7:0] $end
-       $var wire 8 x! val2[1] [7:0] $end
-       $var wire 8 y! val3[0] [7:0] $end
-       $var wire 8 z! val3[1] [7:0] $end
+       $var wire 1 B% clk $end
+       $var wire 128 "# in[0][0] [127:0] $end
+       $var wire 128 &# in[0][1] [127:0] $end
+       $var wire 128 *# in[0][2] [127:0] $end
+       $var wire 128 .# in[1][0] [127:0] $end
+       $var wire 128 2# in[1][1] [127:0] $end
+       $var wire 128 6# in[1][2] [127:0] $end
+       $var wire 8 :# out[0][0] [7:0] $end
+       $var wire 8 ;# out[0][1] [7:0] $end
+       $var wire 8 <# out[0][2] [7:0] $end
+       $var wire 8 =# out[1][0] [7:0] $end
+       $var wire 8 ># out[1][1] [7:0] $end
+       $var wire 8 ?# out[1][2] [7:0] $end
+       $var wire 32 @# count [31:0] $end
+       $var wire 8 u! val0[0] [7:0] $end
+       $var wire 8 v! val0[1] [7:0] $end
+       $var wire 8 w! val1[0] [7:0] $end
+       $var wire 8 x! val1[1] [7:0] $end
+       $var wire 8 y! val2[0] [7:0] $end
+       $var wire 8 z! val2[1] [7:0] $end
+       $var wire 8 {! val3[0] [7:0] $end
+       $var wire 8 |! val3[1] [7:0] $end
        $scope module i_sub0 $end
-        $var wire 32 K% P0 [31:0] $end
-        $var wire 32 L% P1 [31:0] $end
-        $var wire 8 {! out[0] [7:0] $end
-        $var wire 8 |! out[1] [7:0] $end
-       $upscope $end
-       $scope module i_sub1 $end
-        $var wire 32 K% P0 [31:0] $end
-        $var wire 32 L% P1 [31:0] $end
+        $var wire 32 O% P0 [31:0] $end
+        $var wire 32 P% P1 [31:0] $end
         $var wire 8 }! out[0] [7:0] $end
         $var wire 8 ~! out[1] [7:0] $end
        $upscope $end
-       $scope module i_sub2 $end
-        $var wire 32 K% P0 [31:0] $end
-        $var wire 32 L% P1 [31:0] $end
+       $scope module i_sub1 $end
+        $var wire 32 O% P0 [31:0] $end
+        $var wire 32 P% P1 [31:0] $end
         $var wire 8 !" out[0] [7:0] $end
         $var wire 8 "" out[1] [7:0] $end
        $upscope $end
-       $scope module i_sub3 $end
-        $var wire 32 K% P0 [31:0] $end
-        $var wire 32 M% P1 [31:0] $end
+       $scope module i_sub2 $end
+        $var wire 32 O% P0 [31:0] $end
+        $var wire 32 P% P1 [31:0] $end
         $var wire 8 #" out[0] [7:0] $end
         $var wire 8 $" out[1] [7:0] $end
        $upscope $end
+       $scope module i_sub3 $end
+        $var wire 32 O% P0 [31:0] $end
+        $var wire 32 Q% P1 [31:0] $end
+        $var wire 8 %" out[0] [7:0] $end
+        $var wire 8 &" out[1] [7:0] $end
+       $upscope $end
       $upscope $end
      $upscope $end
      $scope module i_sub4_1 $end
-      $var wire 32 F% P0 [31:0] $end
-      $var real 64 G% P1 $end
-      $var real 64 N% P3 $end
-      $var wire 1 >% clk $end
-      $var wire 8 \" in [7:0] $end
-      $var wire 8 ]" out [7:0] $end
-      $var wire 8 ]" ff [7:0] $end
-      $var wire 128 ># sub5_in[0][0] [127:0] $end
-      $var wire 128 B# sub5_in[0][1] [127:0] $end
-      $var wire 128 F# sub5_in[0][2] [127:0] $end
-      $var wire 128 J# sub5_in[1][0] [127:0] $end
-      $var wire 128 N# sub5_in[1][1] [127:0] $end
-      $var wire 128 R# sub5_in[1][2] [127:0] $end
-      $var wire 8 V# sub5_out[0][0] [7:0] $end
-      $var wire 8 W# sub5_out[0][1] [7:0] $end
-      $var wire 8 X# sub5_out[0][2] [7:0] $end
-      $var wire 8 Y# sub5_out[1][0] [7:0] $end
-      $var wire 8 Z# sub5_out[1][1] [7:0] $end
-      $var wire 8 [# sub5_out[1][2] [7:0] $end
-      $var wire 32 \# count [31:0] $end
-      $var wire 32 %" driven_from_bind [31:0] $end
+      $var wire 32 J% P0 [31:0] $end
+      $var real 64 K% P1 $end
+      $var real 64 R% P3 $end
+      $var wire 1 B% clk $end
+      $var wire 8 `" in [7:0] $end
+      $var wire 8 _" out [7:0] $end
+      $var wire 8 _" ff [7:0] $end
+      $var wire 128 A# sub5_in[0][0] [127:0] $end
+      $var wire 128 E# sub5_in[0][1] [127:0] $end
+      $var wire 128 I# sub5_in[0][2] [127:0] $end
+      $var wire 128 M# sub5_in[1][0] [127:0] $end
+      $var wire 128 Q# sub5_in[1][1] [127:0] $end
+      $var wire 128 U# sub5_in[1][2] [127:0] $end
+      $var wire 8 Y# sub5_out[0][0] [7:0] $end
+      $var wire 8 Z# sub5_out[0][1] [7:0] $end
+      $var wire 8 [# sub5_out[0][2] [7:0] $end
+      $var wire 8 \# sub5_out[1][0] [7:0] $end
+      $var wire 8 ]# sub5_out[1][1] [7:0] $end
+      $var wire 8 ^# sub5_out[1][2] [7:0] $end
+      $var wire 32 _# count [31:0] $end
+      $var wire 32 '" driven_from_bind [31:0] $end
       $scope module i_sub4_bound $end
-       $var real 64 G% P1 $end
-       $var wire 32 %" driven_from_bind [31:0] $end
+       $var real 64 K% P1 $end
+       $var wire 32 '" driven_from_bind [31:0] $end
       $upscope $end
       $scope module i_sub5 $end
-       $var wire 1 >% clk $end
-       $var wire 128 ]# in[0][0] [127:0] $end
-       $var wire 128 a# in[0][1] [127:0] $end
-       $var wire 128 e# in[0][2] [127:0] $end
-       $var wire 128 i# in[1][0] [127:0] $end
-       $var wire 128 m# in[1][1] [127:0] $end
-       $var wire 128 q# in[1][2] [127:0] $end
-       $var wire 8 u# out[0][0] [7:0] $end
-       $var wire 8 v# out[0][1] [7:0] $end
-       $var wire 8 w# out[0][2] [7:0] $end
-       $var wire 8 x# out[1][0] [7:0] $end
-       $var wire 8 y# out[1][1] [7:0] $end
-       $var wire 8 z# out[1][2] [7:0] $end
-       $var wire 32 {# count [31:0] $end
-       $var wire 8 &" val0[0] [7:0] $end
-       $var wire 8 '" val0[1] [7:0] $end
-       $var wire 8 (" val1[0] [7:0] $end
-       $var wire 8 )" val1[1] [7:0] $end
-       $var wire 8 *" val2[0] [7:0] $end
-       $var wire 8 +" val2[1] [7:0] $end
-       $var wire 8 ," val3[0] [7:0] $end
-       $var wire 8 -" val3[1] [7:0] $end
+       $var wire 1 B% clk $end
+       $var wire 128 `# in[0][0] [127:0] $end
+       $var wire 128 d# in[0][1] [127:0] $end
+       $var wire 128 h# in[0][2] [127:0] $end
+       $var wire 128 l# in[1][0] [127:0] $end
+       $var wire 128 p# in[1][1] [127:0] $end
+       $var wire 128 t# in[1][2] [127:0] $end
+       $var wire 8 x# out[0][0] [7:0] $end
+       $var wire 8 y# out[0][1] [7:0] $end
+       $var wire 8 z# out[0][2] [7:0] $end
+       $var wire 8 {# out[1][0] [7:0] $end
+       $var wire 8 |# out[1][1] [7:0] $end
+       $var wire 8 }# out[1][2] [7:0] $end
+       $var wire 32 ~# count [31:0] $end
+       $var wire 8 (" val0[0] [7:0] $end
+       $var wire 8 )" val0[1] [7:0] $end
+       $var wire 8 *" val1[0] [7:0] $end
+       $var wire 8 +" val1[1] [7:0] $end
+       $var wire 8 ," val2[0] [7:0] $end
+       $var wire 8 -" val2[1] [7:0] $end
+       $var wire 8 ." val3[0] [7:0] $end
+       $var wire 8 /" val3[1] [7:0] $end
        $scope module i_sub0 $end
-        $var wire 32 K% P0 [31:0] $end
-        $var wire 32 L% P1 [31:0] $end
-        $var wire 8 ." out[0] [7:0] $end
-        $var wire 8 /" out[1] [7:0] $end
-       $upscope $end
-       $scope module i_sub1 $end
-        $var wire 32 K% P0 [31:0] $end
-        $var wire 32 L% P1 [31:0] $end
+        $var wire 32 O% P0 [31:0] $end
+        $var wire 32 P% P1 [31:0] $end
         $var wire 8 0" out[0] [7:0] $end
         $var wire 8 1" out[1] [7:0] $end
        $upscope $end
-       $scope module i_sub2 $end
-        $var wire 32 K% P0 [31:0] $end
-        $var wire 32 L% P1 [31:0] $end
+       $scope module i_sub1 $end
+        $var wire 32 O% P0 [31:0] $end
+        $var wire 32 P% P1 [31:0] $end
         $var wire 8 2" out[0] [7:0] $end
         $var wire 8 3" out[1] [7:0] $end
        $upscope $end
-       $scope module i_sub3 $end
-        $var wire 32 K% P0 [31:0] $end
-        $var wire 32 M% P1 [31:0] $end
+       $scope module i_sub2 $end
+        $var wire 32 O% P0 [31:0] $end
+        $var wire 32 P% P1 [31:0] $end
         $var wire 8 4" out[0] [7:0] $end
         $var wire 8 5" out[1] [7:0] $end
        $upscope $end
+       $scope module i_sub3 $end
+        $var wire 32 O% P0 [31:0] $end
+        $var wire 32 Q% P1 [31:0] $end
+        $var wire 8 6" out[0] [7:0] $end
+        $var wire 8 7" out[1] [7:0] $end
+       $upscope $end
       $upscope $end
      $upscope $end
     $upscope $end
     $scope module i_sub3_2 $end
-     $var wire 8 A% P0 [7:0] $end
-     $var wire 32 P% UNPACKED_ARRAY[0] [31:0] $end
-     $var wire 32 Q% UNPACKED_ARRAY[1] [31:0] $end
-     $var wire 16 D% UNUSED [15:0] $end
-     $var wire 2 E% ENUM [1:0] $end
-     $var wire 1 >% clk $end
-     $var wire 8 X" in [7:0] $end
-     $var wire 8 [" out [7:0] $end
-     $var wire 8 |# ff [7:0] $end
-     $var wire 8 [" out4 [7:0] $end
-     $var wire 8 }# out4_2 [7:0] $end
+     $var wire 8 E% P0 [7:0] $end
+     $var wire 32 T% UNPACKED_ARRAY[0] [31:0] $end
+     $var wire 32 U% UNPACKED_ARRAY[1] [31:0] $end
+     $var wire 16 H% UNUSED [15:0] $end
+     $var wire 2 I% ENUM [1:0] $end
+     $var wire 1 B% clk $end
+     $var wire 8 Z" in [7:0] $end
+     $var wire 8 ]" out [7:0] $end
+     $var wire 8 !$ ff [7:0] $end
+     $var wire 8 ]" out4 [7:0] $end
+     $var wire 8 "$ out4_2 [7:0] $end
      $scope module i_sub4_0 $end
-      $var wire 32 F% P0 [31:0] $end
-      $var real 64 G% P1 $end
-      $var real 64 I% P3 $end
-      $var wire 1 >% clk $end
-      $var wire 8 |# in [7:0] $end
-      $var wire 8 [" out [7:0] $end
-      $var wire 8 [" ff [7:0] $end
-      $var wire 128 ~# sub5_in[0][0] [127:0] $end
-      $var wire 128 $$ sub5_in[0][1] [127:0] $end
-      $var wire 128 ($ sub5_in[0][2] [127:0] $end
-      $var wire 128 ,$ sub5_in[1][0] [127:0] $end
-      $var wire 128 0$ sub5_in[1][1] [127:0] $end
-      $var wire 128 4$ sub5_in[1][2] [127:0] $end
-      $var wire 8 8$ sub5_out[0][0] [7:0] $end
-      $var wire 8 9$ sub5_out[0][1] [7:0] $end
-      $var wire 8 :$ sub5_out[0][2] [7:0] $end
-      $var wire 8 ;$ sub5_out[1][0] [7:0] $end
-      $var wire 8 <$ sub5_out[1][1] [7:0] $end
-      $var wire 8 =$ sub5_out[1][2] [7:0] $end
-      $var wire 32 >$ count [31:0] $end
-      $var wire 32 6" driven_from_bind [31:0] $end
+      $var wire 32 J% P0 [31:0] $end
+      $var real 64 K% P1 $end
+      $var real 64 M% P3 $end
+      $var wire 1 B% clk $end
+      $var wire 8 #$ in [7:0] $end
+      $var wire 8 ]" out [7:0] $end
+      $var wire 8 ]" ff [7:0] $end
+      $var wire 128 $$ sub5_in[0][0] [127:0] $end
+      $var wire 128 ($ sub5_in[0][1] [127:0] $end
+      $var wire 128 ,$ sub5_in[0][2] [127:0] $end
+      $var wire 128 0$ sub5_in[1][0] [127:0] $end
+      $var wire 128 4$ sub5_in[1][1] [127:0] $end
+      $var wire 128 8$ sub5_in[1][2] [127:0] $end
+      $var wire 8 <$ sub5_out[0][0] [7:0] $end
+      $var wire 8 =$ sub5_out[0][1] [7:0] $end
+      $var wire 8 >$ sub5_out[0][2] [7:0] $end
+      $var wire 8 ?$ sub5_out[1][0] [7:0] $end
+      $var wire 8 @$ sub5_out[1][1] [7:0] $end
+      $var wire 8 A$ sub5_out[1][2] [7:0] $end
+      $var wire 32 B$ count [31:0] $end
+      $var wire 32 8" driven_from_bind [31:0] $end
       $scope module i_sub4_bound $end
-       $var real 64 G% P1 $end
-       $var wire 32 6" driven_from_bind [31:0] $end
+       $var real 64 K% P1 $end
+       $var wire 32 8" driven_from_bind [31:0] $end
       $upscope $end
       $scope module i_sub5 $end
-       $var wire 1 >% clk $end
-       $var wire 128 ?$ in[0][0] [127:0] $end
-       $var wire 128 C$ in[0][1] [127:0] $end
-       $var wire 128 G$ in[0][2] [127:0] $end
-       $var wire 128 K$ in[1][0] [127:0] $end
-       $var wire 128 O$ in[1][1] [127:0] $end
-       $var wire 128 S$ in[1][2] [127:0] $end
-       $var wire 8 W$ out[0][0] [7:0] $end
-       $var wire 8 X$ out[0][1] [7:0] $end
-       $var wire 8 Y$ out[0][2] [7:0] $end
-       $var wire 8 Z$ out[1][0] [7:0] $end
-       $var wire 8 [$ out[1][1] [7:0] $end
-       $var wire 8 \$ out[1][2] [7:0] $end
-       $var wire 32 ]$ count [31:0] $end
-       $var wire 8 7" val0[0] [7:0] $end
-       $var wire 8 8" val0[1] [7:0] $end
-       $var wire 8 9" val1[0] [7:0] $end
-       $var wire 8 :" val1[1] [7:0] $end
-       $var wire 8 ;" val2[0] [7:0] $end
-       $var wire 8 <" val2[1] [7:0] $end
-       $var wire 8 =" val3[0] [7:0] $end
-       $var wire 8 >" val3[1] [7:0] $end
+       $var wire 1 B% clk $end
+       $var wire 128 C$ in[0][0] [127:0] $end
+       $var wire 128 G$ in[0][1] [127:0] $end
+       $var wire 128 K$ in[0][2] [127:0] $end
+       $var wire 128 O$ in[1][0] [127:0] $end
+       $var wire 128 S$ in[1][1] [127:0] $end
+       $var wire 128 W$ in[1][2] [127:0] $end
+       $var wire 8 [$ out[0][0] [7:0] $end
+       $var wire 8 \$ out[0][1] [7:0] $end
+       $var wire 8 ]$ out[0][2] [7:0] $end
+       $var wire 8 ^$ out[1][0] [7:0] $end
+       $var wire 8 _$ out[1][1] [7:0] $end
+       $var wire 8 `$ out[1][2] [7:0] $end
+       $var wire 32 a$ count [31:0] $end
+       $var wire 8 9" val0[0] [7:0] $end
+       $var wire 8 :" val0[1] [7:0] $end
+       $var wire 8 ;" val1[0] [7:0] $end
+       $var wire 8 <" val1[1] [7:0] $end
+       $var wire 8 =" val2[0] [7:0] $end
+       $var wire 8 >" val2[1] [7:0] $end
+       $var wire 8 ?" val3[0] [7:0] $end
+       $var wire 8 @" val3[1] [7:0] $end
        $scope module i_sub0 $end
-        $var wire 32 K% P0 [31:0] $end
-        $var wire 32 L% P1 [31:0] $end
-        $var wire 8 ?" out[0] [7:0] $end
-        $var wire 8 @" out[1] [7:0] $end
-       $upscope $end
-       $scope module i_sub1 $end
-        $var wire 32 K% P0 [31:0] $end
-        $var wire 32 L% P1 [31:0] $end
+        $var wire 32 O% P0 [31:0] $end
+        $var wire 32 P% P1 [31:0] $end
         $var wire 8 A" out[0] [7:0] $end
         $var wire 8 B" out[1] [7:0] $end
        $upscope $end
-       $scope module i_sub2 $end
-        $var wire 32 K% P0 [31:0] $end
-        $var wire 32 L% P1 [31:0] $end
+       $scope module i_sub1 $end
+        $var wire 32 O% P0 [31:0] $end
+        $var wire 32 P% P1 [31:0] $end
         $var wire 8 C" out[0] [7:0] $end
         $var wire 8 D" out[1] [7:0] $end
        $upscope $end
-       $scope module i_sub3 $end
-        $var wire 32 K% P0 [31:0] $end
-        $var wire 32 M% P1 [31:0] $end
+       $scope module i_sub2 $end
+        $var wire 32 O% P0 [31:0] $end
+        $var wire 32 P% P1 [31:0] $end
         $var wire 8 E" out[0] [7:0] $end
         $var wire 8 F" out[1] [7:0] $end
        $upscope $end
+       $scope module i_sub3 $end
+        $var wire 32 O% P0 [31:0] $end
+        $var wire 32 Q% P1 [31:0] $end
+        $var wire 8 G" out[0] [7:0] $end
+        $var wire 8 H" out[1] [7:0] $end
+       $upscope $end
       $upscope $end
      $upscope $end
      $scope module i_sub4_1 $end
-      $var wire 32 F% P0 [31:0] $end
-      $var real 64 G% P1 $end
-      $var real 64 N% P3 $end
-      $var wire 1 >% clk $end
-      $var wire 8 |# in [7:0] $end
-      $var wire 8 }# out [7:0] $end
-      $var wire 8 }# ff [7:0] $end
-      $var wire 128 ^$ sub5_in[0][0] [127:0] $end
-      $var wire 128 b$ sub5_in[0][1] [127:0] $end
-      $var wire 128 f$ sub5_in[0][2] [127:0] $end
-      $var wire 128 j$ sub5_in[1][0] [127:0] $end
-      $var wire 128 n$ sub5_in[1][1] [127:0] $end
-      $var wire 128 r$ sub5_in[1][2] [127:0] $end
-      $var wire 8 v$ sub5_out[0][0] [7:0] $end
-      $var wire 8 w$ sub5_out[0][1] [7:0] $end
-      $var wire 8 x$ sub5_out[0][2] [7:0] $end
-      $var wire 8 y$ sub5_out[1][0] [7:0] $end
-      $var wire 8 z$ sub5_out[1][1] [7:0] $end
-      $var wire 8 {$ sub5_out[1][2] [7:0] $end
-      $var wire 32 |$ count [31:0] $end
-      $var wire 32 G" driven_from_bind [31:0] $end
+      $var wire 32 J% P0 [31:0] $end
+      $var real 64 K% P1 $end
+      $var real 64 R% P3 $end
+      $var wire 1 B% clk $end
+      $var wire 8 #$ in [7:0] $end
+      $var wire 8 "$ out [7:0] $end
+      $var wire 8 "$ ff [7:0] $end
+      $var wire 128 b$ sub5_in[0][0] [127:0] $end
+      $var wire 128 f$ sub5_in[0][1] [127:0] $end
+      $var wire 128 j$ sub5_in[0][2] [127:0] $end
+      $var wire 128 n$ sub5_in[1][0] [127:0] $end
+      $var wire 128 r$ sub5_in[1][1] [127:0] $end
+      $var wire 128 v$ sub5_in[1][2] [127:0] $end
+      $var wire 8 z$ sub5_out[0][0] [7:0] $end
+      $var wire 8 {$ sub5_out[0][1] [7:0] $end
+      $var wire 8 |$ sub5_out[0][2] [7:0] $end
+      $var wire 8 }$ sub5_out[1][0] [7:0] $end
+      $var wire 8 ~$ sub5_out[1][1] [7:0] $end
+      $var wire 8 !% sub5_out[1][2] [7:0] $end
+      $var wire 32 "% count [31:0] $end
+      $var wire 32 I" driven_from_bind [31:0] $end
       $scope module i_sub4_bound $end
-       $var real 64 G% P1 $end
-       $var wire 32 G" driven_from_bind [31:0] $end
+       $var real 64 K% P1 $end
+       $var wire 32 I" driven_from_bind [31:0] $end
       $upscope $end
       $scope module i_sub5 $end
-       $var wire 1 >% clk $end
-       $var wire 128 }$ in[0][0] [127:0] $end
-       $var wire 128 #% in[0][1] [127:0] $end
-       $var wire 128 '% in[0][2] [127:0] $end
-       $var wire 128 +% in[1][0] [127:0] $end
-       $var wire 128 /% in[1][1] [127:0] $end
-       $var wire 128 3% in[1][2] [127:0] $end
-       $var wire 8 7% out[0][0] [7:0] $end
-       $var wire 8 8% out[0][1] [7:0] $end
-       $var wire 8 9% out[0][2] [7:0] $end
-       $var wire 8 :% out[1][0] [7:0] $end
-       $var wire 8 ;% out[1][1] [7:0] $end
-       $var wire 8 <% out[1][2] [7:0] $end
-       $var wire 32 =% count [31:0] $end
-       $var wire 8 H" val0[0] [7:0] $end
-       $var wire 8 I" val0[1] [7:0] $end
-       $var wire 8 J" val1[0] [7:0] $end
-       $var wire 8 K" val1[1] [7:0] $end
-       $var wire 8 L" val2[0] [7:0] $end
-       $var wire 8 M" val2[1] [7:0] $end
-       $var wire 8 N" val3[0] [7:0] $end
-       $var wire 8 O" val3[1] [7:0] $end
+       $var wire 1 B% clk $end
+       $var wire 128 #% in[0][0] [127:0] $end
+       $var wire 128 '% in[0][1] [127:0] $end
+       $var wire 128 +% in[0][2] [127:0] $end
+       $var wire 128 /% in[1][0] [127:0] $end
+       $var wire 128 3% in[1][1] [127:0] $end
+       $var wire 128 7% in[1][2] [127:0] $end
+       $var wire 8 ;% out[0][0] [7:0] $end
+       $var wire 8 <% out[0][1] [7:0] $end
+       $var wire 8 =% out[0][2] [7:0] $end
+       $var wire 8 >% out[1][0] [7:0] $end
+       $var wire 8 ?% out[1][1] [7:0] $end
+       $var wire 8 @% out[1][2] [7:0] $end
+       $var wire 32 A% count [31:0] $end
+       $var wire 8 J" val0[0] [7:0] $end
+       $var wire 8 K" val0[1] [7:0] $end
+       $var wire 8 L" val1[0] [7:0] $end
+       $var wire 8 M" val1[1] [7:0] $end
+       $var wire 8 N" val2[0] [7:0] $end
+       $var wire 8 O" val2[1] [7:0] $end
+       $var wire 8 P" val3[0] [7:0] $end
+       $var wire 8 Q" val3[1] [7:0] $end
        $scope module i_sub0 $end
-        $var wire 32 K% P0 [31:0] $end
-        $var wire 32 L% P1 [31:0] $end
-        $var wire 8 P" out[0] [7:0] $end
-        $var wire 8 Q" out[1] [7:0] $end
-       $upscope $end
-       $scope module i_sub1 $end
-        $var wire 32 K% P0 [31:0] $end
-        $var wire 32 L% P1 [31:0] $end
+        $var wire 32 O% P0 [31:0] $end
+        $var wire 32 P% P1 [31:0] $end
         $var wire 8 R" out[0] [7:0] $end
         $var wire 8 S" out[1] [7:0] $end
        $upscope $end
-       $scope module i_sub2 $end
-        $var wire 32 K% P0 [31:0] $end
-        $var wire 32 L% P1 [31:0] $end
+       $scope module i_sub1 $end
+        $var wire 32 O% P0 [31:0] $end
+        $var wire 32 P% P1 [31:0] $end
         $var wire 8 T" out[0] [7:0] $end
         $var wire 8 U" out[1] [7:0] $end
        $upscope $end
-       $scope module i_sub3 $end
-        $var wire 32 K% P0 [31:0] $end
-        $var wire 32 M% P1 [31:0] $end
+       $scope module i_sub2 $end
+        $var wire 32 O% P0 [31:0] $end
+        $var wire 32 P% P1 [31:0] $end
         $var wire 8 V" out[0] [7:0] $end
         $var wire 8 W" out[1] [7:0] $end
        $upscope $end
+       $scope module i_sub3 $end
+        $var wire 32 O% P0 [31:0] $end
+        $var wire 32 Q% P1 [31:0] $end
+        $var wire 8 X" out[0] [7:0] $end
+        $var wire 8 Y" out[1] [7:0] $end
+       $upscope $end
       $upscope $end
      $upscope $end
     $upscope $end
     $scope module in $end
-     $var wire 1 >% clk $end
-     $var wire 8 X" data [7:0] $end
+     $var wire 1 B% clk $end
+     $var wire 8 Z" data [7:0] $end
     $upscope $end
     $scope module out $end
-     $var wire 1 >% clk $end
-     $var wire 8 Z" data [7:0] $end
+     $var wire 1 B% clk $end
+     $var wire 8 \" data [7:0] $end
     $upscope $end
    $upscope $end
    $scope module in_ifs $end
-    $var wire 1 >% clk $end
-    $var wire 8 X" data [7:0] $end
+    $var wire 1 B% clk $end
+    $var wire 8 Z" data [7:0] $end
    $upscope $end
    $scope module out_ifs $end
-    $var wire 1 >% clk $end
-    $var wire 8 Z" data [7:0] $end
+    $var wire 1 B% clk $end
+    $var wire 8 \" data [7:0] $end
    $upscope $end
   $upscope $end
   $scope module i_sub3 $end
-   $var wire 8 Z! P0 [7:0] $end
-   $var wire 32 [! UNPACKED_ARRAY[0] [31:0] $end
-   $var wire 32 \! UNPACKED_ARRAY[1] [31:0] $end
-   $var wire 16 ]! UNUSED [15:0] $end
-   $var wire 2 ^! ENUM [1:0] $end
-   $var wire 1 Q! clk $end
-   $var wire 8 8! in [7:0] $end
-   $var wire 8 R! out [7:0] $end
-   $var wire 8 S! ff [7:0] $end
-   $var wire 8 R! out4 [7:0] $end
+   $var wire 8 \! P0 [7:0] $end
+   $var wire 32 ]! UNPACKED_ARRAY[0] [31:0] $end
+   $var wire 32 ^! UNPACKED_ARRAY[1] [31:0] $end
+   $var wire 16 _! UNUSED [15:0] $end
+   $var wire 2 `! ENUM [1:0] $end
+   $var wire 1 U! clk $end
+   $var wire 8 <! in [7:0] $end
+   $var wire 8 7! out [7:0] $end
+   $var wire 8 8! ff [7:0] $end
+   $var wire 8 7! out4 [7:0] $end
    $var wire 8 - out4_2 [7:0] $end
    $scope module i_sub4_0 $end
-    $var wire 32 _! P0 [31:0] $end
-    $var real 64 `! P1 $end
-    $var real 64 b! P3 $end
-    $var wire 1 Q! clk $end
-    $var wire 8 S! in [7:0] $end
-    $var wire 8 R! out [7:0] $end
-    $var wire 8 R! ff [7:0] $end
+    $var wire 32 a! P0 [31:0] $end
+    $var real 64 b! P1 $end
+    $var real 64 d! P3 $end
+    $var wire 1 U! clk $end
+    $var wire 8 9! in [7:0] $end
+    $var wire 8 7! out [7:0] $end
+    $var wire 8 7! ff [7:0] $end
     $var wire 128 . sub5_in[0][0] [127:0] $end
     $var wire 128 2 sub5_in[0][1] [127:0] $end
     $var wire 128 6 sub5_in[0][2] [127:0] $end
     $var wire 128 : sub5_in[1][0] [127:0] $end
     $var wire 128 > sub5_in[1][1] [127:0] $end
     $var wire 128 B sub5_in[1][2] [127:0] $end
-    $var wire 8 9! sub5_out[0][0] [7:0] $end
-    $var wire 8 :! sub5_out[0][1] [7:0] $end
-    $var wire 8 ;! sub5_out[0][2] [7:0] $end
-    $var wire 8 <! sub5_out[1][0] [7:0] $end
-    $var wire 8 =! sub5_out[1][1] [7:0] $end
-    $var wire 8 >! sub5_out[1][2] [7:0] $end
+    $var wire 8 =! sub5_out[0][0] [7:0] $end
+    $var wire 8 >! sub5_out[0][1] [7:0] $end
+    $var wire 8 ?! sub5_out[0][2] [7:0] $end
+    $var wire 8 @! sub5_out[1][0] [7:0] $end
+    $var wire 8 A! sub5_out[1][1] [7:0] $end
+    $var wire 8 B! sub5_out[1][2] [7:0] $end
     $var wire 32 F count [31:0] $end
     $var wire 32 " driven_from_bind [31:0] $end
     $scope module i_sub4_bound $end
-     $var real 64 `! P1 $end
+     $var real 64 b! P1 $end
      $var wire 32 " driven_from_bind [31:0] $end
     $upscope $end
     $scope module i_sub5 $end
-     $var wire 1 #& clk $end
-     $var wire 128 b% in[0][0] [127:0] $end
-     $var wire 128 f% in[0][1] [127:0] $end
-     $var wire 128 j% in[0][2] [127:0] $end
-     $var wire 128 n% in[1][0] [127:0] $end
-     $var wire 128 r% in[1][1] [127:0] $end
-     $var wire 128 v% in[1][2] [127:0] $end
-     $var wire 8 z% out[0][0] [7:0] $end
-     $var wire 8 {% out[0][1] [7:0] $end
-     $var wire 8 |% out[0][2] [7:0] $end
-     $var wire 8 }% out[1][0] [7:0] $end
-     $var wire 8 ~% out[1][1] [7:0] $end
-     $var wire 8 !& out[1][2] [7:0] $end
-     $var wire 32 "& count [31:0] $end
-     $var wire 8 R% val0[0] [7:0] $end
-     $var wire 8 S% val0[1] [7:0] $end
-     $var wire 8 T% val1[0] [7:0] $end
-     $var wire 8 U% val1[1] [7:0] $end
-     $var wire 8 V% val2[0] [7:0] $end
-     $var wire 8 W% val2[1] [7:0] $end
-     $var wire 8 X% val3[0] [7:0] $end
-     $var wire 8 Y% val3[1] [7:0] $end
+     $var wire 1 '& clk $end
+     $var wire 128 f% in[0][0] [127:0] $end
+     $var wire 128 j% in[0][1] [127:0] $end
+     $var wire 128 n% in[0][2] [127:0] $end
+     $var wire 128 r% in[1][0] [127:0] $end
+     $var wire 128 v% in[1][1] [127:0] $end
+     $var wire 128 z% in[1][2] [127:0] $end
+     $var wire 8 ~% out[0][0] [7:0] $end
+     $var wire 8 !& out[0][1] [7:0] $end
+     $var wire 8 "& out[0][2] [7:0] $end
+     $var wire 8 #& out[1][0] [7:0] $end
+     $var wire 8 $& out[1][1] [7:0] $end
+     $var wire 8 %& out[1][2] [7:0] $end
+     $var wire 32 && count [31:0] $end
+     $var wire 8 V% val0[0] [7:0] $end
+     $var wire 8 W% val0[1] [7:0] $end
+     $var wire 8 X% val1[0] [7:0] $end
+     $var wire 8 Y% val1[1] [7:0] $end
+     $var wire 8 Z% val2[0] [7:0] $end
+     $var wire 8 [% val2[1] [7:0] $end
+     $var wire 8 \% val3[0] [7:0] $end
+     $var wire 8 ]% val3[1] [7:0] $end
      $scope module i_sub0 $end
-      $var wire 32 $& P0 [31:0] $end
-      $var wire 32 %& P1 [31:0] $end
-      $var wire 8 Z% out[0] [7:0] $end
-      $var wire 8 [% out[1] [7:0] $end
-     $upscope $end
-     $scope module i_sub1 $end
-      $var wire 32 $& P0 [31:0] $end
-      $var wire 32 %& P1 [31:0] $end
-      $var wire 8 \% out[0] [7:0] $end
-      $var wire 8 ]% out[1] [7:0] $end
-     $upscope $end
-     $scope module i_sub2 $end
-      $var wire 32 $& P0 [31:0] $end
-      $var wire 32 %& P1 [31:0] $end
+      $var wire 32 (& P0 [31:0] $end
+      $var wire 32 )& P1 [31:0] $end
       $var wire 8 ^% out[0] [7:0] $end
       $var wire 8 _% out[1] [7:0] $end
      $upscope $end
-     $scope module i_sub3 $end
-      $var wire 32 $& P0 [31:0] $end
-      $var wire 32 && P1 [31:0] $end
+     $scope module i_sub1 $end
+      $var wire 32 (& P0 [31:0] $end
+      $var wire 32 )& P1 [31:0] $end
       $var wire 8 `% out[0] [7:0] $end
       $var wire 8 a% out[1] [7:0] $end
      $upscope $end
+     $scope module i_sub2 $end
+      $var wire 32 (& P0 [31:0] $end
+      $var wire 32 )& P1 [31:0] $end
+      $var wire 8 b% out[0] [7:0] $end
+      $var wire 8 c% out[1] [7:0] $end
+     $upscope $end
+     $scope module i_sub3 $end
+      $var wire 32 (& P0 [31:0] $end
+      $var wire 32 *& P1 [31:0] $end
+      $var wire 8 d% out[0] [7:0] $end
+      $var wire 8 e% out[1] [7:0] $end
+     $upscope $end
     $upscope $end
    $upscope $end
    $scope module i_sub4_1 $end
-    $var wire 32 _! P0 [31:0] $end
-    $var real 64 `! P1 $end
-    $var real 64 d! P3 $end
-    $var wire 1 Q! clk $end
-    $var wire 8 S! in [7:0] $end
+    $var wire 32 a! P0 [31:0] $end
+    $var real 64 b! P1 $end
+    $var real 64 f! P3 $end
+    $var wire 1 U! clk $end
+    $var wire 8 9! in [7:0] $end
     $var wire 8 - out [7:0] $end
     $var wire 8 - ff [7:0] $end
     $var wire 128 G sub5_in[0][0] [127:0] $end
@@ -537,228 +537,228 @@ $timescale 1ps $end
     $var wire 128 S sub5_in[1][0] [127:0] $end
     $var wire 128 W sub5_in[1][1] [127:0] $end
     $var wire 128 [ sub5_in[1][2] [127:0] $end
-    $var wire 8 ?! sub5_out[0][0] [7:0] $end
-    $var wire 8 @! sub5_out[0][1] [7:0] $end
-    $var wire 8 A! sub5_out[0][2] [7:0] $end
-    $var wire 8 B! sub5_out[1][0] [7:0] $end
-    $var wire 8 C! sub5_out[1][1] [7:0] $end
-    $var wire 8 D! sub5_out[1][2] [7:0] $end
+    $var wire 8 C! sub5_out[0][0] [7:0] $end
+    $var wire 8 D! sub5_out[0][1] [7:0] $end
+    $var wire 8 E! sub5_out[0][2] [7:0] $end
+    $var wire 8 F! sub5_out[1][0] [7:0] $end
+    $var wire 8 G! sub5_out[1][1] [7:0] $end
+    $var wire 8 H! sub5_out[1][2] [7:0] $end
     $var wire 32 _ count [31:0] $end
     $var wire 32 # driven_from_bind [31:0] $end
     $scope module i_sub4_bound $end
-     $var real 64 `! P1 $end
+     $var real 64 b! P1 $end
      $var wire 32 # driven_from_bind [31:0] $end
     $upscope $end
     $scope module i_sub5 $end
-     $var wire 1 V& clk $end
-     $var wire 128 7& in[0][0] [127:0] $end
-     $var wire 128 ;& in[0][1] [127:0] $end
-     $var wire 128 ?& in[0][2] [127:0] $end
-     $var wire 128 C& in[1][0] [127:0] $end
-     $var wire 128 G& in[1][1] [127:0] $end
-     $var wire 128 K& in[1][2] [127:0] $end
-     $var wire 8 O& out[0][0] [7:0] $end
-     $var wire 8 P& out[0][1] [7:0] $end
-     $var wire 8 Q& out[0][2] [7:0] $end
-     $var wire 8 R& out[1][0] [7:0] $end
-     $var wire 8 S& out[1][1] [7:0] $end
-     $var wire 8 T& out[1][2] [7:0] $end
-     $var wire 32 U& count [31:0] $end
-     $var wire 8 '& val0[0] [7:0] $end
-     $var wire 8 (& val0[1] [7:0] $end
-     $var wire 8 )& val1[0] [7:0] $end
-     $var wire 8 *& val1[1] [7:0] $end
-     $var wire 8 +& val2[0] [7:0] $end
-     $var wire 8 ,& val2[1] [7:0] $end
-     $var wire 8 -& val3[0] [7:0] $end
-     $var wire 8 .& val3[1] [7:0] $end
+     $var wire 1 Z& clk $end
+     $var wire 128 ;& in[0][0] [127:0] $end
+     $var wire 128 ?& in[0][1] [127:0] $end
+     $var wire 128 C& in[0][2] [127:0] $end
+     $var wire 128 G& in[1][0] [127:0] $end
+     $var wire 128 K& in[1][1] [127:0] $end
+     $var wire 128 O& in[1][2] [127:0] $end
+     $var wire 8 S& out[0][0] [7:0] $end
+     $var wire 8 T& out[0][1] [7:0] $end
+     $var wire 8 U& out[0][2] [7:0] $end
+     $var wire 8 V& out[1][0] [7:0] $end
+     $var wire 8 W& out[1][1] [7:0] $end
+     $var wire 8 X& out[1][2] [7:0] $end
+     $var wire 32 Y& count [31:0] $end
+     $var wire 8 +& val0[0] [7:0] $end
+     $var wire 8 ,& val0[1] [7:0] $end
+     $var wire 8 -& val1[0] [7:0] $end
+     $var wire 8 .& val1[1] [7:0] $end
+     $var wire 8 /& val2[0] [7:0] $end
+     $var wire 8 0& val2[1] [7:0] $end
+     $var wire 8 1& val3[0] [7:0] $end
+     $var wire 8 2& val3[1] [7:0] $end
      $scope module i_sub0 $end
-      $var wire 32 W& P0 [31:0] $end
-      $var wire 32 X& P1 [31:0] $end
-      $var wire 8 /& out[0] [7:0] $end
-      $var wire 8 0& out[1] [7:0] $end
-     $upscope $end
-     $scope module i_sub1 $end
-      $var wire 32 W& P0 [31:0] $end
-      $var wire 32 X& P1 [31:0] $end
-      $var wire 8 1& out[0] [7:0] $end
-      $var wire 8 2& out[1] [7:0] $end
-     $upscope $end
-     $scope module i_sub2 $end
-      $var wire 32 W& P0 [31:0] $end
-      $var wire 32 X& P1 [31:0] $end
+      $var wire 32 [& P0 [31:0] $end
+      $var wire 32 \& P1 [31:0] $end
       $var wire 8 3& out[0] [7:0] $end
       $var wire 8 4& out[1] [7:0] $end
      $upscope $end
-     $scope module i_sub3 $end
-      $var wire 32 W& P0 [31:0] $end
-      $var wire 32 Y& P1 [31:0] $end
+     $scope module i_sub1 $end
+      $var wire 32 [& P0 [31:0] $end
+      $var wire 32 \& P1 [31:0] $end
       $var wire 8 5& out[0] [7:0] $end
       $var wire 8 6& out[1] [7:0] $end
      $upscope $end
+     $scope module i_sub2 $end
+      $var wire 32 [& P0 [31:0] $end
+      $var wire 32 \& P1 [31:0] $end
+      $var wire 8 7& out[0] [7:0] $end
+      $var wire 8 8& out[1] [7:0] $end
+     $upscope $end
+     $scope module i_sub3 $end
+      $var wire 32 [& P0 [31:0] $end
+      $var wire 32 ]& P1 [31:0] $end
+      $var wire 8 9& out[0] [7:0] $end
+      $var wire 8 :& out[1] [7:0] $end
+     $upscope $end
     $upscope $end
    $upscope $end
   $upscope $end
   $scope module i_sub3_2 $end
-   $var wire 8 Z! P0 [7:0] $end
-   $var wire 32 f! UNPACKED_ARRAY[0] [31:0] $end
-   $var wire 32 g! UNPACKED_ARRAY[1] [31:0] $end
-   $var wire 16 ]! UNUSED [15:0] $end
-   $var wire 2 ^! ENUM [1:0] $end
-   $var wire 1 Q! clk $end
-   $var wire 8 8! in [7:0] $end
+   $var wire 8 \! P0 [7:0] $end
+   $var wire 32 h! UNPACKED_ARRAY[0] [31:0] $end
+   $var wire 32 i! UNPACKED_ARRAY[1] [31:0] $end
+   $var wire 16 _! UNUSED [15:0] $end
+   $var wire 2 `! ENUM [1:0] $end
+   $var wire 1 U! clk $end
+   $var wire 8 <! in [7:0] $end
    $var wire 8 & out [7:0] $end
    $var wire 8 ` ff [7:0] $end
    $var wire 8 & out4 [7:0] $end
    $var wire 8 a out4_2 [7:0] $end
    $scope module i_sub4_0 $end
-    $var wire 32 _! P0 [31:0] $end
-    $var real 64 `! P1 $end
-    $var real 64 b! P3 $end
-    $var wire 1 Q! clk $end
-    $var wire 8 ` in [7:0] $end
+    $var wire 32 a! P0 [31:0] $end
+    $var real 64 b! P1 $end
+    $var real 64 d! P3 $end
+    $var wire 1 U! clk $end
+    $var wire 8 b in [7:0] $end
     $var wire 8 & out [7:0] $end
     $var wire 8 & ff [7:0] $end
-    $var wire 128 b sub5_in[0][0] [127:0] $end
-    $var wire 128 f sub5_in[0][1] [127:0] $end
-    $var wire 128 j sub5_in[0][2] [127:0] $end
-    $var wire 128 n sub5_in[1][0] [127:0] $end
-    $var wire 128 r sub5_in[1][1] [127:0] $end
-    $var wire 128 v sub5_in[1][2] [127:0] $end
-    $var wire 8 E! sub5_out[0][0] [7:0] $end
-    $var wire 8 F! sub5_out[0][1] [7:0] $end
-    $var wire 8 G! sub5_out[0][2] [7:0] $end
-    $var wire 8 H! sub5_out[1][0] [7:0] $end
-    $var wire 8 I! sub5_out[1][1] [7:0] $end
-    $var wire 8 J! sub5_out[1][2] [7:0] $end
-    $var wire 32 z count [31:0] $end
+    $var wire 128 c sub5_in[0][0] [127:0] $end
+    $var wire 128 g sub5_in[0][1] [127:0] $end
+    $var wire 128 k sub5_in[0][2] [127:0] $end
+    $var wire 128 o sub5_in[1][0] [127:0] $end
+    $var wire 128 s sub5_in[1][1] [127:0] $end
+    $var wire 128 w sub5_in[1][2] [127:0] $end
+    $var wire 8 I! sub5_out[0][0] [7:0] $end
+    $var wire 8 J! sub5_out[0][1] [7:0] $end
+    $var wire 8 K! sub5_out[0][2] [7:0] $end
+    $var wire 8 L! sub5_out[1][0] [7:0] $end
+    $var wire 8 M! sub5_out[1][1] [7:0] $end
+    $var wire 8 N! sub5_out[1][2] [7:0] $end
+    $var wire 32 { count [31:0] $end
     $var wire 32 $ driven_from_bind [31:0] $end
     $scope module i_sub4_bound $end
-     $var real 64 `! P1 $end
+     $var real 64 b! P1 $end
      $var wire 32 $ driven_from_bind [31:0] $end
     $upscope $end
     $scope module i_sub5 $end
-     $var wire 1 +' clk $end
-     $var wire 128 j& in[0][0] [127:0] $end
-     $var wire 128 n& in[0][1] [127:0] $end
-     $var wire 128 r& in[0][2] [127:0] $end
-     $var wire 128 v& in[1][0] [127:0] $end
-     $var wire 128 z& in[1][1] [127:0] $end
-     $var wire 128 ~& in[1][2] [127:0] $end
-     $var wire 8 $' out[0][0] [7:0] $end
-     $var wire 8 %' out[0][1] [7:0] $end
-     $var wire 8 &' out[0][2] [7:0] $end
-     $var wire 8 '' out[1][0] [7:0] $end
-     $var wire 8 (' out[1][1] [7:0] $end
-     $var wire 8 )' out[1][2] [7:0] $end
-     $var wire 32 *' count [31:0] $end
-     $var wire 8 Z& val0[0] [7:0] $end
-     $var wire 8 [& val0[1] [7:0] $end
-     $var wire 8 \& val1[0] [7:0] $end
-     $var wire 8 ]& val1[1] [7:0] $end
-     $var wire 8 ^& val2[0] [7:0] $end
-     $var wire 8 _& val2[1] [7:0] $end
-     $var wire 8 `& val3[0] [7:0] $end
-     $var wire 8 a& val3[1] [7:0] $end
+     $var wire 1 /' clk $end
+     $var wire 128 n& in[0][0] [127:0] $end
+     $var wire 128 r& in[0][1] [127:0] $end
+     $var wire 128 v& in[0][2] [127:0] $end
+     $var wire 128 z& in[1][0] [127:0] $end
+     $var wire 128 ~& in[1][1] [127:0] $end
+     $var wire 128 $' in[1][2] [127:0] $end
+     $var wire 8 (' out[0][0] [7:0] $end
+     $var wire 8 )' out[0][1] [7:0] $end
+     $var wire 8 *' out[0][2] [7:0] $end
+     $var wire 8 +' out[1][0] [7:0] $end
+     $var wire 8 ,' out[1][1] [7:0] $end
+     $var wire 8 -' out[1][2] [7:0] $end
+     $var wire 32 .' count [31:0] $end
+     $var wire 8 ^& val0[0] [7:0] $end
+     $var wire 8 _& val0[1] [7:0] $end
+     $var wire 8 `& val1[0] [7:0] $end
+     $var wire 8 a& val1[1] [7:0] $end
+     $var wire 8 b& val2[0] [7:0] $end
+     $var wire 8 c& val2[1] [7:0] $end
+     $var wire 8 d& val3[0] [7:0] $end
+     $var wire 8 e& val3[1] [7:0] $end
      $scope module i_sub0 $end
-      $var wire 32 ,' P0 [31:0] $end
-      $var wire 32 -' P1 [31:0] $end
-      $var wire 8 b& out[0] [7:0] $end
-      $var wire 8 c& out[1] [7:0] $end
-     $upscope $end
-     $scope module i_sub1 $end
-      $var wire 32 ,' P0 [31:0] $end
-      $var wire 32 -' P1 [31:0] $end
-      $var wire 8 d& out[0] [7:0] $end
-      $var wire 8 e& out[1] [7:0] $end
-     $upscope $end
-     $scope module i_sub2 $end
-      $var wire 32 ,' P0 [31:0] $end
-      $var wire 32 -' P1 [31:0] $end
+      $var wire 32 0' P0 [31:0] $end
+      $var wire 32 1' P1 [31:0] $end
       $var wire 8 f& out[0] [7:0] $end
       $var wire 8 g& out[1] [7:0] $end
      $upscope $end
-     $scope module i_sub3 $end
-      $var wire 32 ,' P0 [31:0] $end
-      $var wire 32 .' P1 [31:0] $end
+     $scope module i_sub1 $end
+      $var wire 32 0' P0 [31:0] $end
+      $var wire 32 1' P1 [31:0] $end
       $var wire 8 h& out[0] [7:0] $end
       $var wire 8 i& out[1] [7:0] $end
      $upscope $end
+     $scope module i_sub2 $end
+      $var wire 32 0' P0 [31:0] $end
+      $var wire 32 1' P1 [31:0] $end
+      $var wire 8 j& out[0] [7:0] $end
+      $var wire 8 k& out[1] [7:0] $end
+     $upscope $end
+     $scope module i_sub3 $end
+      $var wire 32 0' P0 [31:0] $end
+      $var wire 32 2' P1 [31:0] $end
+      $var wire 8 l& out[0] [7:0] $end
+      $var wire 8 m& out[1] [7:0] $end
+     $upscope $end
     $upscope $end
    $upscope $end
    $scope module i_sub4_1 $end
-    $var wire 32 _! P0 [31:0] $end
-    $var real 64 `! P1 $end
-    $var real 64 d! P3 $end
-    $var wire 1 Q! clk $end
-    $var wire 8 ` in [7:0] $end
+    $var wire 32 a! P0 [31:0] $end
+    $var real 64 b! P1 $end
+    $var real 64 f! P3 $end
+    $var wire 1 U! clk $end
+    $var wire 8 b in [7:0] $end
     $var wire 8 a out [7:0] $end
     $var wire 8 a ff [7:0] $end
-    $var wire 128 { sub5_in[0][0] [127:0] $end
-    $var wire 128 !! sub5_in[0][1] [127:0] $end
-    $var wire 128 %! sub5_in[0][2] [127:0] $end
-    $var wire 128 )! sub5_in[1][0] [127:0] $end
-    $var wire 128 -! sub5_in[1][1] [127:0] $end
-    $var wire 128 1! sub5_in[1][2] [127:0] $end
-    $var wire 8 K! sub5_out[0][0] [7:0] $end
-    $var wire 8 L! sub5_out[0][1] [7:0] $end
-    $var wire 8 M! sub5_out[0][2] [7:0] $end
-    $var wire 8 N! sub5_out[1][0] [7:0] $end
-    $var wire 8 O! sub5_out[1][1] [7:0] $end
-    $var wire 8 P! sub5_out[1][2] [7:0] $end
-    $var wire 32 5! count [31:0] $end
+    $var wire 128 | sub5_in[0][0] [127:0] $end
+    $var wire 128 "! sub5_in[0][1] [127:0] $end
+    $var wire 128 &! sub5_in[0][2] [127:0] $end
+    $var wire 128 *! sub5_in[1][0] [127:0] $end
+    $var wire 128 .! sub5_in[1][1] [127:0] $end
+    $var wire 128 2! sub5_in[1][2] [127:0] $end
+    $var wire 8 O! sub5_out[0][0] [7:0] $end
+    $var wire 8 P! sub5_out[0][1] [7:0] $end
+    $var wire 8 Q! sub5_out[0][2] [7:0] $end
+    $var wire 8 R! sub5_out[1][0] [7:0] $end
+    $var wire 8 S! sub5_out[1][1] [7:0] $end
+    $var wire 8 T! sub5_out[1][2] [7:0] $end
+    $var wire 32 6! count [31:0] $end
     $var wire 32 % driven_from_bind [31:0] $end
     $scope module i_sub4_bound $end
-     $var real 64 `! P1 $end
+     $var real 64 b! P1 $end
      $var wire 32 % driven_from_bind [31:0] $end
     $upscope $end
     $scope module i_sub5 $end
-     $var wire 1 ^' clk $end
-     $var wire 128 ?' in[0][0] [127:0] $end
-     $var wire 128 C' in[0][1] [127:0] $end
-     $var wire 128 G' in[0][2] [127:0] $end
-     $var wire 128 K' in[1][0] [127:0] $end
-     $var wire 128 O' in[1][1] [127:0] $end
-     $var wire 128 S' in[1][2] [127:0] $end
-     $var wire 8 W' out[0][0] [7:0] $end
-     $var wire 8 X' out[0][1] [7:0] $end
-     $var wire 8 Y' out[0][2] [7:0] $end
-     $var wire 8 Z' out[1][0] [7:0] $end
-     $var wire 8 [' out[1][1] [7:0] $end
-     $var wire 8 \' out[1][2] [7:0] $end
-     $var wire 32 ]' count [31:0] $end
-     $var wire 8 /' val0[0] [7:0] $end
-     $var wire 8 0' val0[1] [7:0] $end
-     $var wire 8 1' val1[0] [7:0] $end
-     $var wire 8 2' val1[1] [7:0] $end
-     $var wire 8 3' val2[0] [7:0] $end
-     $var wire 8 4' val2[1] [7:0] $end
-     $var wire 8 5' val3[0] [7:0] $end
-     $var wire 8 6' val3[1] [7:0] $end
+     $var wire 1 b' clk $end
+     $var wire 128 C' in[0][0] [127:0] $end
+     $var wire 128 G' in[0][1] [127:0] $end
+     $var wire 128 K' in[0][2] [127:0] $end
+     $var wire 128 O' in[1][0] [127:0] $end
+     $var wire 128 S' in[1][1] [127:0] $end
+     $var wire 128 W' in[1][2] [127:0] $end
+     $var wire 8 [' out[0][0] [7:0] $end
+     $var wire 8 \' out[0][1] [7:0] $end
+     $var wire 8 ]' out[0][2] [7:0] $end
+     $var wire 8 ^' out[1][0] [7:0] $end
+     $var wire 8 _' out[1][1] [7:0] $end
+     $var wire 8 `' out[1][2] [7:0] $end
+     $var wire 32 a' count [31:0] $end
+     $var wire 8 3' val0[0] [7:0] $end
+     $var wire 8 4' val0[1] [7:0] $end
+     $var wire 8 5' val1[0] [7:0] $end
+     $var wire 8 6' val1[1] [7:0] $end
+     $var wire 8 7' val2[0] [7:0] $end
+     $var wire 8 8' val2[1] [7:0] $end
+     $var wire 8 9' val3[0] [7:0] $end
+     $var wire 8 :' val3[1] [7:0] $end
      $scope module i_sub0 $end
-      $var wire 32 _' P0 [31:0] $end
-      $var wire 32 `' P1 [31:0] $end
-      $var wire 8 7' out[0] [7:0] $end
-      $var wire 8 8' out[1] [7:0] $end
-     $upscope $end
-     $scope module i_sub1 $end
-      $var wire 32 _' P0 [31:0] $end
-      $var wire 32 `' P1 [31:0] $end
-      $var wire 8 9' out[0] [7:0] $end
-      $var wire 8 :' out[1] [7:0] $end
-     $upscope $end
-     $scope module i_sub2 $end
-      $var wire 32 _' P0 [31:0] $end
-      $var wire 32 `' P1 [31:0] $end
+      $var wire 32 c' P0 [31:0] $end
+      $var wire 32 d' P1 [31:0] $end
       $var wire 8 ;' out[0] [7:0] $end
       $var wire 8 <' out[1] [7:0] $end
      $upscope $end
-     $scope module i_sub3 $end
-      $var wire 32 _' P0 [31:0] $end
-      $var wire 32 a' P1 [31:0] $end
+     $scope module i_sub1 $end
+      $var wire 32 c' P0 [31:0] $end
+      $var wire 32 d' P1 [31:0] $end
       $var wire 8 =' out[0] [7:0] $end
       $var wire 8 >' out[1] [7:0] $end
      $upscope $end
+     $scope module i_sub2 $end
+      $var wire 32 c' P0 [31:0] $end
+      $var wire 32 d' P1 [31:0] $end
+      $var wire 8 ?' out[0] [7:0] $end
+      $var wire 8 @' out[1] [7:0] $end
+     $upscope $end
+     $scope module i_sub3 $end
+      $var wire 32 c' P0 [31:0] $end
+      $var wire 32 e' P1 [31:0] $end
+      $var wire 8 A' out[0] [7:0] $end
+      $var wire 8 B' out[1] [7:0] $end
+     $upscope $end
     $upscope $end
    $upscope $end
   $upscope $end
@@ -795,21 +795,21 @@ b0000000000000000000000000000000000000000000000000000000000000000000000000000000
 b00000000000000000000000000000000 _
 b00000000 `
 b00000000 a
-b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 b
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-b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 !!
-b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 %!
-b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 )!
-b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -!
-b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 1!
-b00000000000000000000000000000000 5!
-b00000000 6!
+b00000000 b
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+b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 k
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+b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 w
+b00000000000000000000000000000000 {
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+b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 "!
+b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 &!
+b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 *!
+b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 .!
+b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2!
+b00000000000000000000000000000000 6!
 b00000000 7!
 b00000000 8!
 b00000000 9!
@@ -836,365 +836,369 @@ b00000000 M!
 b00000000 N!
 b00000000 O!
 b00000000 P!
-0Q!
+b00000000 Q!
 b00000000 R!
 b00000000 S!
-0m!
-b00000000 n!
-b00000000 o!
+b00000000 T!
+0U!
+0o!
 b00000000 p!
-b00 q!
-b00000000000000000000000000000110 r!
-b00000001 s!
-b00000010 t!
+b00000000 q!
+b00000000 r!
+b00 s!
+b00000000000000000000000000000110 t!
 b00000001 u!
 b00000010 v!
 b00000001 w!
 b00000010 x!
 b00000001 y!
-b00000011 z!
+b00000010 z!
 b00000001 {!
-b00000010 |!
+b00000011 |!
 b00000001 }!
 b00000010 ~!
 b00000001 !"
 b00000010 ""
 b00000001 #"
-b00000011 $"
-b00000000000000000000000000000110 %"
-b00000001 &"
-b00000010 '"
+b00000010 $"
+b00000001 %"
+b00000011 &"
+b00000000000000000000000000000110 '"
 b00000001 ("
 b00000010 )"
 b00000001 *"
 b00000010 +"
 b00000001 ,"
-b00000011 -"
+b00000010 -"
 b00000001 ."
-b00000010 /"
+b00000011 /"
 b00000001 0"
 b00000010 1"
 b00000001 2"
 b00000010 3"
 b00000001 4"
-b00000011 5"
-b00000000000000000000000000000110 6"
-b00000001 7"
-b00000010 8"
+b00000010 5"
+b00000001 6"
+b00000011 7"
+b00000000000000000000000000000110 8"
 b00000001 9"
 b00000010 :"
 b00000001 ;"
 b00000010 <"
 b00000001 ="
-b00000011 >"
+b00000010 >"
 b00000001 ?"
-b00000010 @"
+b00000011 @"
 b00000001 A"
 b00000010 B"
 b00000001 C"
 b00000010 D"
 b00000001 E"
-b00000011 F"
-b00000000000000000000000000000110 G"
-b00000001 H"
-b00000010 I"
+b00000010 F"
+b00000001 G"
+b00000011 H"
+b00000000000000000000000000000110 I"
 b00000001 J"
 b00000010 K"
 b00000001 L"
 b00000010 M"
 b00000001 N"
-b00000011 O"
+b00000010 O"
 b00000001 P"
-b00000010 Q"
+b00000011 Q"
 b00000001 R"
 b00000010 S"
 b00000001 T"
 b00000010 U"
 b00000001 V"
-b00000011 W"
-b00000000 X"
-b00 Y"
+b00000010 W"
+b00000001 X"
+b00000011 Y"
 b00000000 Z"
-b00000000 ["
+b00 ["
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 #165
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 b00011011 &
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diff --git a/test_regress/t/t_trace_hier_block_statefulpkg_cc_vcd.out b/test_regress/t/t_trace_hier_block_statefulpkg_cc_vcd.out
index 30ce91000..c1ad0988d 100644
--- a/test_regress/t/t_trace_hier_block_statefulpkg_cc_vcd.out
+++ b/test_regress/t/t_trace_hier_block_statefulpkg_cc_vcd.out
@@ -1,37 +1,37 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module top $end
-  $var wire 1 R! clk $end
+  $var wire 1 V! clk $end
   $scope module $unit $end
-   $var wire 1 6! global_flag $end
+   $var wire 1 7! global_flag $end
   $upscope $end
   $scope module stateless_pkg $end
-   $var wire 32 i! ONE [31:0] $end
+   $var wire 32 k! ONE [31:0] $end
   $upscope $end
   $scope module t $end
-   $var wire 32 U! PARAM_A [31:0] $end
-   $var wire 32 V! PARAM_B [31:0] $end
-   $var wire 1 R! clk $end
-   $var wire 8 7! out0 [7:0] $end
-   $var wire 8 8! out1 [7:0] $end
-   $var wire 8 9! out2 [7:0] $end
-   $var wire 8 S! out3 [7:0] $end
+   $var wire 32 W! PARAM_A [31:0] $end
+   $var wire 32 X! PARAM_B [31:0] $end
+   $var wire 1 V! clk $end
+   $var wire 8 ;! out0 [7:0] $end
+   $var wire 8 <! out1 [7:0] $end
+   $var wire 8 =! out2 [7:0] $end
+   $var wire 8 8! out3 [7:0] $end
    $var wire 8 & out3_2 [7:0] $end
    $var wire 8 ' out5 [7:0] $end
    $var wire 8 ( out6 [7:0] $end
    $var wire 32 ) count [31:0] $end
    $scope module i_delay0 $end
-    $var wire 32 W! N [31:0] $end
-    $var wire 32 X! WIDTH [31:0] $end
-    $var wire 1 R! clk $end
-    $var wire 8 S! in [7:0] $end
+    $var wire 32 Y! N [31:0] $end
+    $var wire 32 Z! WIDTH [31:0] $end
+    $var wire 1 V! clk $end
+    $var wire 8 8! in [7:0] $end
     $var wire 8 ' out [7:0] $end
     $var wire 8 * tmp [7:0] $end
     $scope module genblk1 $end
      $scope module i_delay $end
-      $var wire 32 Y! N [31:0] $end
-      $var wire 32 X! WIDTH [31:0] $end
-      $var wire 1 R! clk $end
+      $var wire 32 [! N [31:0] $end
+      $var wire 32 Z! WIDTH [31:0] $end
+      $var wire 1 V! clk $end
       $var wire 8 * in [7:0] $end
       $var wire 8 ' out [7:0] $end
       $var wire 8 ' tmp [7:0] $end
@@ -39,25 +39,25 @@ $timescale 1ps $end
     $upscope $end
    $upscope $end
    $scope module i_delay1 $end
-    $var wire 32 Z! N [31:0] $end
-    $var wire 32 X! WIDTH [31:0] $end
-    $var wire 1 R! clk $end
+    $var wire 32 \! N [31:0] $end
+    $var wire 32 Z! WIDTH [31:0] $end
+    $var wire 1 V! clk $end
     $var wire 8 ' in [7:0] $end
     $var wire 8 ( out [7:0] $end
     $var wire 8 + tmp [7:0] $end
     $scope module genblk1 $end
      $scope module i_delay $end
-      $var wire 32 W! N [31:0] $end
-      $var wire 32 X! WIDTH [31:0] $end
-      $var wire 1 R! clk $end
+      $var wire 32 Y! N [31:0] $end
+      $var wire 32 Z! WIDTH [31:0] $end
+      $var wire 1 V! clk $end
       $var wire 8 + in [7:0] $end
       $var wire 8 ( out [7:0] $end
       $var wire 8 , tmp [7:0] $end
       $scope module genblk1 $end
        $scope module i_delay $end
-        $var wire 32 Y! N [31:0] $end
-        $var wire 32 X! WIDTH [31:0] $end
-        $var wire 1 R! clk $end
+        $var wire 32 [! N [31:0] $end
+        $var wire 32 Z! WIDTH [31:0] $end
+        $var wire 1 V! clk $end
         $var wire 8 , in [7:0] $end
         $var wire 8 ( out [7:0] $end
         $var wire 8 ( tmp [7:0] $end
@@ -67,482 +67,482 @@ $timescale 1ps $end
     $upscope $end
    $upscope $end
    $scope module i_sub0 $end
-    $var wire 1 R! clk $end
-    $var wire 8 S! in [7:0] $end
-    $var wire 8 7! out [7:0] $end
+    $var wire 1 V! clk $end
+    $var wire 8 8! in [7:0] $end
+    $var wire 8 ;! out [7:0] $end
     $scope module i_sub0 $end
-     $var wire 1 j! clk $end
-     $var wire 8 k! in [7:0] $end
-     $var wire 8 l! out [7:0] $end
-     $var wire 8 m! ff [7:0] $end
+     $var wire 1 l! clk $end
+     $var wire 8 m! in [7:0] $end
+     $var wire 8 n! out [7:0] $end
+     $var wire 8 o! ff [7:0] $end
      $scope module $libroot $end
-      $var wire 1 n! global_flag $end
+      $var wire 1 p! global_flag $end
      $upscope $end
     $upscope $end
    $upscope $end
    $scope module i_sub1 $end
-    $var wire 1 o! clk $end
-    $var wire 8 p! in [11:4] $end
-    $var wire 8 q! out [7:0] $end
-    $var wire 8 r! ff [7:0] $end
-    $var wire 2 s! enum_v [1:0] $end
+    $var wire 1 q! clk $end
+    $var wire 8 r! in [11:4] $end
+    $var wire 8 s! out [7:0] $end
+    $var wire 8 t! ff [7:0] $end
+    $var wire 2 u! enum_v [1:0] $end
     $scope module $libroot $end
-     $var wire 1 t! global_flag $end
+     $var wire 1 v! global_flag $end
     $upscope $end
    $upscope $end
    $scope module i_sub2 $end
-    $var wire 1 A% clk $end
-    $var wire 8 B% in [7:0] $end
-    $var wire 8 C% out [7:0] $end
-    $var wire 8 [" ff [7:0] $end
-    $var wire 2 \" alt_enum_v [1:0] $end
+    $var wire 1 E% clk $end
+    $var wire 8 F% in [7:0] $end
+    $var wire 8 G% out [7:0] $end
+    $var wire 8 ]" ff [7:0] $end
+    $var wire 2 ^" alt_enum_v [1:0] $end
     $scope module $libroot $end
-     $var wire 1 U% global_flag $end
+     $var wire 1 Y% global_flag $end
     $upscope $end
     $scope module i_sub3 $end
-     $var wire 8 [" in_wire [7:0] $end
-     $var wire 8 ]" out_1 [7:0] $end
-     $var wire 8 ^" out_2 [7:0] $end
+     $var wire 8 ]" in_wire [7:0] $end
+     $var wire 8 _" out_1 [7:0] $end
+     $var wire 8 `" out_2 [7:0] $end
      $scope module i_sub3 $end
-      $var wire 8 D% P0 [7:0] $end
-      $var wire 32 E% UNPACKED_ARRAY[0] [31:0] $end
-      $var wire 32 F% UNPACKED_ARRAY[1] [31:0] $end
-      $var wire 16 G% UNUSED [15:0] $end
-      $var wire 2 H% ENUM [1:0] $end
-      $var wire 1 A% clk $end
-      $var wire 8 [" in [7:0] $end
-      $var wire 8 ]" out [7:0] $end
-      $var wire 8 _" ff [7:0] $end
-      $var wire 8 ]" out4 [7:0] $end
-      $var wire 8 `" out4_2 [7:0] $end
+      $var wire 8 H% P0 [7:0] $end
+      $var wire 32 I% UNPACKED_ARRAY[0] [31:0] $end
+      $var wire 32 J% UNPACKED_ARRAY[1] [31:0] $end
+      $var wire 16 K% UNUSED [15:0] $end
+      $var wire 2 L% ENUM [1:0] $end
+      $var wire 1 E% clk $end
+      $var wire 8 ]" in [7:0] $end
+      $var wire 8 _" out [7:0] $end
+      $var wire 8 a" ff [7:0] $end
+      $var wire 8 _" out4 [7:0] $end
+      $var wire 8 b" out4_2 [7:0] $end
       $scope module i_sub4_0 $end
-       $var wire 32 I% P0 [31:0] $end
-       $var real 64 J% P1 $end
-       $var real 64 L% P3 $end
-       $var wire 1 A% clk $end
-       $var wire 8 _" in [7:0] $end
-       $var wire 8 ]" out [7:0] $end
-       $var wire 8 ]" ff [7:0] $end
-       $var wire 128 a" sub5_in[0][0] [127:0] $end
-       $var wire 128 e" sub5_in[0][1] [127:0] $end
-       $var wire 128 i" sub5_in[0][2] [127:0] $end
-       $var wire 128 m" sub5_in[1][0] [127:0] $end
-       $var wire 128 q" sub5_in[1][1] [127:0] $end
-       $var wire 128 u" sub5_in[1][2] [127:0] $end
-       $var wire 8 y" sub5_out[0][0] [7:0] $end
-       $var wire 8 z" sub5_out[0][1] [7:0] $end
-       $var wire 8 {" sub5_out[0][2] [7:0] $end
-       $var wire 8 |" sub5_out[1][0] [7:0] $end
-       $var wire 8 }" sub5_out[1][1] [7:0] $end
-       $var wire 8 ~" sub5_out[1][2] [7:0] $end
-       $var wire 32 !# count [31:0] $end
-       $var wire 32 u! driven_from_bind [31:0] $end
+       $var wire 32 M% P0 [31:0] $end
+       $var real 64 N% P1 $end
+       $var real 64 P% P3 $end
+       $var wire 1 E% clk $end
+       $var wire 8 c" in [7:0] $end
+       $var wire 8 _" out [7:0] $end
+       $var wire 8 _" ff [7:0] $end
+       $var wire 128 d" sub5_in[0][0] [127:0] $end
+       $var wire 128 h" sub5_in[0][1] [127:0] $end
+       $var wire 128 l" sub5_in[0][2] [127:0] $end
+       $var wire 128 p" sub5_in[1][0] [127:0] $end
+       $var wire 128 t" sub5_in[1][1] [127:0] $end
+       $var wire 128 x" sub5_in[1][2] [127:0] $end
+       $var wire 8 |" sub5_out[0][0] [7:0] $end
+       $var wire 8 }" sub5_out[0][1] [7:0] $end
+       $var wire 8 ~" sub5_out[0][2] [7:0] $end
+       $var wire 8 !# sub5_out[1][0] [7:0] $end
+       $var wire 8 "# sub5_out[1][1] [7:0] $end
+       $var wire 8 ## sub5_out[1][2] [7:0] $end
+       $var wire 32 $# count [31:0] $end
+       $var wire 32 w! driven_from_bind [31:0] $end
        $scope module i_sub4_bound $end
-        $var real 64 J% P1 $end
-        $var wire 32 u! driven_from_bind [31:0] $end
+        $var real 64 N% P1 $end
+        $var wire 32 w! driven_from_bind [31:0] $end
        $upscope $end
        $scope module i_sub5 $end
-        $var wire 1 A% clk $end
-        $var wire 128 "# in[0][0] [127:0] $end
-        $var wire 128 &# in[0][1] [127:0] $end
-        $var wire 128 *# in[0][2] [127:0] $end
-        $var wire 128 .# in[1][0] [127:0] $end
-        $var wire 128 2# in[1][1] [127:0] $end
-        $var wire 128 6# in[1][2] [127:0] $end
-        $var wire 8 :# out[0][0] [7:0] $end
-        $var wire 8 ;# out[0][1] [7:0] $end
-        $var wire 8 <# out[0][2] [7:0] $end
-        $var wire 8 =# out[1][0] [7:0] $end
-        $var wire 8 ># out[1][1] [7:0] $end
-        $var wire 8 ?# out[1][2] [7:0] $end
-        $var wire 32 @# count [31:0] $end
-        $var wire 8 v! val0[0] [7:0] $end
-        $var wire 8 w! val0[1] [7:0] $end
-        $var wire 8 x! val1[0] [7:0] $end
-        $var wire 8 y! val1[1] [7:0] $end
-        $var wire 8 z! val2[0] [7:0] $end
-        $var wire 8 {! val2[1] [7:0] $end
-        $var wire 8 |! val3[0] [7:0] $end
-        $var wire 8 }! val3[1] [7:0] $end
+        $var wire 1 E% clk $end
+        $var wire 128 %# in[0][0] [127:0] $end
+        $var wire 128 )# in[0][1] [127:0] $end
+        $var wire 128 -# in[0][2] [127:0] $end
+        $var wire 128 1# in[1][0] [127:0] $end
+        $var wire 128 5# in[1][1] [127:0] $end
+        $var wire 128 9# in[1][2] [127:0] $end
+        $var wire 8 =# out[0][0] [7:0] $end
+        $var wire 8 ># out[0][1] [7:0] $end
+        $var wire 8 ?# out[0][2] [7:0] $end
+        $var wire 8 @# out[1][0] [7:0] $end
+        $var wire 8 A# out[1][1] [7:0] $end
+        $var wire 8 B# out[1][2] [7:0] $end
+        $var wire 32 C# count [31:0] $end
+        $var wire 8 x! val0[0] [7:0] $end
+        $var wire 8 y! val0[1] [7:0] $end
+        $var wire 8 z! val1[0] [7:0] $end
+        $var wire 8 {! val1[1] [7:0] $end
+        $var wire 8 |! val2[0] [7:0] $end
+        $var wire 8 }! val2[1] [7:0] $end
+        $var wire 8 ~! val3[0] [7:0] $end
+        $var wire 8 !" val3[1] [7:0] $end
         $scope module i_sub0 $end
-         $var wire 32 N% P0 [31:0] $end
-         $var wire 32 O% P1 [31:0] $end
-         $var wire 8 ~! out[0] [7:0] $end
-         $var wire 8 !" out[1] [7:0] $end
-        $upscope $end
-        $scope module i_sub1 $end
-         $var wire 32 N% P0 [31:0] $end
-         $var wire 32 O% P1 [31:0] $end
+         $var wire 32 R% P0 [31:0] $end
+         $var wire 32 S% P1 [31:0] $end
          $var wire 8 "" out[0] [7:0] $end
          $var wire 8 #" out[1] [7:0] $end
         $upscope $end
-        $scope module i_sub2 $end
-         $var wire 32 N% P0 [31:0] $end
-         $var wire 32 O% P1 [31:0] $end
+        $scope module i_sub1 $end
+         $var wire 32 R% P0 [31:0] $end
+         $var wire 32 S% P1 [31:0] $end
          $var wire 8 $" out[0] [7:0] $end
          $var wire 8 %" out[1] [7:0] $end
         $upscope $end
-        $scope module i_sub3 $end
-         $var wire 32 N% P0 [31:0] $end
-         $var wire 32 P% P1 [31:0] $end
+        $scope module i_sub2 $end
+         $var wire 32 R% P0 [31:0] $end
+         $var wire 32 S% P1 [31:0] $end
          $var wire 8 &" out[0] [7:0] $end
          $var wire 8 '" out[1] [7:0] $end
         $upscope $end
+        $scope module i_sub3 $end
+         $var wire 32 R% P0 [31:0] $end
+         $var wire 32 T% P1 [31:0] $end
+         $var wire 8 (" out[0] [7:0] $end
+         $var wire 8 )" out[1] [7:0] $end
+        $upscope $end
        $upscope $end
       $upscope $end
       $scope module i_sub4_1 $end
-       $var wire 32 I% P0 [31:0] $end
-       $var real 64 J% P1 $end
-       $var real 64 Q% P3 $end
-       $var wire 1 A% clk $end
-       $var wire 8 _" in [7:0] $end
-       $var wire 8 `" out [7:0] $end
-       $var wire 8 `" ff [7:0] $end
-       $var wire 128 A# sub5_in[0][0] [127:0] $end
-       $var wire 128 E# sub5_in[0][1] [127:0] $end
-       $var wire 128 I# sub5_in[0][2] [127:0] $end
-       $var wire 128 M# sub5_in[1][0] [127:0] $end
-       $var wire 128 Q# sub5_in[1][1] [127:0] $end
-       $var wire 128 U# sub5_in[1][2] [127:0] $end
-       $var wire 8 Y# sub5_out[0][0] [7:0] $end
-       $var wire 8 Z# sub5_out[0][1] [7:0] $end
-       $var wire 8 [# sub5_out[0][2] [7:0] $end
-       $var wire 8 \# sub5_out[1][0] [7:0] $end
-       $var wire 8 ]# sub5_out[1][1] [7:0] $end
-       $var wire 8 ^# sub5_out[1][2] [7:0] $end
-       $var wire 32 _# count [31:0] $end
-       $var wire 32 (" driven_from_bind [31:0] $end
+       $var wire 32 M% P0 [31:0] $end
+       $var real 64 N% P1 $end
+       $var real 64 U% P3 $end
+       $var wire 1 E% clk $end
+       $var wire 8 c" in [7:0] $end
+       $var wire 8 b" out [7:0] $end
+       $var wire 8 b" ff [7:0] $end
+       $var wire 128 D# sub5_in[0][0] [127:0] $end
+       $var wire 128 H# sub5_in[0][1] [127:0] $end
+       $var wire 128 L# sub5_in[0][2] [127:0] $end
+       $var wire 128 P# sub5_in[1][0] [127:0] $end
+       $var wire 128 T# sub5_in[1][1] [127:0] $end
+       $var wire 128 X# sub5_in[1][2] [127:0] $end
+       $var wire 8 \# sub5_out[0][0] [7:0] $end
+       $var wire 8 ]# sub5_out[0][1] [7:0] $end
+       $var wire 8 ^# sub5_out[0][2] [7:0] $end
+       $var wire 8 _# sub5_out[1][0] [7:0] $end
+       $var wire 8 `# sub5_out[1][1] [7:0] $end
+       $var wire 8 a# sub5_out[1][2] [7:0] $end
+       $var wire 32 b# count [31:0] $end
+       $var wire 32 *" driven_from_bind [31:0] $end
        $scope module i_sub4_bound $end
-        $var real 64 J% P1 $end
-        $var wire 32 (" driven_from_bind [31:0] $end
+        $var real 64 N% P1 $end
+        $var wire 32 *" driven_from_bind [31:0] $end
        $upscope $end
        $scope module i_sub5 $end
-        $var wire 1 A% clk $end
-        $var wire 128 `# in[0][0] [127:0] $end
-        $var wire 128 d# in[0][1] [127:0] $end
-        $var wire 128 h# in[0][2] [127:0] $end
-        $var wire 128 l# in[1][0] [127:0] $end
-        $var wire 128 p# in[1][1] [127:0] $end
-        $var wire 128 t# in[1][2] [127:0] $end
-        $var wire 8 x# out[0][0] [7:0] $end
-        $var wire 8 y# out[0][1] [7:0] $end
-        $var wire 8 z# out[0][2] [7:0] $end
-        $var wire 8 {# out[1][0] [7:0] $end
-        $var wire 8 |# out[1][1] [7:0] $end
-        $var wire 8 }# out[1][2] [7:0] $end
-        $var wire 32 ~# count [31:0] $end
-        $var wire 8 )" val0[0] [7:0] $end
-        $var wire 8 *" val0[1] [7:0] $end
-        $var wire 8 +" val1[0] [7:0] $end
-        $var wire 8 ," val1[1] [7:0] $end
-        $var wire 8 -" val2[0] [7:0] $end
-        $var wire 8 ." val2[1] [7:0] $end
-        $var wire 8 /" val3[0] [7:0] $end
-        $var wire 8 0" val3[1] [7:0] $end
+        $var wire 1 E% clk $end
+        $var wire 128 c# in[0][0] [127:0] $end
+        $var wire 128 g# in[0][1] [127:0] $end
+        $var wire 128 k# in[0][2] [127:0] $end
+        $var wire 128 o# in[1][0] [127:0] $end
+        $var wire 128 s# in[1][1] [127:0] $end
+        $var wire 128 w# in[1][2] [127:0] $end
+        $var wire 8 {# out[0][0] [7:0] $end
+        $var wire 8 |# out[0][1] [7:0] $end
+        $var wire 8 }# out[0][2] [7:0] $end
+        $var wire 8 ~# out[1][0] [7:0] $end
+        $var wire 8 !$ out[1][1] [7:0] $end
+        $var wire 8 "$ out[1][2] [7:0] $end
+        $var wire 32 #$ count [31:0] $end
+        $var wire 8 +" val0[0] [7:0] $end
+        $var wire 8 ," val0[1] [7:0] $end
+        $var wire 8 -" val1[0] [7:0] $end
+        $var wire 8 ." val1[1] [7:0] $end
+        $var wire 8 /" val2[0] [7:0] $end
+        $var wire 8 0" val2[1] [7:0] $end
+        $var wire 8 1" val3[0] [7:0] $end
+        $var wire 8 2" val3[1] [7:0] $end
         $scope module i_sub0 $end
-         $var wire 32 N% P0 [31:0] $end
-         $var wire 32 O% P1 [31:0] $end
-         $var wire 8 1" out[0] [7:0] $end
-         $var wire 8 2" out[1] [7:0] $end
-        $upscope $end
-        $scope module i_sub1 $end
-         $var wire 32 N% P0 [31:0] $end
-         $var wire 32 O% P1 [31:0] $end
+         $var wire 32 R% P0 [31:0] $end
+         $var wire 32 S% P1 [31:0] $end
          $var wire 8 3" out[0] [7:0] $end
          $var wire 8 4" out[1] [7:0] $end
         $upscope $end
-        $scope module i_sub2 $end
-         $var wire 32 N% P0 [31:0] $end
-         $var wire 32 O% P1 [31:0] $end
+        $scope module i_sub1 $end
+         $var wire 32 R% P0 [31:0] $end
+         $var wire 32 S% P1 [31:0] $end
          $var wire 8 5" out[0] [7:0] $end
          $var wire 8 6" out[1] [7:0] $end
         $upscope $end
-        $scope module i_sub3 $end
-         $var wire 32 N% P0 [31:0] $end
-         $var wire 32 P% P1 [31:0] $end
+        $scope module i_sub2 $end
+         $var wire 32 R% P0 [31:0] $end
+         $var wire 32 S% P1 [31:0] $end
          $var wire 8 7" out[0] [7:0] $end
          $var wire 8 8" out[1] [7:0] $end
         $upscope $end
+        $scope module i_sub3 $end
+         $var wire 32 R% P0 [31:0] $end
+         $var wire 32 T% P1 [31:0] $end
+         $var wire 8 9" out[0] [7:0] $end
+         $var wire 8 :" out[1] [7:0] $end
+        $upscope $end
        $upscope $end
       $upscope $end
      $upscope $end
      $scope module i_sub3_2 $end
-      $var wire 8 D% P0 [7:0] $end
-      $var wire 32 S% UNPACKED_ARRAY[0] [31:0] $end
-      $var wire 32 T% UNPACKED_ARRAY[1] [31:0] $end
-      $var wire 16 G% UNUSED [15:0] $end
-      $var wire 2 H% ENUM [1:0] $end
-      $var wire 1 A% clk $end
-      $var wire 8 [" in [7:0] $end
-      $var wire 8 ^" out [7:0] $end
-      $var wire 8 !$ ff [7:0] $end
-      $var wire 8 ^" out4 [7:0] $end
-      $var wire 8 "$ out4_2 [7:0] $end
+      $var wire 8 H% P0 [7:0] $end
+      $var wire 32 W% UNPACKED_ARRAY[0] [31:0] $end
+      $var wire 32 X% UNPACKED_ARRAY[1] [31:0] $end
+      $var wire 16 K% UNUSED [15:0] $end
+      $var wire 2 L% ENUM [1:0] $end
+      $var wire 1 E% clk $end
+      $var wire 8 ]" in [7:0] $end
+      $var wire 8 `" out [7:0] $end
+      $var wire 8 $$ ff [7:0] $end
+      $var wire 8 `" out4 [7:0] $end
+      $var wire 8 %$ out4_2 [7:0] $end
       $scope module i_sub4_0 $end
-       $var wire 32 I% P0 [31:0] $end
-       $var real 64 J% P1 $end
-       $var real 64 L% P3 $end
-       $var wire 1 A% clk $end
-       $var wire 8 !$ in [7:0] $end
-       $var wire 8 ^" out [7:0] $end
-       $var wire 8 ^" ff [7:0] $end
-       $var wire 128 #$ sub5_in[0][0] [127:0] $end
-       $var wire 128 '$ sub5_in[0][1] [127:0] $end
-       $var wire 128 +$ sub5_in[0][2] [127:0] $end
-       $var wire 128 /$ sub5_in[1][0] [127:0] $end
-       $var wire 128 3$ sub5_in[1][1] [127:0] $end
-       $var wire 128 7$ sub5_in[1][2] [127:0] $end
-       $var wire 8 ;$ sub5_out[0][0] [7:0] $end
-       $var wire 8 <$ sub5_out[0][1] [7:0] $end
-       $var wire 8 =$ sub5_out[0][2] [7:0] $end
-       $var wire 8 >$ sub5_out[1][0] [7:0] $end
-       $var wire 8 ?$ sub5_out[1][1] [7:0] $end
-       $var wire 8 @$ sub5_out[1][2] [7:0] $end
-       $var wire 32 A$ count [31:0] $end
-       $var wire 32 9" driven_from_bind [31:0] $end
+       $var wire 32 M% P0 [31:0] $end
+       $var real 64 N% P1 $end
+       $var real 64 P% P3 $end
+       $var wire 1 E% clk $end
+       $var wire 8 &$ in [7:0] $end
+       $var wire 8 `" out [7:0] $end
+       $var wire 8 `" ff [7:0] $end
+       $var wire 128 '$ sub5_in[0][0] [127:0] $end
+       $var wire 128 +$ sub5_in[0][1] [127:0] $end
+       $var wire 128 /$ sub5_in[0][2] [127:0] $end
+       $var wire 128 3$ sub5_in[1][0] [127:0] $end
+       $var wire 128 7$ sub5_in[1][1] [127:0] $end
+       $var wire 128 ;$ sub5_in[1][2] [127:0] $end
+       $var wire 8 ?$ sub5_out[0][0] [7:0] $end
+       $var wire 8 @$ sub5_out[0][1] [7:0] $end
+       $var wire 8 A$ sub5_out[0][2] [7:0] $end
+       $var wire 8 B$ sub5_out[1][0] [7:0] $end
+       $var wire 8 C$ sub5_out[1][1] [7:0] $end
+       $var wire 8 D$ sub5_out[1][2] [7:0] $end
+       $var wire 32 E$ count [31:0] $end
+       $var wire 32 ;" driven_from_bind [31:0] $end
        $scope module i_sub4_bound $end
-        $var real 64 J% P1 $end
-        $var wire 32 9" driven_from_bind [31:0] $end
+        $var real 64 N% P1 $end
+        $var wire 32 ;" driven_from_bind [31:0] $end
        $upscope $end
        $scope module i_sub5 $end
-        $var wire 1 A% clk $end
-        $var wire 128 B$ in[0][0] [127:0] $end
-        $var wire 128 F$ in[0][1] [127:0] $end
-        $var wire 128 J$ in[0][2] [127:0] $end
-        $var wire 128 N$ in[1][0] [127:0] $end
-        $var wire 128 R$ in[1][1] [127:0] $end
-        $var wire 128 V$ in[1][2] [127:0] $end
-        $var wire 8 Z$ out[0][0] [7:0] $end
-        $var wire 8 [$ out[0][1] [7:0] $end
-        $var wire 8 \$ out[0][2] [7:0] $end
-        $var wire 8 ]$ out[1][0] [7:0] $end
-        $var wire 8 ^$ out[1][1] [7:0] $end
-        $var wire 8 _$ out[1][2] [7:0] $end
-        $var wire 32 `$ count [31:0] $end
-        $var wire 8 :" val0[0] [7:0] $end
-        $var wire 8 ;" val0[1] [7:0] $end
-        $var wire 8 <" val1[0] [7:0] $end
-        $var wire 8 =" val1[1] [7:0] $end
-        $var wire 8 >" val2[0] [7:0] $end
-        $var wire 8 ?" val2[1] [7:0] $end
-        $var wire 8 @" val3[0] [7:0] $end
-        $var wire 8 A" val3[1] [7:0] $end
+        $var wire 1 E% clk $end
+        $var wire 128 F$ in[0][0] [127:0] $end
+        $var wire 128 J$ in[0][1] [127:0] $end
+        $var wire 128 N$ in[0][2] [127:0] $end
+        $var wire 128 R$ in[1][0] [127:0] $end
+        $var wire 128 V$ in[1][1] [127:0] $end
+        $var wire 128 Z$ in[1][2] [127:0] $end
+        $var wire 8 ^$ out[0][0] [7:0] $end
+        $var wire 8 _$ out[0][1] [7:0] $end
+        $var wire 8 `$ out[0][2] [7:0] $end
+        $var wire 8 a$ out[1][0] [7:0] $end
+        $var wire 8 b$ out[1][1] [7:0] $end
+        $var wire 8 c$ out[1][2] [7:0] $end
+        $var wire 32 d$ count [31:0] $end
+        $var wire 8 <" val0[0] [7:0] $end
+        $var wire 8 =" val0[1] [7:0] $end
+        $var wire 8 >" val1[0] [7:0] $end
+        $var wire 8 ?" val1[1] [7:0] $end
+        $var wire 8 @" val2[0] [7:0] $end
+        $var wire 8 A" val2[1] [7:0] $end
+        $var wire 8 B" val3[0] [7:0] $end
+        $var wire 8 C" val3[1] [7:0] $end
         $scope module i_sub0 $end
-         $var wire 32 N% P0 [31:0] $end
-         $var wire 32 O% P1 [31:0] $end
-         $var wire 8 B" out[0] [7:0] $end
-         $var wire 8 C" out[1] [7:0] $end
-        $upscope $end
-        $scope module i_sub1 $end
-         $var wire 32 N% P0 [31:0] $end
-         $var wire 32 O% P1 [31:0] $end
+         $var wire 32 R% P0 [31:0] $end
+         $var wire 32 S% P1 [31:0] $end
          $var wire 8 D" out[0] [7:0] $end
          $var wire 8 E" out[1] [7:0] $end
         $upscope $end
-        $scope module i_sub2 $end
-         $var wire 32 N% P0 [31:0] $end
-         $var wire 32 O% P1 [31:0] $end
+        $scope module i_sub1 $end
+         $var wire 32 R% P0 [31:0] $end
+         $var wire 32 S% P1 [31:0] $end
          $var wire 8 F" out[0] [7:0] $end
          $var wire 8 G" out[1] [7:0] $end
         $upscope $end
-        $scope module i_sub3 $end
-         $var wire 32 N% P0 [31:0] $end
-         $var wire 32 P% P1 [31:0] $end
+        $scope module i_sub2 $end
+         $var wire 32 R% P0 [31:0] $end
+         $var wire 32 S% P1 [31:0] $end
          $var wire 8 H" out[0] [7:0] $end
          $var wire 8 I" out[1] [7:0] $end
         $upscope $end
+        $scope module i_sub3 $end
+         $var wire 32 R% P0 [31:0] $end
+         $var wire 32 T% P1 [31:0] $end
+         $var wire 8 J" out[0] [7:0] $end
+         $var wire 8 K" out[1] [7:0] $end
+        $upscope $end
        $upscope $end
       $upscope $end
       $scope module i_sub4_1 $end
-       $var wire 32 I% P0 [31:0] $end
-       $var real 64 J% P1 $end
-       $var real 64 Q% P3 $end
-       $var wire 1 A% clk $end
-       $var wire 8 !$ in [7:0] $end
-       $var wire 8 "$ out [7:0] $end
-       $var wire 8 "$ ff [7:0] $end
-       $var wire 128 a$ sub5_in[0][0] [127:0] $end
-       $var wire 128 e$ sub5_in[0][1] [127:0] $end
-       $var wire 128 i$ sub5_in[0][2] [127:0] $end
-       $var wire 128 m$ sub5_in[1][0] [127:0] $end
-       $var wire 128 q$ sub5_in[1][1] [127:0] $end
-       $var wire 128 u$ sub5_in[1][2] [127:0] $end
-       $var wire 8 y$ sub5_out[0][0] [7:0] $end
-       $var wire 8 z$ sub5_out[0][1] [7:0] $end
-       $var wire 8 {$ sub5_out[0][2] [7:0] $end
-       $var wire 8 |$ sub5_out[1][0] [7:0] $end
-       $var wire 8 }$ sub5_out[1][1] [7:0] $end
-       $var wire 8 ~$ sub5_out[1][2] [7:0] $end
-       $var wire 32 !% count [31:0] $end
-       $var wire 32 J" driven_from_bind [31:0] $end
+       $var wire 32 M% P0 [31:0] $end
+       $var real 64 N% P1 $end
+       $var real 64 U% P3 $end
+       $var wire 1 E% clk $end
+       $var wire 8 &$ in [7:0] $end
+       $var wire 8 %$ out [7:0] $end
+       $var wire 8 %$ ff [7:0] $end
+       $var wire 128 e$ sub5_in[0][0] [127:0] $end
+       $var wire 128 i$ sub5_in[0][1] [127:0] $end
+       $var wire 128 m$ sub5_in[0][2] [127:0] $end
+       $var wire 128 q$ sub5_in[1][0] [127:0] $end
+       $var wire 128 u$ sub5_in[1][1] [127:0] $end
+       $var wire 128 y$ sub5_in[1][2] [127:0] $end
+       $var wire 8 }$ sub5_out[0][0] [7:0] $end
+       $var wire 8 ~$ sub5_out[0][1] [7:0] $end
+       $var wire 8 !% sub5_out[0][2] [7:0] $end
+       $var wire 8 "% sub5_out[1][0] [7:0] $end
+       $var wire 8 #% sub5_out[1][1] [7:0] $end
+       $var wire 8 $% sub5_out[1][2] [7:0] $end
+       $var wire 32 %% count [31:0] $end
+       $var wire 32 L" driven_from_bind [31:0] $end
        $scope module i_sub4_bound $end
-        $var real 64 J% P1 $end
-        $var wire 32 J" driven_from_bind [31:0] $end
+        $var real 64 N% P1 $end
+        $var wire 32 L" driven_from_bind [31:0] $end
        $upscope $end
        $scope module i_sub5 $end
-        $var wire 1 A% clk $end
-        $var wire 128 "% in[0][0] [127:0] $end
-        $var wire 128 &% in[0][1] [127:0] $end
-        $var wire 128 *% in[0][2] [127:0] $end
-        $var wire 128 .% in[1][0] [127:0] $end
-        $var wire 128 2% in[1][1] [127:0] $end
-        $var wire 128 6% in[1][2] [127:0] $end
-        $var wire 8 :% out[0][0] [7:0] $end
-        $var wire 8 ;% out[0][1] [7:0] $end
-        $var wire 8 <% out[0][2] [7:0] $end
-        $var wire 8 =% out[1][0] [7:0] $end
-        $var wire 8 >% out[1][1] [7:0] $end
-        $var wire 8 ?% out[1][2] [7:0] $end
-        $var wire 32 @% count [31:0] $end
-        $var wire 8 K" val0[0] [7:0] $end
-        $var wire 8 L" val0[1] [7:0] $end
-        $var wire 8 M" val1[0] [7:0] $end
-        $var wire 8 N" val1[1] [7:0] $end
-        $var wire 8 O" val2[0] [7:0] $end
-        $var wire 8 P" val2[1] [7:0] $end
-        $var wire 8 Q" val3[0] [7:0] $end
-        $var wire 8 R" val3[1] [7:0] $end
+        $var wire 1 E% clk $end
+        $var wire 128 &% in[0][0] [127:0] $end
+        $var wire 128 *% in[0][1] [127:0] $end
+        $var wire 128 .% in[0][2] [127:0] $end
+        $var wire 128 2% in[1][0] [127:0] $end
+        $var wire 128 6% in[1][1] [127:0] $end
+        $var wire 128 :% in[1][2] [127:0] $end
+        $var wire 8 >% out[0][0] [7:0] $end
+        $var wire 8 ?% out[0][1] [7:0] $end
+        $var wire 8 @% out[0][2] [7:0] $end
+        $var wire 8 A% out[1][0] [7:0] $end
+        $var wire 8 B% out[1][1] [7:0] $end
+        $var wire 8 C% out[1][2] [7:0] $end
+        $var wire 32 D% count [31:0] $end
+        $var wire 8 M" val0[0] [7:0] $end
+        $var wire 8 N" val0[1] [7:0] $end
+        $var wire 8 O" val1[0] [7:0] $end
+        $var wire 8 P" val1[1] [7:0] $end
+        $var wire 8 Q" val2[0] [7:0] $end
+        $var wire 8 R" val2[1] [7:0] $end
+        $var wire 8 S" val3[0] [7:0] $end
+        $var wire 8 T" val3[1] [7:0] $end
         $scope module i_sub0 $end
-         $var wire 32 N% P0 [31:0] $end
-         $var wire 32 O% P1 [31:0] $end
-         $var wire 8 S" out[0] [7:0] $end
-         $var wire 8 T" out[1] [7:0] $end
-        $upscope $end
-        $scope module i_sub1 $end
-         $var wire 32 N% P0 [31:0] $end
-         $var wire 32 O% P1 [31:0] $end
+         $var wire 32 R% P0 [31:0] $end
+         $var wire 32 S% P1 [31:0] $end
          $var wire 8 U" out[0] [7:0] $end
          $var wire 8 V" out[1] [7:0] $end
         $upscope $end
-        $scope module i_sub2 $end
-         $var wire 32 N% P0 [31:0] $end
-         $var wire 32 O% P1 [31:0] $end
+        $scope module i_sub1 $end
+         $var wire 32 R% P0 [31:0] $end
+         $var wire 32 S% P1 [31:0] $end
          $var wire 8 W" out[0] [7:0] $end
          $var wire 8 X" out[1] [7:0] $end
         $upscope $end
-        $scope module i_sub3 $end
-         $var wire 32 N% P0 [31:0] $end
-         $var wire 32 P% P1 [31:0] $end
+        $scope module i_sub2 $end
+         $var wire 32 R% P0 [31:0] $end
+         $var wire 32 S% P1 [31:0] $end
          $var wire 8 Y" out[0] [7:0] $end
          $var wire 8 Z" out[1] [7:0] $end
         $upscope $end
+        $scope module i_sub3 $end
+         $var wire 32 R% P0 [31:0] $end
+         $var wire 32 T% P1 [31:0] $end
+         $var wire 8 [" out[0] [7:0] $end
+         $var wire 8 \" out[1] [7:0] $end
+        $upscope $end
        $upscope $end
       $upscope $end
      $upscope $end
      $scope module in $end
-      $var wire 1 A% clk $end
-      $var wire 8 [" data [7:0] $end
+      $var wire 1 E% clk $end
+      $var wire 8 ]" data [7:0] $end
      $upscope $end
      $scope module out $end
-      $var wire 1 A% clk $end
-      $var wire 8 ]" data [7:0] $end
+      $var wire 1 E% clk $end
+      $var wire 8 _" data [7:0] $end
      $upscope $end
     $upscope $end
     $scope module in_ifs $end
-     $var wire 1 A% clk $end
-     $var wire 8 [" data [7:0] $end
+     $var wire 1 E% clk $end
+     $var wire 8 ]" data [7:0] $end
     $upscope $end
     $scope module out_ifs $end
-     $var wire 1 A% clk $end
-     $var wire 8 ]" data [7:0] $end
+     $var wire 1 E% clk $end
+     $var wire 8 _" data [7:0] $end
     $upscope $end
    $upscope $end
    $scope module i_sub3 $end
-    $var wire 8 [! P0 [7:0] $end
-    $var wire 32 \! UNPACKED_ARRAY[0] [31:0] $end
-    $var wire 32 ]! UNPACKED_ARRAY[1] [31:0] $end
-    $var wire 16 ^! UNUSED [15:0] $end
-    $var wire 2 _! ENUM [1:0] $end
-    $var wire 1 R! clk $end
-    $var wire 8 9! in [7:0] $end
-    $var wire 8 S! out [7:0] $end
-    $var wire 8 T! ff [7:0] $end
-    $var wire 8 S! out4 [7:0] $end
+    $var wire 8 ]! P0 [7:0] $end
+    $var wire 32 ^! UNPACKED_ARRAY[0] [31:0] $end
+    $var wire 32 _! UNPACKED_ARRAY[1] [31:0] $end
+    $var wire 16 `! UNUSED [15:0] $end
+    $var wire 2 a! ENUM [1:0] $end
+    $var wire 1 V! clk $end
+    $var wire 8 =! in [7:0] $end
+    $var wire 8 8! out [7:0] $end
+    $var wire 8 9! ff [7:0] $end
+    $var wire 8 8! out4 [7:0] $end
     $var wire 8 - out4_2 [7:0] $end
     $scope module i_sub4_0 $end
-     $var wire 32 `! P0 [31:0] $end
-     $var real 64 a! P1 $end
-     $var real 64 c! P3 $end
-     $var wire 1 R! clk $end
-     $var wire 8 T! in [7:0] $end
-     $var wire 8 S! out [7:0] $end
-     $var wire 8 S! ff [7:0] $end
+     $var wire 32 b! P0 [31:0] $end
+     $var real 64 c! P1 $end
+     $var real 64 e! P3 $end
+     $var wire 1 V! clk $end
+     $var wire 8 :! in [7:0] $end
+     $var wire 8 8! out [7:0] $end
+     $var wire 8 8! ff [7:0] $end
      $var wire 128 . sub5_in[0][0] [127:0] $end
      $var wire 128 2 sub5_in[0][1] [127:0] $end
      $var wire 128 6 sub5_in[0][2] [127:0] $end
      $var wire 128 : sub5_in[1][0] [127:0] $end
      $var wire 128 > sub5_in[1][1] [127:0] $end
      $var wire 128 B sub5_in[1][2] [127:0] $end
-     $var wire 8 :! sub5_out[0][0] [7:0] $end
-     $var wire 8 ;! sub5_out[0][1] [7:0] $end
-     $var wire 8 <! sub5_out[0][2] [7:0] $end
-     $var wire 8 =! sub5_out[1][0] [7:0] $end
-     $var wire 8 >! sub5_out[1][1] [7:0] $end
-     $var wire 8 ?! sub5_out[1][2] [7:0] $end
+     $var wire 8 >! sub5_out[0][0] [7:0] $end
+     $var wire 8 ?! sub5_out[0][1] [7:0] $end
+     $var wire 8 @! sub5_out[0][2] [7:0] $end
+     $var wire 8 A! sub5_out[1][0] [7:0] $end
+     $var wire 8 B! sub5_out[1][1] [7:0] $end
+     $var wire 8 C! sub5_out[1][2] [7:0] $end
      $var wire 32 F count [31:0] $end
      $var wire 32 " driven_from_bind [31:0] $end
      $scope module i_sub4_bound $end
-      $var real 64 a! P1 $end
+      $var real 64 c! P1 $end
       $var wire 32 " driven_from_bind [31:0] $end
      $upscope $end
      $scope module i_sub5 $end
-      $var wire 1 '& clk $end
-      $var wire 128 f% in[0][0] [127:0] $end
-      $var wire 128 j% in[0][1] [127:0] $end
-      $var wire 128 n% in[0][2] [127:0] $end
-      $var wire 128 r% in[1][0] [127:0] $end
-      $var wire 128 v% in[1][1] [127:0] $end
-      $var wire 128 z% in[1][2] [127:0] $end
-      $var wire 8 ~% out[0][0] [7:0] $end
-      $var wire 8 !& out[0][1] [7:0] $end
-      $var wire 8 "& out[0][2] [7:0] $end
-      $var wire 8 #& out[1][0] [7:0] $end
-      $var wire 8 $& out[1][1] [7:0] $end
-      $var wire 8 %& out[1][2] [7:0] $end
-      $var wire 32 && count [31:0] $end
-      $var wire 8 V% val0[0] [7:0] $end
-      $var wire 8 W% val0[1] [7:0] $end
-      $var wire 8 X% val1[0] [7:0] $end
-      $var wire 8 Y% val1[1] [7:0] $end
-      $var wire 8 Z% val2[0] [7:0] $end
-      $var wire 8 [% val2[1] [7:0] $end
-      $var wire 8 \% val3[0] [7:0] $end
-      $var wire 8 ]% val3[1] [7:0] $end
+      $var wire 1 +& clk $end
+      $var wire 128 j% in[0][0] [127:0] $end
+      $var wire 128 n% in[0][1] [127:0] $end
+      $var wire 128 r% in[0][2] [127:0] $end
+      $var wire 128 v% in[1][0] [127:0] $end
+      $var wire 128 z% in[1][1] [127:0] $end
+      $var wire 128 ~% in[1][2] [127:0] $end
+      $var wire 8 $& out[0][0] [7:0] $end
+      $var wire 8 %& out[0][1] [7:0] $end
+      $var wire 8 && out[0][2] [7:0] $end
+      $var wire 8 '& out[1][0] [7:0] $end
+      $var wire 8 (& out[1][1] [7:0] $end
+      $var wire 8 )& out[1][2] [7:0] $end
+      $var wire 32 *& count [31:0] $end
+      $var wire 8 Z% val0[0] [7:0] $end
+      $var wire 8 [% val0[1] [7:0] $end
+      $var wire 8 \% val1[0] [7:0] $end
+      $var wire 8 ]% val1[1] [7:0] $end
+      $var wire 8 ^% val2[0] [7:0] $end
+      $var wire 8 _% val2[1] [7:0] $end
+      $var wire 8 `% val3[0] [7:0] $end
+      $var wire 8 a% val3[1] [7:0] $end
       $scope module $libroot $end
-       $var wire 1 +& global_flag $end
+       $var wire 1 /& global_flag $end
       $upscope $end
       $scope module i_sub0 $end
-       $var wire 32 (& P0 [31:0] $end
-       $var wire 32 )& P1 [31:0] $end
-       $var wire 8 ^% out[0] [7:0] $end
-       $var wire 8 _% out[1] [7:0] $end
-      $upscope $end
-      $scope module i_sub1 $end
-       $var wire 32 (& P0 [31:0] $end
-       $var wire 32 )& P1 [31:0] $end
-       $var wire 8 `% out[0] [7:0] $end
-       $var wire 8 a% out[1] [7:0] $end
-      $upscope $end
-      $scope module i_sub2 $end
-       $var wire 32 (& P0 [31:0] $end
-       $var wire 32 )& P1 [31:0] $end
+       $var wire 32 ,& P0 [31:0] $end
+       $var wire 32 -& P1 [31:0] $end
        $var wire 8 b% out[0] [7:0] $end
        $var wire 8 c% out[1] [7:0] $end
       $upscope $end
-      $scope module i_sub3 $end
-       $var wire 32 (& P0 [31:0] $end
-       $var wire 32 *& P1 [31:0] $end
+      $scope module i_sub1 $end
+       $var wire 32 ,& P0 [31:0] $end
+       $var wire 32 -& P1 [31:0] $end
        $var wire 8 d% out[0] [7:0] $end
        $var wire 8 e% out[1] [7:0] $end
       $upscope $end
+      $scope module i_sub2 $end
+       $var wire 32 ,& P0 [31:0] $end
+       $var wire 32 -& P1 [31:0] $end
+       $var wire 8 f% out[0] [7:0] $end
+       $var wire 8 g% out[1] [7:0] $end
+      $upscope $end
+      $scope module i_sub3 $end
+       $var wire 32 ,& P0 [31:0] $end
+       $var wire 32 .& P1 [31:0] $end
+       $var wire 8 h% out[0] [7:0] $end
+       $var wire 8 i% out[1] [7:0] $end
+      $upscope $end
      $upscope $end
     $upscope $end
     $scope module i_sub4_1 $end
-     $var wire 32 `! P0 [31:0] $end
-     $var real 64 a! P1 $end
-     $var real 64 e! P3 $end
-     $var wire 1 R! clk $end
-     $var wire 8 T! in [7:0] $end
+     $var wire 32 b! P0 [31:0] $end
+     $var real 64 c! P1 $end
+     $var real 64 g! P3 $end
+     $var wire 1 V! clk $end
+     $var wire 8 :! in [7:0] $end
      $var wire 8 - out [7:0] $end
      $var wire 8 - ff [7:0] $end
      $var wire 128 G sub5_in[0][0] [127:0] $end
@@ -551,237 +551,237 @@ $timescale 1ps $end
      $var wire 128 S sub5_in[1][0] [127:0] $end
      $var wire 128 W sub5_in[1][1] [127:0] $end
      $var wire 128 [ sub5_in[1][2] [127:0] $end
-     $var wire 8 @! sub5_out[0][0] [7:0] $end
-     $var wire 8 A! sub5_out[0][1] [7:0] $end
-     $var wire 8 B! sub5_out[0][2] [7:0] $end
-     $var wire 8 C! sub5_out[1][0] [7:0] $end
-     $var wire 8 D! sub5_out[1][1] [7:0] $end
-     $var wire 8 E! sub5_out[1][2] [7:0] $end
+     $var wire 8 D! sub5_out[0][0] [7:0] $end
+     $var wire 8 E! sub5_out[0][1] [7:0] $end
+     $var wire 8 F! sub5_out[0][2] [7:0] $end
+     $var wire 8 G! sub5_out[1][0] [7:0] $end
+     $var wire 8 H! sub5_out[1][1] [7:0] $end
+     $var wire 8 I! sub5_out[1][2] [7:0] $end
      $var wire 32 _ count [31:0] $end
      $var wire 32 # driven_from_bind [31:0] $end
      $scope module i_sub4_bound $end
-      $var real 64 a! P1 $end
+      $var real 64 c! P1 $end
       $var wire 32 # driven_from_bind [31:0] $end
      $upscope $end
      $scope module i_sub5 $end
-      $var wire 1 [& clk $end
-      $var wire 128 <& in[0][0] [127:0] $end
-      $var wire 128 @& in[0][1] [127:0] $end
-      $var wire 128 D& in[0][2] [127:0] $end
-      $var wire 128 H& in[1][0] [127:0] $end
-      $var wire 128 L& in[1][1] [127:0] $end
-      $var wire 128 P& in[1][2] [127:0] $end
-      $var wire 8 T& out[0][0] [7:0] $end
-      $var wire 8 U& out[0][1] [7:0] $end
-      $var wire 8 V& out[0][2] [7:0] $end
-      $var wire 8 W& out[1][0] [7:0] $end
-      $var wire 8 X& out[1][1] [7:0] $end
-      $var wire 8 Y& out[1][2] [7:0] $end
-      $var wire 32 Z& count [31:0] $end
-      $var wire 8 ,& val0[0] [7:0] $end
-      $var wire 8 -& val0[1] [7:0] $end
-      $var wire 8 .& val1[0] [7:0] $end
-      $var wire 8 /& val1[1] [7:0] $end
-      $var wire 8 0& val2[0] [7:0] $end
-      $var wire 8 1& val2[1] [7:0] $end
-      $var wire 8 2& val3[0] [7:0] $end
-      $var wire 8 3& val3[1] [7:0] $end
+      $var wire 1 _& clk $end
+      $var wire 128 @& in[0][0] [127:0] $end
+      $var wire 128 D& in[0][1] [127:0] $end
+      $var wire 128 H& in[0][2] [127:0] $end
+      $var wire 128 L& in[1][0] [127:0] $end
+      $var wire 128 P& in[1][1] [127:0] $end
+      $var wire 128 T& in[1][2] [127:0] $end
+      $var wire 8 X& out[0][0] [7:0] $end
+      $var wire 8 Y& out[0][1] [7:0] $end
+      $var wire 8 Z& out[0][2] [7:0] $end
+      $var wire 8 [& out[1][0] [7:0] $end
+      $var wire 8 \& out[1][1] [7:0] $end
+      $var wire 8 ]& out[1][2] [7:0] $end
+      $var wire 32 ^& count [31:0] $end
+      $var wire 8 0& val0[0] [7:0] $end
+      $var wire 8 1& val0[1] [7:0] $end
+      $var wire 8 2& val1[0] [7:0] $end
+      $var wire 8 3& val1[1] [7:0] $end
+      $var wire 8 4& val2[0] [7:0] $end
+      $var wire 8 5& val2[1] [7:0] $end
+      $var wire 8 6& val3[0] [7:0] $end
+      $var wire 8 7& val3[1] [7:0] $end
       $scope module $libroot $end
-       $var wire 1 _& global_flag $end
+       $var wire 1 c& global_flag $end
       $upscope $end
       $scope module i_sub0 $end
-       $var wire 32 \& P0 [31:0] $end
-       $var wire 32 ]& P1 [31:0] $end
-       $var wire 8 4& out[0] [7:0] $end
-       $var wire 8 5& out[1] [7:0] $end
-      $upscope $end
-      $scope module i_sub1 $end
-       $var wire 32 \& P0 [31:0] $end
-       $var wire 32 ]& P1 [31:0] $end
-       $var wire 8 6& out[0] [7:0] $end
-       $var wire 8 7& out[1] [7:0] $end
-      $upscope $end
-      $scope module i_sub2 $end
-       $var wire 32 \& P0 [31:0] $end
-       $var wire 32 ]& P1 [31:0] $end
+       $var wire 32 `& P0 [31:0] $end
+       $var wire 32 a& P1 [31:0] $end
        $var wire 8 8& out[0] [7:0] $end
        $var wire 8 9& out[1] [7:0] $end
       $upscope $end
-      $scope module i_sub3 $end
-       $var wire 32 \& P0 [31:0] $end
-       $var wire 32 ^& P1 [31:0] $end
+      $scope module i_sub1 $end
+       $var wire 32 `& P0 [31:0] $end
+       $var wire 32 a& P1 [31:0] $end
        $var wire 8 :& out[0] [7:0] $end
        $var wire 8 ;& out[1] [7:0] $end
       $upscope $end
+      $scope module i_sub2 $end
+       $var wire 32 `& P0 [31:0] $end
+       $var wire 32 a& P1 [31:0] $end
+       $var wire 8 <& out[0] [7:0] $end
+       $var wire 8 =& out[1] [7:0] $end
+      $upscope $end
+      $scope module i_sub3 $end
+       $var wire 32 `& P0 [31:0] $end
+       $var wire 32 b& P1 [31:0] $end
+       $var wire 8 >& out[0] [7:0] $end
+       $var wire 8 ?& out[1] [7:0] $end
+      $upscope $end
      $upscope $end
     $upscope $end
    $upscope $end
    $scope module i_sub3_2 $end
-    $var wire 8 [! P0 [7:0] $end
-    $var wire 32 g! UNPACKED_ARRAY[0] [31:0] $end
-    $var wire 32 h! UNPACKED_ARRAY[1] [31:0] $end
-    $var wire 16 ^! UNUSED [15:0] $end
-    $var wire 2 _! ENUM [1:0] $end
-    $var wire 1 R! clk $end
-    $var wire 8 9! in [7:0] $end
+    $var wire 8 ]! P0 [7:0] $end
+    $var wire 32 i! UNPACKED_ARRAY[0] [31:0] $end
+    $var wire 32 j! UNPACKED_ARRAY[1] [31:0] $end
+    $var wire 16 `! UNUSED [15:0] $end
+    $var wire 2 a! ENUM [1:0] $end
+    $var wire 1 V! clk $end
+    $var wire 8 =! in [7:0] $end
     $var wire 8 & out [7:0] $end
     $var wire 8 ` ff [7:0] $end
     $var wire 8 & out4 [7:0] $end
     $var wire 8 a out4_2 [7:0] $end
     $scope module i_sub4_0 $end
-     $var wire 32 `! P0 [31:0] $end
-     $var real 64 a! P1 $end
-     $var real 64 c! P3 $end
-     $var wire 1 R! clk $end
-     $var wire 8 ` in [7:0] $end
+     $var wire 32 b! P0 [31:0] $end
+     $var real 64 c! P1 $end
+     $var real 64 e! P3 $end
+     $var wire 1 V! clk $end
+     $var wire 8 b in [7:0] $end
      $var wire 8 & out [7:0] $end
      $var wire 8 & ff [7:0] $end
-     $var wire 128 b sub5_in[0][0] [127:0] $end
-     $var wire 128 f sub5_in[0][1] [127:0] $end
-     $var wire 128 j sub5_in[0][2] [127:0] $end
-     $var wire 128 n sub5_in[1][0] [127:0] $end
-     $var wire 128 r sub5_in[1][1] [127:0] $end
-     $var wire 128 v sub5_in[1][2] [127:0] $end
-     $var wire 8 F! sub5_out[0][0] [7:0] $end
-     $var wire 8 G! sub5_out[0][1] [7:0] $end
-     $var wire 8 H! sub5_out[0][2] [7:0] $end
-     $var wire 8 I! sub5_out[1][0] [7:0] $end
-     $var wire 8 J! sub5_out[1][1] [7:0] $end
-     $var wire 8 K! sub5_out[1][2] [7:0] $end
-     $var wire 32 z count [31:0] $end
+     $var wire 128 c sub5_in[0][0] [127:0] $end
+     $var wire 128 g sub5_in[0][1] [127:0] $end
+     $var wire 128 k sub5_in[0][2] [127:0] $end
+     $var wire 128 o sub5_in[1][0] [127:0] $end
+     $var wire 128 s sub5_in[1][1] [127:0] $end
+     $var wire 128 w sub5_in[1][2] [127:0] $end
+     $var wire 8 J! sub5_out[0][0] [7:0] $end
+     $var wire 8 K! sub5_out[0][1] [7:0] $end
+     $var wire 8 L! sub5_out[0][2] [7:0] $end
+     $var wire 8 M! sub5_out[1][0] [7:0] $end
+     $var wire 8 N! sub5_out[1][1] [7:0] $end
+     $var wire 8 O! sub5_out[1][2] [7:0] $end
+     $var wire 32 { count [31:0] $end
      $var wire 32 $ driven_from_bind [31:0] $end
      $scope module i_sub4_bound $end
-      $var real 64 a! P1 $end
+      $var real 64 c! P1 $end
       $var wire 32 $ driven_from_bind [31:0] $end
      $upscope $end
      $scope module i_sub5 $end
-      $var wire 1 1' clk $end
-      $var wire 128 p& in[0][0] [127:0] $end
-      $var wire 128 t& in[0][1] [127:0] $end
-      $var wire 128 x& in[0][2] [127:0] $end
-      $var wire 128 |& in[1][0] [127:0] $end
-      $var wire 128 "' in[1][1] [127:0] $end
-      $var wire 128 &' in[1][2] [127:0] $end
-      $var wire 8 *' out[0][0] [7:0] $end
-      $var wire 8 +' out[0][1] [7:0] $end
-      $var wire 8 ,' out[0][2] [7:0] $end
-      $var wire 8 -' out[1][0] [7:0] $end
-      $var wire 8 .' out[1][1] [7:0] $end
-      $var wire 8 /' out[1][2] [7:0] $end
-      $var wire 32 0' count [31:0] $end
-      $var wire 8 `& val0[0] [7:0] $end
-      $var wire 8 a& val0[1] [7:0] $end
-      $var wire 8 b& val1[0] [7:0] $end
-      $var wire 8 c& val1[1] [7:0] $end
-      $var wire 8 d& val2[0] [7:0] $end
-      $var wire 8 e& val2[1] [7:0] $end
-      $var wire 8 f& val3[0] [7:0] $end
-      $var wire 8 g& val3[1] [7:0] $end
+      $var wire 1 5' clk $end
+      $var wire 128 t& in[0][0] [127:0] $end
+      $var wire 128 x& in[0][1] [127:0] $end
+      $var wire 128 |& in[0][2] [127:0] $end
+      $var wire 128 "' in[1][0] [127:0] $end
+      $var wire 128 &' in[1][1] [127:0] $end
+      $var wire 128 *' in[1][2] [127:0] $end
+      $var wire 8 .' out[0][0] [7:0] $end
+      $var wire 8 /' out[0][1] [7:0] $end
+      $var wire 8 0' out[0][2] [7:0] $end
+      $var wire 8 1' out[1][0] [7:0] $end
+      $var wire 8 2' out[1][1] [7:0] $end
+      $var wire 8 3' out[1][2] [7:0] $end
+      $var wire 32 4' count [31:0] $end
+      $var wire 8 d& val0[0] [7:0] $end
+      $var wire 8 e& val0[1] [7:0] $end
+      $var wire 8 f& val1[0] [7:0] $end
+      $var wire 8 g& val1[1] [7:0] $end
+      $var wire 8 h& val2[0] [7:0] $end
+      $var wire 8 i& val2[1] [7:0] $end
+      $var wire 8 j& val3[0] [7:0] $end
+      $var wire 8 k& val3[1] [7:0] $end
       $scope module $libroot $end
-       $var wire 1 5' global_flag $end
+       $var wire 1 9' global_flag $end
       $upscope $end
       $scope module i_sub0 $end
-       $var wire 32 2' P0 [31:0] $end
-       $var wire 32 3' P1 [31:0] $end
-       $var wire 8 h& out[0] [7:0] $end
-       $var wire 8 i& out[1] [7:0] $end
-      $upscope $end
-      $scope module i_sub1 $end
-       $var wire 32 2' P0 [31:0] $end
-       $var wire 32 3' P1 [31:0] $end
-       $var wire 8 j& out[0] [7:0] $end
-       $var wire 8 k& out[1] [7:0] $end
-      $upscope $end
-      $scope module i_sub2 $end
-       $var wire 32 2' P0 [31:0] $end
-       $var wire 32 3' P1 [31:0] $end
+       $var wire 32 6' P0 [31:0] $end
+       $var wire 32 7' P1 [31:0] $end
        $var wire 8 l& out[0] [7:0] $end
        $var wire 8 m& out[1] [7:0] $end
       $upscope $end
-      $scope module i_sub3 $end
-       $var wire 32 2' P0 [31:0] $end
-       $var wire 32 4' P1 [31:0] $end
+      $scope module i_sub1 $end
+       $var wire 32 6' P0 [31:0] $end
+       $var wire 32 7' P1 [31:0] $end
        $var wire 8 n& out[0] [7:0] $end
        $var wire 8 o& out[1] [7:0] $end
       $upscope $end
+      $scope module i_sub2 $end
+       $var wire 32 6' P0 [31:0] $end
+       $var wire 32 7' P1 [31:0] $end
+       $var wire 8 p& out[0] [7:0] $end
+       $var wire 8 q& out[1] [7:0] $end
+      $upscope $end
+      $scope module i_sub3 $end
+       $var wire 32 6' P0 [31:0] $end
+       $var wire 32 8' P1 [31:0] $end
+       $var wire 8 r& out[0] [7:0] $end
+       $var wire 8 s& out[1] [7:0] $end
+      $upscope $end
      $upscope $end
     $upscope $end
     $scope module i_sub4_1 $end
-     $var wire 32 `! P0 [31:0] $end
-     $var real 64 a! P1 $end
-     $var real 64 e! P3 $end
-     $var wire 1 R! clk $end
-     $var wire 8 ` in [7:0] $end
+     $var wire 32 b! P0 [31:0] $end
+     $var real 64 c! P1 $end
+     $var real 64 g! P3 $end
+     $var wire 1 V! clk $end
+     $var wire 8 b in [7:0] $end
      $var wire 8 a out [7:0] $end
      $var wire 8 a ff [7:0] $end
-     $var wire 128 { sub5_in[0][0] [127:0] $end
-     $var wire 128 !! sub5_in[0][1] [127:0] $end
-     $var wire 128 %! sub5_in[0][2] [127:0] $end
-     $var wire 128 )! sub5_in[1][0] [127:0] $end
-     $var wire 128 -! sub5_in[1][1] [127:0] $end
-     $var wire 128 1! sub5_in[1][2] [127:0] $end
-     $var wire 8 L! sub5_out[0][0] [7:0] $end
-     $var wire 8 M! sub5_out[0][1] [7:0] $end
-     $var wire 8 N! sub5_out[0][2] [7:0] $end
-     $var wire 8 O! sub5_out[1][0] [7:0] $end
-     $var wire 8 P! sub5_out[1][1] [7:0] $end
-     $var wire 8 Q! sub5_out[1][2] [7:0] $end
-     $var wire 32 5! count [31:0] $end
+     $var wire 128 | sub5_in[0][0] [127:0] $end
+     $var wire 128 "! sub5_in[0][1] [127:0] $end
+     $var wire 128 &! sub5_in[0][2] [127:0] $end
+     $var wire 128 *! sub5_in[1][0] [127:0] $end
+     $var wire 128 .! sub5_in[1][1] [127:0] $end
+     $var wire 128 2! sub5_in[1][2] [127:0] $end
+     $var wire 8 P! sub5_out[0][0] [7:0] $end
+     $var wire 8 Q! sub5_out[0][1] [7:0] $end
+     $var wire 8 R! sub5_out[0][2] [7:0] $end
+     $var wire 8 S! sub5_out[1][0] [7:0] $end
+     $var wire 8 T! sub5_out[1][1] [7:0] $end
+     $var wire 8 U! sub5_out[1][2] [7:0] $end
+     $var wire 32 6! count [31:0] $end
      $var wire 32 % driven_from_bind [31:0] $end
      $scope module i_sub4_bound $end
-      $var real 64 a! P1 $end
+      $var real 64 c! P1 $end
       $var wire 32 % driven_from_bind [31:0] $end
      $upscope $end
      $scope module i_sub5 $end
-      $var wire 1 e' clk $end
-      $var wire 128 F' in[0][0] [127:0] $end
-      $var wire 128 J' in[0][1] [127:0] $end
-      $var wire 128 N' in[0][2] [127:0] $end
-      $var wire 128 R' in[1][0] [127:0] $end
-      $var wire 128 V' in[1][1] [127:0] $end
-      $var wire 128 Z' in[1][2] [127:0] $end
-      $var wire 8 ^' out[0][0] [7:0] $end
-      $var wire 8 _' out[0][1] [7:0] $end
-      $var wire 8 `' out[0][2] [7:0] $end
-      $var wire 8 a' out[1][0] [7:0] $end
-      $var wire 8 b' out[1][1] [7:0] $end
-      $var wire 8 c' out[1][2] [7:0] $end
-      $var wire 32 d' count [31:0] $end
-      $var wire 8 6' val0[0] [7:0] $end
-      $var wire 8 7' val0[1] [7:0] $end
-      $var wire 8 8' val1[0] [7:0] $end
-      $var wire 8 9' val1[1] [7:0] $end
-      $var wire 8 :' val2[0] [7:0] $end
-      $var wire 8 ;' val2[1] [7:0] $end
-      $var wire 8 <' val3[0] [7:0] $end
-      $var wire 8 =' val3[1] [7:0] $end
+      $var wire 1 i' clk $end
+      $var wire 128 J' in[0][0] [127:0] $end
+      $var wire 128 N' in[0][1] [127:0] $end
+      $var wire 128 R' in[0][2] [127:0] $end
+      $var wire 128 V' in[1][0] [127:0] $end
+      $var wire 128 Z' in[1][1] [127:0] $end
+      $var wire 128 ^' in[1][2] [127:0] $end
+      $var wire 8 b' out[0][0] [7:0] $end
+      $var wire 8 c' out[0][1] [7:0] $end
+      $var wire 8 d' out[0][2] [7:0] $end
+      $var wire 8 e' out[1][0] [7:0] $end
+      $var wire 8 f' out[1][1] [7:0] $end
+      $var wire 8 g' out[1][2] [7:0] $end
+      $var wire 32 h' count [31:0] $end
+      $var wire 8 :' val0[0] [7:0] $end
+      $var wire 8 ;' val0[1] [7:0] $end
+      $var wire 8 <' val1[0] [7:0] $end
+      $var wire 8 =' val1[1] [7:0] $end
+      $var wire 8 >' val2[0] [7:0] $end
+      $var wire 8 ?' val2[1] [7:0] $end
+      $var wire 8 @' val3[0] [7:0] $end
+      $var wire 8 A' val3[1] [7:0] $end
       $scope module $libroot $end
-       $var wire 1 i' global_flag $end
+       $var wire 1 m' global_flag $end
       $upscope $end
       $scope module i_sub0 $end
-       $var wire 32 f' P0 [31:0] $end
-       $var wire 32 g' P1 [31:0] $end
-       $var wire 8 >' out[0] [7:0] $end
-       $var wire 8 ?' out[1] [7:0] $end
-      $upscope $end
-      $scope module i_sub1 $end
-       $var wire 32 f' P0 [31:0] $end
-       $var wire 32 g' P1 [31:0] $end
-       $var wire 8 @' out[0] [7:0] $end
-       $var wire 8 A' out[1] [7:0] $end
-      $upscope $end
-      $scope module i_sub2 $end
-       $var wire 32 f' P0 [31:0] $end
-       $var wire 32 g' P1 [31:0] $end
+       $var wire 32 j' P0 [31:0] $end
+       $var wire 32 k' P1 [31:0] $end
        $var wire 8 B' out[0] [7:0] $end
        $var wire 8 C' out[1] [7:0] $end
       $upscope $end
-      $scope module i_sub3 $end
-       $var wire 32 f' P0 [31:0] $end
-       $var wire 32 h' P1 [31:0] $end
+      $scope module i_sub1 $end
+       $var wire 32 j' P0 [31:0] $end
+       $var wire 32 k' P1 [31:0] $end
        $var wire 8 D' out[0] [7:0] $end
        $var wire 8 E' out[1] [7:0] $end
       $upscope $end
+      $scope module i_sub2 $end
+       $var wire 32 j' P0 [31:0] $end
+       $var wire 32 k' P1 [31:0] $end
+       $var wire 8 F' out[0] [7:0] $end
+       $var wire 8 G' out[1] [7:0] $end
+      $upscope $end
+      $scope module i_sub3 $end
+       $var wire 32 j' P0 [31:0] $end
+       $var wire 32 l' P1 [31:0] $end
+       $var wire 8 H' out[0] [7:0] $end
+       $var wire 8 I' out[1] [7:0] $end
+      $upscope $end
      $upscope $end
     $upscope $end
    $upscope $end
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diff --git a/test_regress/t/t_trace_hier_fst.out b/test_regress/t/t_trace_hier_fst.out
index 7cb138d02..8a6a3a56a 100644
--- a/test_regress/t/t_trace_hier_fst.out
+++ b/test_regress/t/t_trace_hier_fst.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 14 09:16:58 2026
+Tue Apr 14 17:15:24 2026
 
 $end
 $version
diff --git a/test_regress/t/t_trace_huge_array.py b/test_regress/t/t_trace_huge_array.py
new file mode 100755
index 000000000..5fc9fecce
--- /dev/null
+++ b/test_regress/t/t_trace_huge_array.py
@@ -0,0 +1,23 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2024 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios("vlt_all")
+
+test.compile(v_flags2=[
+    "--trace-vcd --trace-max-width 0 --trace-max-array 0 --output-split-ctrace 10 --trace-structs"
+])
+trace_files = glob.glob(test.obj_dir + "/*Trace*.cpp")
+if len(trace_files) < 10:
+    test.error("Too few trace files")
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_trace_huge_array.v b/test_regress/t/t_trace_huge_array.v
new file mode 100644
index 000000000..aa71ff1d7
--- /dev/null
+++ b/test_regress/t/t_trace_huge_array.v
@@ -0,0 +1,29 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Wilson Snyder
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+   int cyc = 0;
+
+   localparam max = 1000;
+   logic [31:0] foo [max:0];
+   logic [max:0] [15:0] [31:0] bar;
+
+   always_ff @(posedge clk) begin
+      cyc <= cyc + 1;
+      foo[0] <= cyc;
+      for (int i = 1; i <= max; i++) foo[i] <= foo[i-1];
+      bar <= (bar << 32) | type(bar)'(cyc);
+      if (cyc == 10) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+endmodule
diff --git a/test_regress/t/t_trace_iface.out b/test_regress/t/t_trace_iface.out
index 3cf7ce8da..b99d88d1f 100644
--- a/test_regress/t/t_trace_iface.out
+++ b/test_regress/t/t_trace_iface.out
@@ -1,19 +1,19 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module top $end
-  $var wire 1 ( clk $end
+  $var wire 1 ' clk $end
   $scope module t $end
-   $var wire 1 ( clk $end
-   $var wire 32 # cyc [31:0] $end
+   $var wire 1 ' clk $end
+   $var wire 32 " cyc [31:0] $end
    $scope module c5_data $end
-    $var wire 1 $ valid $end
-    $var wire 4 % value [3:0] $end
-    $var wire 1 ) reset $end
+    $var wire 1 # valid $end
+    $var wire 4 $ value [3:0] $end
+    $var wire 1 ( reset $end
    $upscope $end
    $scope module c6_data $end
-    $var wire 1 & valid $end
-    $var wire 4 ' value [3:0] $end
-    $var wire 1 * reset $end
+    $var wire 1 % valid $end
+    $var wire 4 & value [3:0] $end
+    $var wire 1 ) reset $end
    $upscope $end
    $scope module cif2 $end
    $upscope $end
@@ -25,112 +25,112 @@ $enddefinitions $end
 
 
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diff --git a/test_regress/t/t_trace_interface_ref_cc_fst.out b/test_regress/t/t_trace_interface_ref_cc_fst.out
index 8fc37b7af..5472ae9ae 100644
--- a/test_regress/t/t_trace_interface_ref_cc_fst.out
+++ b/test_regress/t/t_trace_interface_ref_cc_fst.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 14 09:16:41 2026
+Tue Apr 14 15:20:43 2026
 
 $end
 $version
diff --git a/test_regress/t/t_trace_interface_ref_cc_saif.out b/test_regress/t/t_trace_interface_ref_cc_saif.out
index 085c0964a..c7dcd5f52 100644
--- a/test_regress/t/t_trace_interface_ref_cc_saif.out
+++ b/test_regress/t/t_trace_interface_ref_cc_saif.out
@@ -46,555 +46,11 @@
     (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
     (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
    )
-   (INSTANCE intf_1
-    (NET
-     (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41))
-     (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
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-       (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      )
-     )
-     (INSTANCE inner
+    (INSTANCE ac1
+     (INSTANCE intf_for_check
       (NET
+       (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41))
        (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
        (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10))
        (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5))
@@ -627,11 +83,11 @@
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        (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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-       (value\[4\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22))
+       (value\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11))
+       (value\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (value\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (value\[4\] (T0 150) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
        (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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        (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
@@ -660,146 +116,148 @@
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        (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
       )
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+        (val100\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val100\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val100\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val100\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val100\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val100\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val100\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val100\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val100\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val100\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val100\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val100\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val100\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val100\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val100\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val100\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val100\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val100\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val100\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val100\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val100\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val200\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22))
+        (val200\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11))
+        (val200\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (val200\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (val200\[4\] (T0 70) (T1 140) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (val200\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val200\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (val200\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val200\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val200\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val200\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val200\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val200\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val200\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+        (val200\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val200\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+        (val200\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+        (val200\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val200\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val200\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val200\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val200\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+      (INSTANCE inner
+       (NET
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+        (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10))
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+        (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+        (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+        (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+        (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[0\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+        (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+        (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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-      (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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-      (value\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
-      (value\[4\] (T0 140) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
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-      (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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-      (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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-      (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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-       (val200\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-       (val200\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-       (val200\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-       (val200\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-       (val200\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-       (val200\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-       (val200\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-       (val200\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-       (val200\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-       (val200\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-       (val200\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-       (val200\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-       (val200\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-       (val200\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-       (val200\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-       (val200\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-       (val200\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-       (val200\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-       (val200\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-       (val200\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-       (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      )
-     )
-     (INSTANCE inner
+    (INSTANCE ac2
+     (INSTANCE intf_for_check
       (NET
+       (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41))
        (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
        (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10))
        (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5))
@@ -832,11 +290,11 @@
        (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
        (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
        (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-       (value\[0\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-       (value\[1\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-       (value\[2\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-       (value\[3\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-       (value\[4\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+       (value\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11))
+       (value\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (value\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (value\[4\] (T0 140) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
        (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
        (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
        (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
@@ -865,6 +323,556 @@
        (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
        (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
       )
+      (INSTANCE the_struct
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+        (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
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+        (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
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+     )
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+        (val200\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+      (INSTANCE inner
+       (NET
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+        (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10))
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+        (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+        (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+        (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
      )
     )
     (INSTANCE intf_in_sub_all
@@ -1072,10 +1080,144 @@
       )
      )
     )
-    (INSTANCE ac1
-     (INSTANCE intf_for_check
+    (INSTANCE intf_one
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+      (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+     (INSTANCE the_struct
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+       (val200\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (val200\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (val200\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (val200\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (val200\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (val200\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (val200\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (val200\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (val200\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (val200\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (val200\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (val200\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (val200\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (val200\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (val200\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (val200\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (val200\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+     )
+     (INSTANCE inner
       (NET
-       (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41))
        (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
        (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10))
        (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5))
@@ -1108,11 +1250,11 @@
        (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
        (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
        (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-       (value\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22))
-       (value\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11))
-       (value\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5))
-       (value\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
-       (value\[4\] (T0 150) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (value\[0\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[1\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[2\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[3\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[4\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
        (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
        (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
        (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
@@ -1141,145 +1283,216 @@
        (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
        (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
       )
-      (INSTANCE the_struct
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-        (val100\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22))
-        (val100\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11))
-        (val100\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 6))
-        (val100\[3\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 3))
-        (val100\[4\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
-        (val100\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
-        (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
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-        (val100\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (val100\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (val100\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (val100\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (val100\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (val100\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (val100\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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-        (val100\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (val100\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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-        (val200\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5))
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-        (val200\[4\] (T0 70) (T1 140) (TZ 0) (TX 0) (TB 0) (TC 1))
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-        (val200\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
-        (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
-        (val200\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (val200\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (val200\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (val200\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (val200\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (val200\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (val200\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (val200\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (val200\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (val200\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (val200\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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-        (val200\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (val200\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (val200\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (val200\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (val200\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (val200\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (val200\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (val200\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (val200\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (val200\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (val200\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-       )
+     )
+    )
+    (INSTANCE intf_two
+     (NET
+      (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41))
+      (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+      (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10))
+      (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+      (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+      (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+      (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+      (value\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (value\[4\] (T0 140) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+      (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     )
+     (INSTANCE the_struct
+      (NET
+       (val100\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+       (val100\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11))
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+       (val200\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (val200\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (val200\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
       )
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-        (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-       )
+     )
+     (INSTANCE inner
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+       (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10))
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+       (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
       )
      )
     )
-    (INSTANCE ac2
+   )
+   (INSTANCE abcdefghijklmnopqrstuvwxyz
+    (INSTANCE ac1
      (INSTANCE intf_for_check
       (NET
        (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41))
@@ -1486,7 +1699,7 @@
       )
      )
     )
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+    (INSTANCE ac2
      (INSTANCE intf_for_check
       (NET
        (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41))
@@ -1525,8 +1738,215 @@
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        (value\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11))
        (value\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5))
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+       (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
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+        (val200\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val200\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val200\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val200\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val200\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val200\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val200\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val200\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val200\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val200\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val200\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val200\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val200\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+      (INSTANCE inner
+       (NET
+        (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+        (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[0\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[1\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[2\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[3\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[4\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+    )
+    (INSTANCE ac3
+     (INSTANCE intf_for_check
+      (NET
+       (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41))
+       (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+       (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+       (value\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11))
+       (value\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5))
        (value\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3))
-       (value\[4\] (T0 70) (T1 140) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (value\[4\] (T0 60) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
        (value\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
        (value\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
        (value\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
@@ -1557,12 +1977,12 @@
       )
       (INSTANCE the_struct
        (NET
-        (val100\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22))
-        (val100\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11))
-        (val100\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 6))
-        (val100\[3\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (val100\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+        (val100\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11))
+        (val100\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (val100\[3\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 4))
         (val100\[4\] (T0 50) (T1 160) (TZ 0) (TX 0) (TB 0) (TC 2))
-        (val100\[5\] (T0 190) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (val100\[5\] (T0 180) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
         (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
         (val100\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
         (val100\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
@@ -1589,13 +2009,13 @@
         (val100\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
         (val100\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
         (val100\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (val200\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22))
-        (val200\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11))
-        (val200\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (val200\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+        (val200\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11))
+        (val200\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5))
         (val200\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
-        (val200\[4\] (T0 60) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 2))
-        (val200\[5\] (T0 60) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 2))
-        (val200\[6\] (T0 150) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (val200\[4\] (T0 70) (T1 140) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (val200\[5\] (T0 70) (T1 140) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (val200\[6\] (T0 140) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
         (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
         (val200\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
         (val200\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
@@ -1729,11 +2149,11 @@
        (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
        (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
        (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-       (value\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22))
-       (value\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11))
-       (value\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (value\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+       (value\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11))
+       (value\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5))
        (value\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3))
-       (value\[4\] (T0 70) (T1 140) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (value\[4\] (T0 60) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
        (value\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
        (value\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
        (value\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
@@ -1764,12 +2184,12 @@
       )
       (INSTANCE the_struct
        (NET
-        (val100\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22))
-        (val100\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11))
-        (val100\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 6))
-        (val100\[3\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (val100\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+        (val100\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11))
+        (val100\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (val100\[3\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 4))
         (val100\[4\] (T0 50) (T1 160) (TZ 0) (TX 0) (TB 0) (TC 2))
-        (val100\[5\] (T0 190) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (val100\[5\] (T0 180) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
         (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
         (val100\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
         (val100\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
@@ -1796,13 +2216,13 @@
         (val100\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
         (val100\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
         (val100\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (val200\[0\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 22))
-        (val200\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11))
-        (val200\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (val200\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+        (val200\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11))
+        (val200\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5))
         (val200\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
-        (val200\[4\] (T0 60) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 2))
-        (val200\[5\] (T0 60) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 2))
-        (val200\[6\] (T0 150) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (val200\[4\] (T0 70) (T1 140) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (val200\[5\] (T0 70) (T1 140) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (val200\[6\] (T0 140) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
         (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
         (val200\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
         (val200\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
@@ -1900,8 +2320,211 @@
       )
      )
     )
-   )
-   (INSTANCE abcdefghijklmnopqrstuvwxyz
+    (INSTANCE intf_in_sub_all
+     (NET
+      (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41))
+      (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+      (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10))
+      (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+      (value\[9\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
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+      (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+      (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+      (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+      (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     )
+     (INSTANCE the_struct
+      (NET
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+       (val100\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11))
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+       (val100\[5\] (T0 180) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
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+       (val100\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (val200\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (val200\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (val200\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (val200\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+     )
+     (INSTANCE inner
+      (NET
+       (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+       (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[0\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[1\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[2\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[3\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[4\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+     )
+    )
     (INSTANCE intf_one
      (NET
       (clk (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 41))
@@ -2312,1039 +2935,6 @@
       )
      )
     )
-    (INSTANCE intf_in_sub_all
-     (NET
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-      (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10))
-      (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5))
-      (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
-      (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
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-      (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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-      (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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-      (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (value\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
-      (value\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11))
-      (value\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5))
-      (value\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3))
-      (value\[4\] (T0 60) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
-      (value\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
-      (value\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
-      (value\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
-      (value\[8\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
-      (value\[9\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
-      (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-      (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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-      (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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-        (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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-        (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-        (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-       )
-      )
-     )
-    )
    )
    (INSTANCE c1
     (INSTANCE intf_for_check
@@ -3760,6 +3350,416 @@
      )
     )
    )
+   (INSTANCE intf_1
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+     (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+     (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+     (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    )
+    (INSTANCE the_struct
+     (NET
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+      (val100\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 11))
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+      (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     )
+    )
+    (INSTANCE inner
+     (NET
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+      (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     )
+    )
+   )
+   (INSTANCE intf_2
+    (NET
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+     (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+     (value\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11))
+     (value\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (value\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (value\[4\] (T0 140) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    )
+    (INSTANCE the_struct
+     (NET
+      (val100\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+      (val100\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11))
+      (val100\[2\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 6))
+      (val100\[3\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 3))
+      (val100\[4\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (val100\[5\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (val100\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (val100\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val100\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val100\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val100\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val100\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val100\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val100\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val100\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val100\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val100\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val100\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val100\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val100\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val100\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val100\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val100\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val100\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val100\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val100\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val100\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val100\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val100\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val100\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val100\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val100\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val200\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+      (val200\[1\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 11))
+      (val200\[2\] (T0 100) (T1 110) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (val200\[3\] (T0 80) (T1 130) (TZ 0) (TX 0) (TB 0) (TC 3))
+      (val200\[4\] (T0 60) (T1 150) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (val200\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val200\[6\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (val200\[7\] (T0 0) (T1 210) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (val200\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val200\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val200\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val200\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val200\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val200\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val200\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val200\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val200\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val200\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val200\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val200\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val200\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val200\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val200\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val200\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val200\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val200\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val200\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val200\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val200\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val200\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val200\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (val200\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     )
+    )
+    (INSTANCE inner
+     (NET
+      (cyc\[0\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 21))
+      (cyc\[1\] (T0 110) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 10))
+      (cyc\[2\] (T0 120) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (cyc\[3\] (T0 130) (T1 80) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (cyc\[4\] (T0 160) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (cyc\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[0\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[1\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[2\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[3\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[4\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[5\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[6\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[7\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[8\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[9\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[10\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[11\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[12\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[13\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[14\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[15\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[16\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[17\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[18\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[19\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[20\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[21\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[22\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[23\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[24\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[25\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[26\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[27\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[28\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[29\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[30\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (value\[31\] (T0 210) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     )
+    )
+   )
    (INSTANCE s1
     (INSTANCE intf_for_struct
      (NET
diff --git a/test_regress/t/t_trace_interface_ref_cc_vcd.out b/test_regress/t/t_trace_interface_ref_cc_vcd.out
index 6cf55743f..1eb7639c2 100644
--- a/test_regress/t/t_trace_interface_ref_cc_vcd.out
+++ b/test_regress/t/t_trace_interface_ref_cc_vcd.out
@@ -1,296 +1,295 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
-
  $scope module top $end
-  $var wire 1 0 clk $end
+  $var wire 1 / clk $end
   $scope module t $end
-   $var wire 1 0 clk $end
-   $var wire 32 # cyc [31:0] $end
-   $scope module intf_1 $end
-    $var wire 1 0 clk $end
-    $var wire 32 # cyc [31:0] $end
-    $var wire 32 $ value [31:0] $end
-    $scope module the_struct $end
-     $var wire 32 % val100 [31:0] $end
-     $var wire 32 & val200 [31:0] $end
+   $var wire 1 / clk $end
+   $var wire 32 " cyc [31:0] $end
+   $scope module a $end
+    $scope module ac1 $end
+     $scope module intf_for_check $end
+      $var wire 1 / clk $end
+      $var wire 32 " cyc [31:0] $end
+      $var wire 32 # value [31:0] $end
+      $scope module the_struct $end
+       $var wire 32 $ val100 [31:0] $end
+       $var wire 32 % val200 [31:0] $end
+      $upscope $end
+      $scope module inner $end
+       $var wire 32 " cyc [31:0] $end
+       $var wire 32 0 value [31:0] $end
+      $upscope $end
+     $upscope $end
     $upscope $end
-    $scope module inner $end
-     $var wire 32 # cyc [31:0] $end
-     $var wire 32 1 value [31:0] $end
+    $scope module ac2 $end
+     $scope module intf_for_check $end
+      $var wire 1 / clk $end
+      $var wire 32 " cyc [31:0] $end
+      $var wire 32 & value [31:0] $end
+      $scope module the_struct $end
+       $var wire 32 ' val100 [31:0] $end
+       $var wire 32 ( val200 [31:0] $end
+      $upscope $end
+      $scope module inner $end
+       $var wire 32 " cyc [31:0] $end
+       $var wire 32 1 value [31:0] $end
+      $upscope $end
+     $upscope $end
+    $upscope $end
+    $scope module ac3 $end
+     $scope module intf_for_check $end
+      $var wire 1 / clk $end
+      $var wire 32 " cyc [31:0] $end
+      $var wire 32 ) value [31:0] $end
+      $scope module the_struct $end
+       $var wire 32 * val100 [31:0] $end
+       $var wire 32 + val200 [31:0] $end
+      $upscope $end
+      $scope module inner $end
+       $var wire 32 " cyc [31:0] $end
+       $var wire 32 2 value [31:0] $end
+      $upscope $end
+     $upscope $end
+    $upscope $end
+    $scope module as3 $end
+     $scope module intf_for_struct $end
+      $var wire 1 / clk $end
+      $var wire 32 " cyc [31:0] $end
+      $var wire 32 ) value [31:0] $end
+      $scope module the_struct $end
+       $var wire 32 * val100 [31:0] $end
+       $var wire 32 + val200 [31:0] $end
+      $upscope $end
+      $scope module inner $end
+       $var wire 32 " cyc [31:0] $end
+       $var wire 32 2 value [31:0] $end
+      $upscope $end
+     $upscope $end
+    $upscope $end
+    $scope module intf_in_sub_all $end
+     $var wire 1 / clk $end
+     $var wire 32 " cyc [31:0] $end
+     $var wire 32 ) value [31:0] $end
+     $scope module the_struct $end
+      $var wire 32 * val100 [31:0] $end
+      $var wire 32 + val200 [31:0] $end
+     $upscope $end
+     $scope module inner $end
+      $var wire 32 " cyc [31:0] $end
+      $var wire 32 2 value [31:0] $end
+     $upscope $end
+    $upscope $end
+    $scope module intf_one $end
+     $var wire 1 / clk $end
+     $var wire 32 " cyc [31:0] $end
+     $var wire 32 # value [31:0] $end
+     $scope module the_struct $end
+      $var wire 32 $ val100 [31:0] $end
+      $var wire 32 % val200 [31:0] $end
+     $upscope $end
+     $scope module inner $end
+      $var wire 32 " cyc [31:0] $end
+      $var wire 32 0 value [31:0] $end
+     $upscope $end
+    $upscope $end
+    $scope module intf_two $end
+     $var wire 1 / clk $end
+     $var wire 32 " cyc [31:0] $end
+     $var wire 32 & value [31:0] $end
+     $scope module the_struct $end
+      $var wire 32 ' val100 [31:0] $end
+      $var wire 32 ( val200 [31:0] $end
+     $upscope $end
+     $scope module inner $end
+      $var wire 32 " cyc [31:0] $end
+      $var wire 32 1 value [31:0] $end
+     $upscope $end
     $upscope $end
    $upscope $end
-   $scope module intf_2 $end
-    $var wire 1 0 clk $end
-    $var wire 32 # cyc [31:0] $end
-    $var wire 32 ' value [31:0] $end
-    $scope module the_struct $end
-     $var wire 32 ( val100 [31:0] $end
-     $var wire 32 ) val200 [31:0] $end
+   $scope module abcdefghijklmnopqrstuvwxyz $end
+    $scope module ac1 $end
+     $scope module intf_for_check $end
+      $var wire 1 / clk $end
+      $var wire 32 " cyc [31:0] $end
+      $var wire 32 & value [31:0] $end
+      $scope module the_struct $end
+       $var wire 32 ' val100 [31:0] $end
+       $var wire 32 ( val200 [31:0] $end
+      $upscope $end
+      $scope module inner $end
+       $var wire 32 " cyc [31:0] $end
+       $var wire 32 1 value [31:0] $end
+      $upscope $end
+     $upscope $end
     $upscope $end
-    $scope module inner $end
-     $var wire 32 # cyc [31:0] $end
-     $var wire 32 2 value [31:0] $end
+    $scope module ac2 $end
+     $scope module intf_for_check $end
+      $var wire 1 / clk $end
+      $var wire 32 " cyc [31:0] $end
+      $var wire 32 # value [31:0] $end
+      $scope module the_struct $end
+       $var wire 32 $ val100 [31:0] $end
+       $var wire 32 % val200 [31:0] $end
+      $upscope $end
+      $scope module inner $end
+       $var wire 32 " cyc [31:0] $end
+       $var wire 32 0 value [31:0] $end
+      $upscope $end
+     $upscope $end
+    $upscope $end
+    $scope module ac3 $end
+     $scope module intf_for_check $end
+      $var wire 1 / clk $end
+      $var wire 32 " cyc [31:0] $end
+      $var wire 32 , value [31:0] $end
+      $scope module the_struct $end
+       $var wire 32 - val100 [31:0] $end
+       $var wire 32 . val200 [31:0] $end
+      $upscope $end
+      $scope module inner $end
+       $var wire 32 " cyc [31:0] $end
+       $var wire 32 3 value [31:0] $end
+      $upscope $end
+     $upscope $end
+    $upscope $end
+    $scope module as3 $end
+     $scope module intf_for_struct $end
+      $var wire 1 / clk $end
+      $var wire 32 " cyc [31:0] $end
+      $var wire 32 , value [31:0] $end
+      $scope module the_struct $end
+       $var wire 32 - val100 [31:0] $end
+       $var wire 32 . val200 [31:0] $end
+      $upscope $end
+      $scope module inner $end
+       $var wire 32 " cyc [31:0] $end
+       $var wire 32 3 value [31:0] $end
+      $upscope $end
+     $upscope $end
+    $upscope $end
+    $scope module intf_in_sub_all $end
+     $var wire 1 / clk $end
+     $var wire 32 " cyc [31:0] $end
+     $var wire 32 , value [31:0] $end
+     $scope module the_struct $end
+      $var wire 32 - val100 [31:0] $end
+      $var wire 32 . val200 [31:0] $end
+     $upscope $end
+     $scope module inner $end
+      $var wire 32 " cyc [31:0] $end
+      $var wire 32 3 value [31:0] $end
+     $upscope $end
+    $upscope $end
+    $scope module intf_one $end
+     $var wire 1 / clk $end
+     $var wire 32 " cyc [31:0] $end
+     $var wire 32 & value [31:0] $end
+     $scope module the_struct $end
+      $var wire 32 ' val100 [31:0] $end
+      $var wire 32 ( val200 [31:0] $end
+     $upscope $end
+     $scope module inner $end
+      $var wire 32 " cyc [31:0] $end
+      $var wire 32 1 value [31:0] $end
+     $upscope $end
+    $upscope $end
+    $scope module intf_two $end
+     $var wire 1 / clk $end
+     $var wire 32 " cyc [31:0] $end
+     $var wire 32 # value [31:0] $end
+     $scope module the_struct $end
+      $var wire 32 $ val100 [31:0] $end
+      $var wire 32 % val200 [31:0] $end
+     $upscope $end
+     $scope module inner $end
+      $var wire 32 " cyc [31:0] $end
+      $var wire 32 0 value [31:0] $end
+     $upscope $end
     $upscope $end
    $upscope $end
    $scope module c1 $end
     $scope module intf_for_check $end
-     $var wire 1 0 clk $end
-     $var wire 32 # cyc [31:0] $end
-     $var wire 32 $ value [31:0] $end
+     $var wire 1 / clk $end
+     $var wire 32 " cyc [31:0] $end
+     $var wire 32 # value [31:0] $end
      $scope module the_struct $end
-      $var wire 32 % val100 [31:0] $end
-      $var wire 32 & val200 [31:0] $end
+      $var wire 32 $ val100 [31:0] $end
+      $var wire 32 % val200 [31:0] $end
      $upscope $end
      $scope module inner $end
-      $var wire 32 # cyc [31:0] $end
-      $var wire 32 1 value [31:0] $end
+      $var wire 32 " cyc [31:0] $end
+      $var wire 32 0 value [31:0] $end
      $upscope $end
     $upscope $end
    $upscope $end
    $scope module c2 $end
     $scope module intf_for_check $end
-     $var wire 1 0 clk $end
-     $var wire 32 # cyc [31:0] $end
-     $var wire 32 ' value [31:0] $end
+     $var wire 1 / clk $end
+     $var wire 32 " cyc [31:0] $end
+     $var wire 32 & value [31:0] $end
      $scope module the_struct $end
-      $var wire 32 ( val100 [31:0] $end
-      $var wire 32 ) val200 [31:0] $end
+      $var wire 32 ' val100 [31:0] $end
+      $var wire 32 ( val200 [31:0] $end
      $upscope $end
      $scope module inner $end
-      $var wire 32 # cyc [31:0] $end
-      $var wire 32 2 value [31:0] $end
-     $upscope $end
-    $upscope $end
-   $upscope $end
-   $scope module a $end
-    $scope module intf_one $end
-     $var wire 1 0 clk $end
-     $var wire 32 # cyc [31:0] $end
-     $var wire 32 $ value [31:0] $end
-     $scope module the_struct $end
-      $var wire 32 % val100 [31:0] $end
-      $var wire 32 & val200 [31:0] $end
-     $upscope $end
-     $scope module inner $end
-      $var wire 32 # cyc [31:0] $end
+      $var wire 32 " cyc [31:0] $end
       $var wire 32 1 value [31:0] $end
      $upscope $end
     $upscope $end
-    $scope module intf_two $end
-     $var wire 1 0 clk $end
-     $var wire 32 # cyc [31:0] $end
-     $var wire 32 ' value [31:0] $end
-     $scope module the_struct $end
-      $var wire 32 ( val100 [31:0] $end
-      $var wire 32 ) val200 [31:0] $end
-     $upscope $end
-     $scope module inner $end
-      $var wire 32 # cyc [31:0] $end
-      $var wire 32 2 value [31:0] $end
-     $upscope $end
+   $upscope $end
+   $scope module intf_1 $end
+    $var wire 1 / clk $end
+    $var wire 32 " cyc [31:0] $end
+    $var wire 32 # value [31:0] $end
+    $scope module the_struct $end
+     $var wire 32 $ val100 [31:0] $end
+     $var wire 32 % val200 [31:0] $end
     $upscope $end
-    $scope module intf_in_sub_all $end
-     $var wire 1 0 clk $end
-     $var wire 32 # cyc [31:0] $end
-     $var wire 32 * value [31:0] $end
-     $scope module the_struct $end
-      $var wire 32 + val100 [31:0] $end
-      $var wire 32 , val200 [31:0] $end
-     $upscope $end
-     $scope module inner $end
-      $var wire 32 # cyc [31:0] $end
-      $var wire 32 3 value [31:0] $end
-     $upscope $end
-    $upscope $end
-    $scope module ac1 $end
-     $scope module intf_for_check $end
-      $var wire 1 0 clk $end
-      $var wire 32 # cyc [31:0] $end
-      $var wire 32 $ value [31:0] $end
-      $scope module the_struct $end
-       $var wire 32 % val100 [31:0] $end
-       $var wire 32 & val200 [31:0] $end
-      $upscope $end
-      $scope module inner $end
-       $var wire 32 # cyc [31:0] $end
-       $var wire 32 1 value [31:0] $end
-      $upscope $end
-     $upscope $end
-    $upscope $end
-    $scope module ac2 $end
-     $scope module intf_for_check $end
-      $var wire 1 0 clk $end
-      $var wire 32 # cyc [31:0] $end
-      $var wire 32 ' value [31:0] $end
-      $scope module the_struct $end
-       $var wire 32 ( val100 [31:0] $end
-       $var wire 32 ) val200 [31:0] $end
-      $upscope $end
-      $scope module inner $end
-       $var wire 32 # cyc [31:0] $end
-       $var wire 32 2 value [31:0] $end
-      $upscope $end
-     $upscope $end
-    $upscope $end
-    $scope module ac3 $end
-     $scope module intf_for_check $end
-      $var wire 1 0 clk $end
-      $var wire 32 # cyc [31:0] $end
-      $var wire 32 * value [31:0] $end
-      $scope module the_struct $end
-       $var wire 32 + val100 [31:0] $end
-       $var wire 32 , val200 [31:0] $end
-      $upscope $end
-      $scope module inner $end
-       $var wire 32 # cyc [31:0] $end
-       $var wire 32 3 value [31:0] $end
-      $upscope $end
-     $upscope $end
-    $upscope $end
-    $scope module as3 $end
-     $scope module intf_for_struct $end
-      $var wire 1 0 clk $end
-      $var wire 32 # cyc [31:0] $end
-      $var wire 32 * value [31:0] $end
-      $scope module the_struct $end
-       $var wire 32 + val100 [31:0] $end
-       $var wire 32 , val200 [31:0] $end
-      $upscope $end
-      $scope module inner $end
-       $var wire 32 # cyc [31:0] $end
-       $var wire 32 3 value [31:0] $end
-      $upscope $end
-     $upscope $end
+    $scope module inner $end
+     $var wire 32 " cyc [31:0] $end
+     $var wire 32 0 value [31:0] $end
     $upscope $end
    $upscope $end
-   $scope module abcdefghijklmnopqrstuvwxyz $end
-    $scope module intf_one $end
-     $var wire 1 0 clk $end
-     $var wire 32 # cyc [31:0] $end
-     $var wire 32 ' value [31:0] $end
-     $scope module the_struct $end
-      $var wire 32 ( val100 [31:0] $end
-      $var wire 32 ) val200 [31:0] $end
-     $upscope $end
-     $scope module inner $end
-      $var wire 32 # cyc [31:0] $end
-      $var wire 32 2 value [31:0] $end
-     $upscope $end
+   $scope module intf_2 $end
+    $var wire 1 / clk $end
+    $var wire 32 " cyc [31:0] $end
+    $var wire 32 & value [31:0] $end
+    $scope module the_struct $end
+     $var wire 32 ' val100 [31:0] $end
+     $var wire 32 ( val200 [31:0] $end
     $upscope $end
-    $scope module intf_two $end
-     $var wire 1 0 clk $end
-     $var wire 32 # cyc [31:0] $end
-     $var wire 32 $ value [31:0] $end
-     $scope module the_struct $end
-      $var wire 32 % val100 [31:0] $end
-      $var wire 32 & val200 [31:0] $end
-     $upscope $end
-     $scope module inner $end
-      $var wire 32 # cyc [31:0] $end
-      $var wire 32 1 value [31:0] $end
-     $upscope $end
-    $upscope $end
-    $scope module intf_in_sub_all $end
-     $var wire 1 0 clk $end
-     $var wire 32 # cyc [31:0] $end
-     $var wire 32 - value [31:0] $end
-     $scope module the_struct $end
-      $var wire 32 . val100 [31:0] $end
-      $var wire 32 / val200 [31:0] $end
-     $upscope $end
-     $scope module inner $end
-      $var wire 32 # cyc [31:0] $end
-      $var wire 32 4 value [31:0] $end
-     $upscope $end
-    $upscope $end
-    $scope module ac1 $end
-     $scope module intf_for_check $end
-      $var wire 1 0 clk $end
-      $var wire 32 # cyc [31:0] $end
-      $var wire 32 ' value [31:0] $end
-      $scope module the_struct $end
-       $var wire 32 ( val100 [31:0] $end
-       $var wire 32 ) val200 [31:0] $end
-      $upscope $end
-      $scope module inner $end
-       $var wire 32 # cyc [31:0] $end
-       $var wire 32 2 value [31:0] $end
-      $upscope $end
-     $upscope $end
-    $upscope $end
-    $scope module ac2 $end
-     $scope module intf_for_check $end
-      $var wire 1 0 clk $end
-      $var wire 32 # cyc [31:0] $end
-      $var wire 32 $ value [31:0] $end
-      $scope module the_struct $end
-       $var wire 32 % val100 [31:0] $end
-       $var wire 32 & val200 [31:0] $end
-      $upscope $end
-      $scope module inner $end
-       $var wire 32 # cyc [31:0] $end
-       $var wire 32 1 value [31:0] $end
-      $upscope $end
-     $upscope $end
-    $upscope $end
-    $scope module ac3 $end
-     $scope module intf_for_check $end
-      $var wire 1 0 clk $end
-      $var wire 32 # cyc [31:0] $end
-      $var wire 32 - value [31:0] $end
-      $scope module the_struct $end
-       $var wire 32 . val100 [31:0] $end
-       $var wire 32 / val200 [31:0] $end
-      $upscope $end
-      $scope module inner $end
-       $var wire 32 # cyc [31:0] $end
-       $var wire 32 4 value [31:0] $end
-      $upscope $end
-     $upscope $end
-    $upscope $end
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-     $scope module intf_for_struct $end
-      $var wire 1 0 clk $end
-      $var wire 32 # cyc [31:0] $end
-      $var wire 32 - value [31:0] $end
-      $scope module the_struct $end
-       $var wire 32 . val100 [31:0] $end
-       $var wire 32 / val200 [31:0] $end
-      $upscope $end
-      $scope module inner $end
-       $var wire 32 # cyc [31:0] $end
-       $var wire 32 4 value [31:0] $end
-      $upscope $end
-     $upscope $end
+    $scope module inner $end
+     $var wire 32 " cyc [31:0] $end
+     $var wire 32 1 value [31:0] $end
     $upscope $end
    $upscope $end
    $scope module s1 $end
     $scope module intf_for_struct $end
-     $var wire 1 0 clk $end
-     $var wire 32 # cyc [31:0] $end
-     $var wire 32 $ value [31:0] $end
+     $var wire 1 / clk $end
+     $var wire 32 " cyc [31:0] $end
+     $var wire 32 # value [31:0] $end
      $scope module the_struct $end
-      $var wire 32 % val100 [31:0] $end
-      $var wire 32 & val200 [31:0] $end
+      $var wire 32 $ val100 [31:0] $end
+      $var wire 32 % val200 [31:0] $end
      $upscope $end
      $scope module inner $end
-      $var wire 32 # cyc [31:0] $end
-      $var wire 32 1 value [31:0] $end
+      $var wire 32 " cyc [31:0] $end
+      $var wire 32 0 value [31:0] $end
      $upscope $end
     $upscope $end
    $upscope $end
    $scope module s2 $end
     $scope module intf_for_struct $end
-     $var wire 1 0 clk $end
-     $var wire 32 # cyc [31:0] $end
-     $var wire 32 ' value [31:0] $end
+     $var wire 1 / clk $end
+     $var wire 32 " cyc [31:0] $end
+     $var wire 32 & value [31:0] $end
      $scope module the_struct $end
-      $var wire 32 ( val100 [31:0] $end
-      $var wire 32 ) val200 [31:0] $end
+      $var wire 32 ' val100 [31:0] $end
+      $var wire 32 ( val200 [31:0] $end
      $upscope $end
      $scope module inner $end
-      $var wire 32 # cyc [31:0] $end
-      $var wire 32 2 value [31:0] $end
+      $var wire 32 " cyc [31:0] $end
+      $var wire 32 1 value [31:0] $end
      $upscope $end
     $upscope $end
    $upscope $end
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-b00000000000000000000010010111010 /
-10
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 b00000000000000000000000000001001 #
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 b00000000000000000000000000001011 #
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-b00000000000000000000001111110100 *
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 b00000000000000000000000000001100 #
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-b00000000000000000000001111110101 *
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 b00000000000000000000000000001101 #
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-b00000000000000000000001111110110 *
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 b00000000000000000000000000001110 #
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-b00000000000000000000000011011000 )
-b00000000000000000000001111110111 *
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-00
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 b00000000000000000000000000001111 #
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 b00000000000000000000000000010000 #
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-b00000000000000000000000011011001 &
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-b00000000000000000000000011011010 )
-b00000000000000000000001111111001 *
-b00000000000000000000010001011101 +
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-b00000000000000000000001111111010 -
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-b00000000000000000000010011000010 /
-10
-#165
-00
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+0/
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 b00000000000000000000000000010001 #
-b00000000000000000000000000010010 $
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-b00000000000000000000000011011011 )
-b00000000000000000000001111111010 *
-b00000000000000000000010001011110 +
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-b00000000000000000000001111111011 -
-b00000000000000000000010001011111 .
-b00000000000000000000010011000011 /
-10
-#175
-00
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 b00000000000000000000000000010010 #
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-b00000000000000000000000011011100 )
-b00000000000000000000001111111011 *
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-10
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-00
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 b00000000000000000000000000010011 #
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-b00000000000000000000001111111100 *
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-b00000000000000000000010011000101 /
-10
-#195
-00
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 b00000000000000000000000000010100 #
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-b00000000000000000000000011011110 )
-b00000000000000000000001111111101 *
-b00000000000000000000010001100001 +
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-b00000000000000000000001111111110 -
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 b00000000000000000000000000010101 #
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-b00000000000000000000000011011111 )
-b00000000000000000000001111111110 *
-b00000000000000000000010001100010 +
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-10
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+b00000000000000000000010001100010 *
+b00000000000000000000010011000110 +
+b00000000000000000000001111111111 ,
+b00000000000000000000010001100011 -
+b00000000000000000000010011000111 .
+1/
diff --git a/test_regress/t/t_trace_interface_ref_sc_fst.out b/test_regress/t/t_trace_interface_ref_sc_fst.out
index 9cb871617..d37f43695 100644
--- a/test_regress/t/t_trace_interface_ref_sc_fst.out
+++ b/test_regress/t/t_trace_interface_ref_sc_fst.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 14 09:17:10 2026
+Tue Apr 14 15:20:43 2026
 
 $end
 $version
diff --git a/test_regress/t/t_trace_lib_default_fst.out b/test_regress/t/t_trace_lib_default_fst.out
index c8d98349d..4de5c06f5 100644
--- a/test_regress/t/t_trace_lib_default_fst.out
+++ b/test_regress/t/t_trace_lib_default_fst.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 21 21:35:43 2026
+Tue Apr 14 15:20:29 2026
 
 $end
 $version
diff --git a/test_regress/t/t_trace_lib_notop_fst.out b/test_regress/t/t_trace_lib_notop_fst.out
index 2ea266a51..feaf4ef3d 100644
--- a/test_regress/t/t_trace_lib_notop_fst.out
+++ b/test_regress/t/t_trace_lib_notop_fst.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 21 21:35:35 2026
+Tue Apr 14 15:20:30 2026
 
 $end
 $version
diff --git a/test_regress/t/t_trace_max.out b/test_regress/t/t_trace_max.out
index e4489ebff..ab8b78888 100644
--- a/test_regress/t/t_trace_max.out
+++ b/test_regress/t/t_trace_max.out
@@ -1,43 +1,43 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module top $end
-  $var wire 1 # clk $end
+  $var wire 1 " clk $end
   $scope module t $end
-   $var wire 1 # clk $end
-   $var wire 32 $ cyc [31:0] $end
+   $var wire 1 " clk $end
+   $var wire 32 # cyc [31:0] $end
   $upscope $end
  $upscope $end
 $enddefinitions $end
 
 
 #0
-0#
-b00000000000000000000000000000000 $
+0"
+b00000000000000000000000000000000 #
 #10
-1#
-b00000000000000000000000000000001 $
+1"
+b00000000000000000000000000000001 #
 #15
-0#
+0"
 #20
-1#
-b00000000000000000000000000000010 $
+1"
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 #25
-0#
+0"
 #30
-1#
-b00000000000000000000000000000011 $
+1"
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 #35
-0#
+0"
 #40
-1#
-b00000000000000000000000000000100 $
+1"
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 #45
-0#
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 #50
-1#
-b00000000000000000000000000000101 $
+1"
+b00000000000000000000000000000101 #
 #55
-0#
+0"
 #60
-1#
-b00000000000000000000000000000110 $
+1"
+b00000000000000000000000000000110 #
diff --git a/test_regress/t/t_trace_max_default.out b/test_regress/t/t_trace_max_default.out
index 3b8af555e..515745921 100644
--- a/test_regress/t/t_trace_max_default.out
+++ b/test_regress/t/t_trace_max_default.out
@@ -1,59 +1,60 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module top $end
-  $var wire 1 O clk $end
+  $var wire 1 N clk $end
   $scope module t $end
-   $var wire 1 O clk $end
-   $var wire 32 # cyc [31:0] $end
-   $var wire 96 $ wide1 [95:0] $end
-   $var wire 16 ' wide2[0] [15:0] $end
-   $var wire 16 ( wide2[1] [15:0] $end
-   $var wire 16 ) wide2[2] [15:0] $end
-   $var wire 16 * wide2[3] [15:0] $end
-   $var wire 16 + wide2[4] [15:0] $end
-   $var wire 16 , wide2[5] [15:0] $end
-   $var wire 16 - wide2[6] [15:0] $end
-   $var wire 16 . wide2[7] [15:0] $end
-   $var wire 16 / wide2[8] [15:0] $end
-   $var wire 16 0 wide2[9] [15:0] $end
-   $var wire 16 1 wide2[10] [15:0] $end
-   $var wire 16 2 wide2[11] [15:0] $end
-   $var wire 16 3 wide2[12] [15:0] $end
-   $var wire 16 4 wide2[13] [15:0] $end
-   $var wire 16 5 wide2[14] [15:0] $end
-   $var wire 16 6 wide2[15] [15:0] $end
-   $var wire 1 7 deep1[0] $end
-   $var wire 1 8 deep1[1] $end
-   $var wire 1 9 deep1[2] $end
-   $var wire 1 : deep1[3] $end
-   $var wire 1 ; deep1[4] $end
-   $var wire 1 < deep1[5] $end
-   $var wire 1 = deep1[6] $end
-   $var wire 1 > deep1[7] $end
-   $var wire 1 ? deep1[8] $end
-   $var wire 1 @ deep1[9] $end
-   $var wire 1 A deep1[10] $end
-   $var wire 1 B deep1[11] $end
-   $var wire 1 C deep1[12] $end
-   $var wire 1 D deep1[13] $end
-   $var wire 1 E deep1[14] $end
-   $var wire 1 F deep1[15] $end
-   $var wire 1 G deep1[16] $end
-   $var wire 1 H deep1[17] $end
-   $var wire 1 I deep1[18] $end
-   $var wire 1 J deep1[19] $end
-   $var wire 1 K deep1[20] $end
-   $var wire 1 L deep1[21] $end
-   $var wire 1 M deep1[22] $end
-   $var wire 1 N deep1[23] $end
+   $var wire 1 N clk $end
+   $var wire 32 " cyc [31:0] $end
+   $var wire 96 # wide1 [95:0] $end
+   $var wire 16 & wide2[0] [15:0] $end
+   $var wire 16 ' wide2[1] [15:0] $end
+   $var wire 16 ( wide2[2] [15:0] $end
+   $var wire 16 ) wide2[3] [15:0] $end
+   $var wire 16 * wide2[4] [15:0] $end
+   $var wire 16 + wide2[5] [15:0] $end
+   $var wire 16 , wide2[6] [15:0] $end
+   $var wire 16 - wide2[7] [15:0] $end
+   $var wire 16 . wide2[8] [15:0] $end
+   $var wire 16 / wide2[9] [15:0] $end
+   $var wire 16 0 wide2[10] [15:0] $end
+   $var wire 16 1 wide2[11] [15:0] $end
+   $var wire 16 2 wide2[12] [15:0] $end
+   $var wire 16 3 wide2[13] [15:0] $end
+   $var wire 16 4 wide2[14] [15:0] $end
+   $var wire 16 5 wide2[15] [15:0] $end
+   $var wire 1 6 deep1[0] $end
+   $var wire 1 7 deep1[1] $end
+   $var wire 1 8 deep1[2] $end
+   $var wire 1 9 deep1[3] $end
+   $var wire 1 : deep1[4] $end
+   $var wire 1 ; deep1[5] $end
+   $var wire 1 < deep1[6] $end
+   $var wire 1 = deep1[7] $end
+   $var wire 1 > deep1[8] $end
+   $var wire 1 ? deep1[9] $end
+   $var wire 1 @ deep1[10] $end
+   $var wire 1 A deep1[11] $end
+   $var wire 1 B deep1[12] $end
+   $var wire 1 C deep1[13] $end
+   $var wire 1 D deep1[14] $end
+   $var wire 1 E deep1[15] $end
+   $var wire 1 F deep1[16] $end
+   $var wire 1 G deep1[17] $end
+   $var wire 1 H deep1[18] $end
+   $var wire 1 I deep1[19] $end
+   $var wire 1 J deep1[20] $end
+   $var wire 1 K deep1[21] $end
+   $var wire 1 L deep1[22] $end
+   $var wire 1 M deep1[23] $end
   $upscope $end
  $upscope $end
 $enddefinitions $end
 
 
 #0
-b00000000000000000000000000000000 #
-b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 $
+b00000000000000000000000000000000 "
+b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 #
+b0000000000000000 &
 b0000000000000000 '
 b0000000000000000 (
 b0000000000000000 )
@@ -69,7 +70,7 @@ b0000000000000000 2
 b0000000000000000 3
 b0000000000000000 4
 b0000000000000000 5
-b0000000000000000 6
+06
 07
 08
 09
@@ -94,47 +95,46 @@ b0000000000000000 6
 0L
 0M
 0N
-0O
 #10
-b00000000000000000000000000000001 #
-1O
+b00000000000000000000000000000001 "
+1N
 #15
-0O
+0N
 #20
-b00000000000000000000000000000010 #
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-b0000000000000001 )
-1:
-1O
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+b0000000000000001 (
+19
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 #25
-0O
+0N
 #30
-b00000000000000000000000000000011 #
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-b0000000000000010 )
-0:
-1O
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+b0000000000000010 (
+09
+1N
 #35
-0O
+0N
 #40
-b00000000000000000000000000000100 #
-b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 $
-b0000000000000011 )
-1:
-1O
+b00000000000000000000000000000100 "
+b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 #
+b0000000000000011 (
+19
+1N
 #45
-0O
+0N
 #50
-b00000000000000000000000000000101 #
-b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 $
-b0000000000000100 )
-0:
-1O
+b00000000000000000000000000000101 "
+b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 #
+b0000000000000100 (
+09
+1N
 #55
-0O
+0N
 #60
-b00000000000000000000000000000110 #
-b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 $
-b0000000000000101 )
-1:
-1O
+b00000000000000000000000000000110 "
+b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 #
+b0000000000000101 (
+19
+1N
diff --git a/test_regress/t/t_trace_no_top_name2_fst.out b/test_regress/t/t_trace_no_top_name2_fst.out
index 53f5852cc..ff438bce1 100644
--- a/test_regress/t/t_trace_no_top_name2_fst.out
+++ b/test_regress/t/t_trace_no_top_name2_fst.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 14 09:17:09 2026
+Tue Apr 14 15:20:43 2026
 
 $end
 $version
diff --git a/test_regress/t/t_trace_no_top_name2_vcd.out b/test_regress/t/t_trace_no_top_name2_vcd.out
index 7835046a5..8358e5c2b 100644
--- a/test_regress/t/t_trace_no_top_name2_vcd.out
+++ b/test_regress/t/t_trace_no_top_name2_vcd.out
@@ -1,73 +1,73 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module $rootio $end
-  $var wire 1 # clk $end
+  $var wire 1 " clk $end
  $upscope $end
  $scope module foo_pkg $end
-  $var wire 32 & foo_func__Vstatic__b_current [31:0] $end
+  $var wire 32 % foo_func__Vstatic__b_current [31:0] $end
  $upscope $end
  $scope module t $end
-  $var wire 1 # clk $end
-  $var wire 32 $ cyc [31:0] $end
+  $var wire 1 " clk $end
+  $var wire 32 # cyc [31:0] $end
   $scope module sub $end
-   $var wire 32 % a [31:0] $end
+   $var wire 32 $ a [31:0] $end
   $upscope $end
  $upscope $end
 $enddefinitions $end
 
 
 #0
-0#
-b00000000000000000000000000000000 $
-b00000000000000000000010010111100 %
-b00000000000000000000000000000000 &
+0"
+b00000000000000000000000000000000 #
+b00000000000000000000010010111100 $
+b00000000000000000000000000000000 %
 #1
-1#
-b00000000000000000000000000000001 $
+1"
+b00000000000000000000000000000001 #
 #2
-0#
+0"
 #3
-1#
-b00000000000000000000000000000010 $
+1"
+b00000000000000000000000000000010 #
 #4
-0#
+0"
 #5
-1#
-b00000000000000000000000000000011 $
+1"
+b00000000000000000000000000000011 #
 #6
-0#
+0"
 #7
-1#
-b00000000000000000000000000000100 $
+1"
+b00000000000000000000000000000100 #
 #8
-0#
+0"
 #9
-1#
-b00000000000000000000000000000101 $
+1"
+b00000000000000000000000000000101 #
 #10
-0#
+0"
 #11
-1#
-b00000000000000000000000000000110 $
+1"
+b00000000000000000000000000000110 #
 #12
-0#
+0"
 #13
-1#
-b00000000000000000000000000000111 $
+1"
+b00000000000000000000000000000111 #
 #14
-0#
+0"
 #15
-1#
-b00000000000000000000000000001000 $
+1"
+b00000000000000000000000000001000 #
 #16
-0#
+0"
 #17
-1#
-b00000000000000000000000000001001 $
+1"
+b00000000000000000000000000001001 #
 #18
-0#
+0"
 #19
-1#
-b00000000000000000000000000001010 $
+1"
+b00000000000000000000000000001010 #
 #20
-0#
+0"
diff --git a/test_regress/t/t_trace_no_top_name_fst.out b/test_regress/t/t_trace_no_top_name_fst.out
index 73e77e84c..d1e05ec93 100644
--- a/test_regress/t/t_trace_no_top_name_fst.out
+++ b/test_regress/t/t_trace_no_top_name_fst.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 14 09:17:18 2026
+Tue Apr 14 15:20:43 2026
 
 $end
 $version
diff --git a/test_regress/t/t_trace_no_top_name_vcd.out b/test_regress/t/t_trace_no_top_name_vcd.out
index 2905133f4..f2c4b21b6 100644
--- a/test_regress/t/t_trace_no_top_name_vcd.out
+++ b/test_regress/t/t_trace_no_top_name_vcd.out
@@ -1,13 +1,13 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module another_top $end
-  $var wire 1 # b $end
+  $var wire 1 " b $end
  $upscope $end
  $scope module t $end
-  $var wire 1 # a $end
+  $var wire 1 " a $end
  $upscope $end
 $enddefinitions $end
 
 
 #0
-0#
+0"
diff --git a/test_regress/t/t_trace_packed_struct_cc_fst.out b/test_regress/t/t_trace_packed_struct_cc_fst.out
index 3a7e329b9..793a5cac0 100644
--- a/test_regress/t/t_trace_packed_struct_cc_fst.out
+++ b/test_regress/t/t_trace_packed_struct_cc_fst.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 14 09:17:23 2026
+Tue Apr 14 15:20:44 2026
 
 $end
 $version
diff --git a/test_regress/t/t_trace_packed_struct_cc_saif.out b/test_regress/t/t_trace_packed_struct_cc_saif.out
index 1edfc23c1..d99998cf6 100644
--- a/test_regress/t/t_trace_packed_struct_cc_saif.out
+++ b/test_regress/t/t_trace_packed_struct_cc_saif.out
@@ -45,198 +45,6 @@
     (cnt\[29\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
     (cnt\[30\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
     (cnt\[31\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-    (v[0]\[0\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-    (v[0]\[1\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-    (v[0]\[2\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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-    (v[0]\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-    (v[0]\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-    (v[0]\[8\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-    (v[0]\[9\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-    (v[0]\[10\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-    (v[0]\[11\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-    (v[0]\[12\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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-    (v[0]\[15\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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-    (v[1]\[86\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-    (v[1]\[87\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-    (v[1]\[88\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-    (v[1]\[89\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-    (v[1]\[90\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-    (v[1]\[91\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-    (v[1]\[92\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-    (v[1]\[93\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
-    (v[1]\[94\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
-    (v[1]\[95\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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     (v[2]\[2\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
@@ -333,6 +141,198 @@
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    )
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  )
diff --git a/test_regress/t/t_trace_packed_struct_sc_fst.out b/test_regress/t/t_trace_packed_struct_sc_fst.out
index c4c60fd49..4d2a4955b 100644
--- a/test_regress/t/t_trace_packed_struct_sc_fst.out
+++ b/test_regress/t/t_trace_packed_struct_sc_fst.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 14 09:17:13 2026
+Tue Apr 14 15:20:44 2026
 
 $end
 $version
diff --git a/test_regress/t/t_trace_param_fst.out b/test_regress/t/t_trace_param_fst.out
index 43f896715..f05534b05 100644
--- a/test_regress/t/t_trace_param_fst.out
+++ b/test_regress/t/t_trace_param_fst.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 14 09:16:46 2026
+Tue Apr 14 15:20:43 2026
 
 $end
 $version
diff --git a/test_regress/t/t_trace_param_override.out b/test_regress/t/t_trace_param_override.out
index e896822d2..895e18ef2 100644
--- a/test_regress/t/t_trace_param_override.out
+++ b/test_regress/t/t_trace_param_override.out
@@ -1,12 +1,12 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module t $end
-  $var wire 32 # POVERRODE [31:0] $end
-  $var wire 32 $ PORIG [31:0] $end
+  $var wire 32 " POVERRODE [31:0] $end
+  $var wire 32 # PORIG [31:0] $end
  $upscope $end
 $enddefinitions $end
 
 
 #0
-b00000000000000000000000000011111 #
-b00000000000000000000000000010000 $
+b00000000000000000000000000011111 "
+b00000000000000000000000000010000 #
diff --git a/test_regress/t/t_trace_primitive_cc_fst.out b/test_regress/t/t_trace_primitive_cc_fst.out
index d974fc260..13962204a 100644
--- a/test_regress/t/t_trace_primitive_cc_fst.out
+++ b/test_regress/t/t_trace_primitive_cc_fst.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 14 09:17:00 2026
+Tue Apr 14 15:20:44 2026
 
 $end
 $version
diff --git a/test_regress/t/t_trace_primitive_sc_fst.out b/test_regress/t/t_trace_primitive_sc_fst.out
index 6467b59ec..4d40302ca 100644
--- a/test_regress/t/t_trace_primitive_sc_fst.out
+++ b/test_regress/t/t_trace_primitive_sc_fst.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 14 09:17:00 2026
+Tue Apr 14 15:20:44 2026
 
 $end
 $version
diff --git a/test_regress/t/t_trace_public.out b/test_regress/t/t_trace_public.out
index 875fb6e14..c639ac2bd 100644
--- a/test_regress/t/t_trace_public.out
+++ b/test_regress/t/t_trace_public.out
@@ -6,8 +6,8 @@ $timescale 1ps $end
   $scope module t $end
    $var wire 1 4 CLK $end
    $var wire 1 " RESET $end
-   $var wire 2 # vec[3] [2:1] $end
-   $var wire 2 $ vec[4] [2:1] $end
+   $var wire 2 # vec[4] [2:1] $end
+   $var wire 2 $ vec[3] [2:1] $end
    $var wire 32 % val [31:0] $end
    $scope module glbl $end
     $var wire 1 6 GSR $end
diff --git a/test_regress/t/t_trace_scope_no_inline.out b/test_regress/t/t_trace_scope_no_inline.out
index e9ddddcb6..cb1a51a2e 100644
--- a/test_regress/t/t_trace_scope_no_inline.out
+++ b/test_regress/t/t_trace_scope_no_inline.out
@@ -5,19 +5,19 @@ $timescale 1ps $end
    $scope module mid_a $end
    $upscope $end
    $scope module mid_b $end
-    $var wire 1 ' clk $end
-    $var wire 32 # cnt [31:0] $end
+    $var wire 1 & clk $end
+    $var wire 32 " cnt [31:0] $end
     $scope module sub_a $end
-     $var wire 1 ' clk $end
-     $var wire 32 $ cnt [31:0] $end
+     $var wire 1 & clk $end
+     $var wire 32 # cnt [31:0] $end
     $upscope $end
     $scope module sub_b $end
-     $var wire 1 ' clk $end
-     $var wire 32 % cnt [31:0] $end
+     $var wire 1 & clk $end
+     $var wire 32 $ cnt [31:0] $end
     $upscope $end
     $scope module sub_c $end
-     $var wire 1 ' clk $end
-     $var wire 32 & cnt [31:0] $end
+     $var wire 1 & clk $end
+     $var wire 32 % cnt [31:0] $end
     $upscope $end
    $upscope $end
    $scope module mid_c $end
@@ -28,54 +28,54 @@ $enddefinitions $end
 
 
 #0
+b00000000000000000000000000000000 "
 b00000000000000000000000000000000 #
 b00000000000000000000000000000000 $
 b00000000000000000000000000000000 %
-b00000000000000000000000000000000 &
-0'
+0&
 #10
-b00000000000000000000000000000001 #
+b00000000000000000000000000000001 "
+b00000000000000000000000000000010 #
 b00000000000000000000000000000010 $
 b00000000000000000000000000000010 %
-b00000000000000000000000000000010 &
-1'
+1&
 #15
-0'
+0&
 #20
-b00000000000000000000000000000010 #
+b00000000000000000000000000000010 "
+b00000000000000000000000000000100 #
 b00000000000000000000000000000100 $
 b00000000000000000000000000000100 %
-b00000000000000000000000000000100 &
-1'
+1&
 #25
-0'
+0&
 #30
-b00000000000000000000000000000011 #
+b00000000000000000000000000000011 "
+b00000000000000000000000000000110 #
 b00000000000000000000000000000110 $
 b00000000000000000000000000000110 %
-b00000000000000000000000000000110 &
-1'
+1&
 #35
-0'
+0&
 #40
-b00000000000000000000000000000100 #
+b00000000000000000000000000000100 "
+b00000000000000000000000000001000 #
 b00000000000000000000000000001000 $
 b00000000000000000000000000001000 %
-b00000000000000000000000000001000 &
-1'
+1&
 #45
-0'
+0&
 #50
-b00000000000000000000000000000101 #
+b00000000000000000000000000000101 "
+b00000000000000000000000000001010 #
 b00000000000000000000000000001010 $
 b00000000000000000000000000001010 %
-b00000000000000000000000000001010 &
-1'
+1&
 #55
-0'
+0&
 #60
-b00000000000000000000000000000110 #
+b00000000000000000000000000000110 "
+b00000000000000000000000000001100 #
 b00000000000000000000000000001100 $
 b00000000000000000000000000001100 %
-b00000000000000000000000000001100 &
-1'
+1&
diff --git a/test_regress/t/t_trace_scope_vlt.out b/test_regress/t/t_trace_scope_vlt.out
index 72e07b491..cdc8260bc 100644
--- a/test_regress/t/t_trace_scope_vlt.out
+++ b/test_regress/t/t_trace_scope_vlt.out
@@ -1,32 +1,31 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
-
  $scope module top $end
-  $var wire 1 ) clk $end
+  $var wire 1 ( clk $end
   $scope module t $end
-   $var wire 1 ) clk $end
+   $var wire 1 ( clk $end
    $scope module sub1a $end
-    $var wire 32 * ADD [31:0] $end
-    $var wire 32 # cyc [31:0] $end
-    $var wire 32 $ value [31:0] $end
+    $var wire 32 ) ADD [31:0] $end
+    $var wire 32 " cyc [31:0] $end
+    $var wire 32 # value [31:0] $end
    $upscope $end
    $scope module sub1b $end
-    $var wire 32 + ADD [31:0] $end
-    $var wire 32 # cyc [31:0] $end
-    $var wire 32 % value [31:0] $end
+    $var wire 32 * ADD [31:0] $end
+    $var wire 32 " cyc [31:0] $end
+    $var wire 32 $ value [31:0] $end
     $scope module sub2a $end
-     $var wire 32 # cyc [31:0] $end
-     $var wire 32 & value [31:0] $end
+     $var wire 32 " cyc [31:0] $end
+     $var wire 32 % value [31:0] $end
     $upscope $end
     $scope module sub2b $end
-     $var wire 32 , ADD [31:0] $end
-     $var wire 32 # cyc [31:0] $end
-     $var wire 32 ' value [31:0] $end
+     $var wire 32 + ADD [31:0] $end
+     $var wire 32 " cyc [31:0] $end
+     $var wire 32 & value [31:0] $end
     $upscope $end
     $scope module sub2c $end
-     $var wire 32 - ADD [31:0] $end
-     $var wire 32 # cyc [31:0] $end
-     $var wire 32 ( value [31:0] $end
+     $var wire 32 , ADD [31:0] $end
+     $var wire 32 " cyc [31:0] $end
+     $var wire 32 ' value [31:0] $end
     $upscope $end
    $upscope $end
   $upscope $end
@@ -35,122 +34,122 @@ $enddefinitions $end
 
 
 #0
-b00000000000000000000000000000000 #
-b00000000000000000000000000001010 $
-b00000000000000000000000000010100 %
-b00000000000000000000000000010101 &
-b00000000000000000000000000010110 '
-b00000000000000000000000000010111 (
-0)
-b00000000000000000000000000001010 *
-b00000000000000000000000000010100 +
-b00000000000000000000000000010110 ,
-b00000000000000000000000000010111 -
-#10
-b00000000000000000000000000000001 #
-b00000000000000000000000000001011 $
+b00000000000000000000000000000000 "
+b00000000000000000000000000001010 #
+b00000000000000000000000000010100 $
 b00000000000000000000000000010101 %
 b00000000000000000000000000010110 &
 b00000000000000000000000000010111 '
-b00000000000000000000000000011000 (
-1)
-#15
-0)
-#20
-b00000000000000000000000000000010 #
-b00000000000000000000000000001100 $
+0(
+b00000000000000000000000000001010 )
+b00000000000000000000000000010100 *
+b00000000000000000000000000010110 +
+b00000000000000000000000000010111 ,
+#10
+b00000000000000000000000000000001 "
+b00000000000000000000000000001011 #
+b00000000000000000000000000010101 $
 b00000000000000000000000000010110 %
 b00000000000000000000000000010111 &
 b00000000000000000000000000011000 '
-b00000000000000000000000000011001 (
-1)
-#25
-0)
-#30
-b00000000000000000000000000000011 #
-b00000000000000000000000000001101 $
+1(
+#15
+0(
+#20
+b00000000000000000000000000000010 "
+b00000000000000000000000000001100 #
+b00000000000000000000000000010110 $
 b00000000000000000000000000010111 %
 b00000000000000000000000000011000 &
 b00000000000000000000000000011001 '
-b00000000000000000000000000011010 (
-1)
-#35
-0)
-#40
-b00000000000000000000000000000100 #
-b00000000000000000000000000001110 $
+1(
+#25
+0(
+#30
+b00000000000000000000000000000011 "
+b00000000000000000000000000001101 #
+b00000000000000000000000000010111 $
 b00000000000000000000000000011000 %
 b00000000000000000000000000011001 &
 b00000000000000000000000000011010 '
-b00000000000000000000000000011011 (
-1)
-#45
-0)
-#50
-b00000000000000000000000000000101 #
-b00000000000000000000000000001111 $
+1(
+#35
+0(
+#40
+b00000000000000000000000000000100 "
+b00000000000000000000000000001110 #
+b00000000000000000000000000011000 $
 b00000000000000000000000000011001 %
 b00000000000000000000000000011010 &
 b00000000000000000000000000011011 '
-b00000000000000000000000000011100 (
-1)
-#55
-0)
-#60
-b00000000000000000000000000000110 #
-b00000000000000000000000000010000 $
+1(
+#45
+0(
+#50
+b00000000000000000000000000000101 "
+b00000000000000000000000000001111 #
+b00000000000000000000000000011001 $
 b00000000000000000000000000011010 %
 b00000000000000000000000000011011 &
 b00000000000000000000000000011100 '
-b00000000000000000000000000011101 (
-1)
-#65
-0)
-#70
-b00000000000000000000000000000111 #
-b00000000000000000000000000010001 $
+1(
+#55
+0(
+#60
+b00000000000000000000000000000110 "
+b00000000000000000000000000010000 #
+b00000000000000000000000000011010 $
 b00000000000000000000000000011011 %
 b00000000000000000000000000011100 &
 b00000000000000000000000000011101 '
-b00000000000000000000000000011110 (
-1)
-#75
-0)
-#80
-b00000000000000000000000000001000 #
-b00000000000000000000000000010010 $
+1(
+#65
+0(
+#70
+b00000000000000000000000000000111 "
+b00000000000000000000000000010001 #
+b00000000000000000000000000011011 $
 b00000000000000000000000000011100 %
 b00000000000000000000000000011101 &
 b00000000000000000000000000011110 '
-b00000000000000000000000000011111 (
-1)
-#85
-0)
-#90
-b00000000000000000000000000001001 #
-b00000000000000000000000000010011 $
+1(
+#75
+0(
+#80
+b00000000000000000000000000001000 "
+b00000000000000000000000000010010 #
+b00000000000000000000000000011100 $
 b00000000000000000000000000011101 %
 b00000000000000000000000000011110 &
 b00000000000000000000000000011111 '
-b00000000000000000000000000100000 (
-1)
-#95
-0)
-#100
-b00000000000000000000000000001010 #
-b00000000000000000000000000010100 $
+1(
+#85
+0(
+#90
+b00000000000000000000000000001001 "
+b00000000000000000000000000010011 #
+b00000000000000000000000000011101 $
 b00000000000000000000000000011110 %
 b00000000000000000000000000011111 &
 b00000000000000000000000000100000 '
-b00000000000000000000000000100001 (
-1)
-#105
-0)
-#110
-b00000000000000000000000000001011 #
-b00000000000000000000000000010101 $
+1(
+#95
+0(
+#100
+b00000000000000000000000000001010 "
+b00000000000000000000000000010100 #
+b00000000000000000000000000011110 $
 b00000000000000000000000000011111 %
 b00000000000000000000000000100000 &
 b00000000000000000000000000100001 '
-b00000000000000000000000000100010 (
-1)
+1(
+#105
+0(
+#110
+b00000000000000000000000000001011 "
+b00000000000000000000000000010101 #
+b00000000000000000000000000011111 $
+b00000000000000000000000000100000 %
+b00000000000000000000000000100001 &
+b00000000000000000000000000100010 '
+1(
diff --git a/test_regress/t/t_trace_split_struct.v b/test_regress/t/t_trace_split_struct.v
new file mode 100644
index 000000000..8e0f3e8b8
--- /dev/null
+++ b/test_regress/t/t_trace_split_struct.v
@@ -0,0 +1,45 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Wilson Snyder
+// SPDX-License-Identifier: CC0-1.0
+
+// Test that when struct fields are driven from different clocks,
+// no trace_chg_dtype function is created (fields must be traced individually).
+
+bit global_bit;
+
+module t (clk, clk2);
+   input clk;
+   input clk2;
+   integer cyc = 0;
+
+   typedef struct packed {
+      bit         b1;
+      bit         b0;
+   } strp_t;
+
+   strp_t       v_strp, v_strp2;
+   logic foo;
+
+   logic [7:0]       unpacked_array[-7:0];
+
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      foo <= ~foo;
+      v_strp.b0 <= cyc[0];
+      v_strp2.b0 <= cyc[2];
+      unpacked_array[0] = cyc[8:1];
+      if (cyc == 5) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+
+   always @(posedge clk2) begin
+      v_strp.b1 <= cyc[1];
+      v_strp2.b1 <= cyc[3];
+     for (int i = -1; i > -8; i--)
+       unpacked_array[i] = cyc[7:0];
+   end
+endmodule
diff --git a/test_regress/t/t_trace_split_struct_fst.out b/test_regress/t/t_trace_split_struct_fst.out
new file mode 100644
index 000000000..fe2492f0e
--- /dev/null
+++ b/test_regress/t/t_trace_split_struct_fst.out
@@ -0,0 +1,107 @@
+$date
+Tue Mar 31 17:23:31 2026
+
+$end
+$version
+Generated by VerilatedFst
+$end
+$timescale
+1ps
+$end
+ $scope module top $end
+  $var wire 1 ! clk $end
+  $var wire 1 " clk2 $end
+  $scope module $unit $end
+   $var bit 1 # global_bit $end
+  $upscope $end
+  $scope module t $end
+   $var wire 1 ! clk $end
+   $var wire 1 " clk2 $end
+   $var integer 32 $ cyc [31:0] $end
+   $attrbegin pack packed members 2 $end
+   $scope struct v_strp $end
+    $var bit 1 % b1 $end
+    $var bit 1 & b0 $end
+   $upscope $end
+   $attrbegin pack packed members 2 $end
+   $scope struct v_strp2 $end
+    $var bit 1 ' b1 $end
+    $var bit 1 ( b0 $end
+   $upscope $end
+   $var logic 1 ) foo $end
+   $attrbegin array unpacked bounds -30064771072 $end
+   $scope sv_array unpacked_array $end
+    $var logic 8 * unpacked_array[-7] [7:0] $end
+    $var logic 8 + unpacked_array[-6] [7:0] $end
+    $var logic 8 , unpacked_array[-5] [7:0] $end
+    $var logic 8 - unpacked_array[-4] [7:0] $end
+    $var logic 8 . unpacked_array[-3] [7:0] $end
+    $var logic 8 / unpacked_array[-2] [7:0] $end
+    $var logic 8 0 unpacked_array[-1] [7:0] $end
+    $var logic 8 1 unpacked_array[0] [7:0] $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b00000000 1
+b00000000 0
+b00000000 /
+b00000000 .
+b00000000 -
+b00000000 ,
+b00000000 +
+b00000000 *
+0)
+0(
+0'
+0&
+0%
+b00000000000000000000000000000000 $
+0#
+0"
+0!
+$end
+#10
+1!
+b00000000000000000000000000000001 $
+1)
+#15
+0!
+#20
+1!
+0)
+b00000000000000000000000000000010 $
+1&
+#25
+0!
+#30
+1!
+0&
+b00000000000000000000000000000011 $
+1)
+b00000001 1
+#35
+0!
+#40
+1!
+0)
+b00000000000000000000000000000100 $
+1&
+#45
+0!
+#50
+1!
+0&
+b00000000000000000000000000000101 $
+1)
+b00000010 1
+1(
+#55
+0!
+#60
+1!
+0)
+b00000000000000000000000000000110 $
+1&
diff --git a/test_regress/t/t_trace_split_struct_fst.py b/test_regress/t/t_trace_split_struct_fst.py
new file mode 100755
index 000000000..e60e691f2
--- /dev/null
+++ b/test_regress/t/t_trace_split_struct_fst.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_split_struct_common
+
+test.scenarios('vlt_all')
+
+trace_split_struct_common.run(test)
diff --git a/test_regress/t/t_trace_split_struct_saif.out b/test_regress/t/t_trace_split_struct_saif.out
new file mode 100644
index 000000000..902475760
--- /dev/null
+++ b/test_regress/t/t_trace_split_struct_saif.out
@@ -0,0 +1,135 @@
+// Generated by verilated_saif
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(PROGRAM_NAME "Verilator")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 60)
+ (INSTANCE top
+  (NET
+   (clk (T0 35) (T1 25) (TZ 0) (TX 0) (TB 0) (TC 11))
+   (clk2 (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+  )
+  (INSTANCE $unit
+   (NET
+    (global_bit (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   )
+  )
+  (INSTANCE t
+   (NET
+    (clk (T0 35) (T1 25) (TZ 0) (TX 0) (TB 0) (TC 11))
+    (clk2 (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[0\] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (cyc\[1\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
+    (cyc\[2\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (cyc\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[8\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[9\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[10\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[11\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[12\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[13\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[14\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[15\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[16\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[17\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[18\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[19\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[20\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[21\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[22\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[23\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[24\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[25\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[26\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[27\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[28\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[29\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[30\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[31\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (foo (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+    (unpacked_array[-7]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-7]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-7]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-7]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-7]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-7]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-7]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-7]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-6]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-6]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-6]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-6]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-6]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-6]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-6]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-6]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-5]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-5]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-5]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-5]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-5]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-5]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-5]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-5]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-4]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-4]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-4]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-4]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-4]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-4]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-4]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-4]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-3]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-3]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-3]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-3]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-3]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-3]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-3]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-3]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-2]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-2]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-2]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-2]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-2]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-2]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-2]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-2]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-1]\[0\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-1]\[1\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-1]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-1]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-1]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-1]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-1]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[-1]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[0]\[0\] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
+    (unpacked_array[0]\[1\] (T0 50) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (unpacked_array[0]\[2\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[0]\[3\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[0]\[4\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[0]\[5\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[0]\[6\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (unpacked_array[0]\[7\] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   )
+   (INSTANCE v_strp
+    (NET
+     (b1 (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (b0 (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 5))
+    )
+   )
+   (INSTANCE v_strp2
+    (NET
+     (b1 (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (b0 (T0 50) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+    )
+   )
+  )
+ )
+)
diff --git a/test_regress/t/t_trace_split_struct_saif.py b/test_regress/t/t_trace_split_struct_saif.py
new file mode 100755
index 000000000..e60e691f2
--- /dev/null
+++ b/test_regress/t/t_trace_split_struct_saif.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_split_struct_common
+
+test.scenarios('vlt_all')
+
+trace_split_struct_common.run(test)
diff --git a/test_regress/t/t_trace_split_struct_vcd.out b/test_regress/t/t_trace_split_struct_vcd.out
new file mode 100644
index 000000000..c5dd775fd
--- /dev/null
+++ b/test_regress/t/t_trace_split_struct_vcd.out
@@ -0,0 +1,94 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module top $end
+  $var wire 1 - clk $end
+  $var wire 1 . clk2 $end
+  $scope module $unit $end
+   $var wire 1 2 global_bit $end
+  $upscope $end
+  $scope module t $end
+   $var wire 1 - clk $end
+   $var wire 1 . clk2 $end
+   $var wire 32 / cyc [31:0] $end
+   $scope module v_strp $end
+    $var wire 1 0 b1 $end
+    $var wire 1 " b0 $end
+   $upscope $end
+   $scope module v_strp2 $end
+    $var wire 1 1 b1 $end
+    $var wire 1 # b0 $end
+   $upscope $end
+   $var wire 1 $ foo $end
+   $var wire 8 % unpacked_array[-7] [7:0] $end
+   $var wire 8 & unpacked_array[-6] [7:0] $end
+   $var wire 8 ' unpacked_array[-5] [7:0] $end
+   $var wire 8 ( unpacked_array[-4] [7:0] $end
+   $var wire 8 ) unpacked_array[-3] [7:0] $end
+   $var wire 8 * unpacked_array[-2] [7:0] $end
+   $var wire 8 + unpacked_array[-1] [7:0] $end
+   $var wire 8 , unpacked_array[0] [7:0] $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+0"
+0#
+0$
+b00000000 %
+b00000000 &
+b00000000 '
+b00000000 (
+b00000000 )
+b00000000 *
+b00000000 +
+b00000000 ,
+0-
+0.
+b00000000000000000000000000000000 /
+00
+01
+02
+#10
+1$
+1-
+b00000000000000000000000000000001 /
+#15
+0-
+#20
+1"
+0$
+1-
+b00000000000000000000000000000010 /
+#25
+0-
+#30
+0"
+1$
+b00000001 ,
+1-
+b00000000000000000000000000000011 /
+#35
+0-
+#40
+1"
+0$
+1-
+b00000000000000000000000000000100 /
+#45
+0-
+#50
+0"
+1#
+1$
+b00000010 ,
+1-
+b00000000000000000000000000000101 /
+#55
+0-
+#60
+1"
+0$
+1-
+b00000000000000000000000000000110 /
diff --git a/test_regress/t/t_trace_split_struct_vcd.py b/test_regress/t/t_trace_split_struct_vcd.py
new file mode 100755
index 000000000..e60e691f2
--- /dev/null
+++ b/test_regress/t/t_trace_split_struct_vcd.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_split_struct_common
+
+test.scenarios('vlt_all')
+
+trace_split_struct_common.run(test)
diff --git a/test_regress/t/t_trace_struct_alias.v b/test_regress/t/t_trace_struct_alias.v
new file mode 100644
index 000000000..3019a929f
--- /dev/null
+++ b/test_regress/t/t_trace_struct_alias.v
@@ -0,0 +1,47 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Wilson Snyder
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+   int cyc;
+
+   typedef struct packed {
+      logic [7:0] a;
+      logic [7:0] b;
+   } strp_t;
+
+   strp_t s1;
+   strp_t s2;
+
+   strp_t s3;
+   logic [7:0] alias_of_s3a;
+   assign alias_of_s3a = s3.a;
+
+   strp_t s4;
+   strp_t s5;
+   assign s5 = s4;
+
+   logic [7:0] source_val;
+   strp_t s6;
+   assign s6.a = source_val;
+
+   always @(posedge clk) begin
+      cyc <= cyc + 1;
+      s1 <= {8'(cyc), 8'(cyc + 1)};
+      s2 <= {8'(cyc + 2), 8'(cyc + 3)};
+      s3 <= {8'(cyc + 4), 8'(cyc + 5)};
+      s4 <= {8'(cyc + 6), 8'(cyc + 7)};
+      source_val <= 8'(cyc + 8);
+      s6.b <= 8'(cyc + 9);
+      if (cyc == 9) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+endmodule
diff --git a/test_regress/t/t_trace_struct_alias_fst.out b/test_regress/t/t_trace_struct_alias_fst.out
new file mode 100644
index 000000000..326c1fa25
--- /dev/null
+++ b/test_regress/t/t_trace_struct_alias_fst.out
@@ -0,0 +1,212 @@
+$date
+Tue Mar 31 17:14:59 2026
+
+$end
+$version
+Generated by VerilatedFst
+$end
+$timescale
+1ps
+$end
+ $scope module top $end
+  $var wire 1 ! clk $end
+  $scope module t $end
+   $var wire 1 ! clk $end
+   $var int 32 " cyc [31:0] $end
+   $attrbegin pack packed members 2 $end
+   $scope struct s1 $end
+    $var logic 8 # a [7:0] $end
+    $var logic 8 $ b [7:0] $end
+   $upscope $end
+   $attrbegin pack packed members 2 $end
+   $scope struct s2 $end
+    $var logic 8 % a [7:0] $end
+    $var logic 8 & b [7:0] $end
+   $upscope $end
+   $attrbegin pack packed members 2 $end
+   $scope struct s3 $end
+    $var logic 8 ' a [7:0] $end
+    $var logic 8 ( b [7:0] $end
+   $upscope $end
+   $var logic 8 ' alias_of_s3a [7:0] $end
+   $attrbegin pack packed members 2 $end
+   $scope struct s4 $end
+    $var logic 8 ) a [7:0] $end
+    $var logic 8 * b [7:0] $end
+   $upscope $end
+   $attrbegin pack packed members 2 $end
+   $scope struct s5 $end
+    $var logic 8 ) a [7:0] $end
+    $var logic 8 * b [7:0] $end
+   $upscope $end
+   $var logic 8 + source_val [7:0] $end
+   $attrbegin pack packed members 2 $end
+   $scope struct s6 $end
+    $var logic 8 + a [7:0] $end
+    $var logic 8 , b [7:0] $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b00000000 ,
+b00000000 +
+b00000000 *
+b00000000 )
+b00000000 (
+b00000000 '
+b00000000 &
+b00000000 %
+b00000000 $
+b00000000 #
+b00000000000000000000000000000000 "
+0!
+$end
+#10
+1!
+b00000000000000000000000000000001 "
+b00000001 $
+b00000010 %
+b00000011 &
+b00000100 '
+b00000101 (
+b00000110 )
+b00000111 *
+b00001000 +
+b00001001 ,
+#15
+0!
+#20
+1!
+b00001010 ,
+b00001001 +
+b00001000 *
+b00000111 )
+b00000110 (
+b00000101 '
+b00000100 &
+b00000011 %
+b00000010 $
+b00000000000000000000000000000010 "
+b00000001 #
+#25
+0!
+#30
+1!
+b00000010 #
+b00000000000000000000000000000011 "
+b00000011 $
+b00000100 %
+b00000101 &
+b00000110 '
+b00000111 (
+b00001000 )
+b00001001 *
+b00001010 +
+b00001011 ,
+#35
+0!
+#40
+1!
+b00001100 ,
+b00001011 +
+b00001010 *
+b00001001 )
+b00001000 (
+b00000111 '
+b00000110 &
+b00000101 %
+b00000100 $
+b00000000000000000000000000000100 "
+b00000011 #
+#45
+0!
+#50
+1!
+b00000100 #
+b00000000000000000000000000000101 "
+b00000101 $
+b00000110 %
+b00000111 &
+b00001000 '
+b00001001 (
+b00001010 )
+b00001011 *
+b00001100 +
+b00001101 ,
+#55
+0!
+#60
+1!
+b00001110 ,
+b00001101 +
+b00001100 *
+b00001011 )
+b00001010 (
+b00001001 '
+b00001000 &
+b00000111 %
+b00000110 $
+b00000000000000000000000000000110 "
+b00000101 #
+#65
+0!
+#70
+1!
+b00000110 #
+b00000000000000000000000000000111 "
+b00000111 $
+b00001000 %
+b00001001 &
+b00001010 '
+b00001011 (
+b00001100 )
+b00001101 *
+b00001110 +
+b00001111 ,
+#75
+0!
+#80
+1!
+b00010000 ,
+b00001111 +
+b00001110 *
+b00001101 )
+b00001100 (
+b00001011 '
+b00001010 &
+b00001001 %
+b00001000 $
+b00000000000000000000000000001000 "
+b00000111 #
+#85
+0!
+#90
+1!
+b00001000 #
+b00000000000000000000000000001001 "
+b00001001 $
+b00001010 %
+b00001011 &
+b00001100 '
+b00001101 (
+b00001110 )
+b00001111 *
+b00010000 +
+b00010001 ,
+#95
+0!
+#100
+1!
+b00010010 ,
+b00010001 +
+b00010000 *
+b00001111 )
+b00001110 (
+b00001101 '
+b00001100 &
+b00001011 %
+b00001010 $
+b00000000000000000000000000001010 "
+b00001001 #
diff --git a/test_regress/t/t_trace_struct_alias_fst.py b/test_regress/t/t_trace_struct_alias_fst.py
new file mode 100755
index 000000000..3fa9e9bce
--- /dev/null
+++ b/test_regress/t/t_trace_struct_alias_fst.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_struct_alias_common
+
+test.scenarios('vlt_all')
+
+trace_struct_alias_common.run(test)
diff --git a/test_regress/t/t_trace_struct_alias_vcd.out b/test_regress/t/t_trace_struct_alias_vcd.out
new file mode 100644
index 000000000..9a5d26e01
--- /dev/null
+++ b/test_regress/t/t_trace_struct_alias_vcd.out
@@ -0,0 +1,198 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module top $end
+  $var wire 1 - clk $end
+  $scope module t $end
+   $var wire 1 - clk $end
+   $var wire 32 " cyc [31:0] $end
+   $scope module s1 $end
+    $var wire 8 # a [7:0] $end
+    $var wire 8 $ b [7:0] $end
+   $upscope $end
+   $scope module s2 $end
+    $var wire 8 % a [7:0] $end
+    $var wire 8 & b [7:0] $end
+   $upscope $end
+   $scope module s3 $end
+    $var wire 8 ' a [7:0] $end
+    $var wire 8 ( b [7:0] $end
+   $upscope $end
+   $var wire 8 ' alias_of_s3a [7:0] $end
+   $scope module s4 $end
+    $var wire 8 ) a [7:0] $end
+    $var wire 8 * b [7:0] $end
+   $upscope $end
+   $scope module s5 $end
+    $var wire 8 ) a [7:0] $end
+    $var wire 8 * b [7:0] $end
+   $upscope $end
+   $var wire 8 + source_val [7:0] $end
+   $scope module s6 $end
+    $var wire 8 + a [7:0] $end
+    $var wire 8 , b [7:0] $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 "
+b00000000 #
+b00000000 $
+b00000000 %
+b00000000 &
+b00000000 '
+b00000000 (
+b00000000 )
+b00000000 *
+b00000000 +
+b00000000 ,
+0-
+#10
+b00000000000000000000000000000001 "
+b00000001 $
+b00000010 %
+b00000011 &
+b00000100 '
+b00000101 (
+b00000110 )
+b00000111 *
+b00001000 +
+b00001001 ,
+1-
+#15
+0-
+#20
+b00000000000000000000000000000010 "
+b00000001 #
+b00000010 $
+b00000011 %
+b00000100 &
+b00000101 '
+b00000110 (
+b00000111 )
+b00001000 *
+b00001001 +
+b00001010 ,
+1-
+#25
+0-
+#30
+b00000000000000000000000000000011 "
+b00000010 #
+b00000011 $
+b00000100 %
+b00000101 &
+b00000110 '
+b00000111 (
+b00001000 )
+b00001001 *
+b00001010 +
+b00001011 ,
+1-
+#35
+0-
+#40
+b00000000000000000000000000000100 "
+b00000011 #
+b00000100 $
+b00000101 %
+b00000110 &
+b00000111 '
+b00001000 (
+b00001001 )
+b00001010 *
+b00001011 +
+b00001100 ,
+1-
+#45
+0-
+#50
+b00000000000000000000000000000101 "
+b00000100 #
+b00000101 $
+b00000110 %
+b00000111 &
+b00001000 '
+b00001001 (
+b00001010 )
+b00001011 *
+b00001100 +
+b00001101 ,
+1-
+#55
+0-
+#60
+b00000000000000000000000000000110 "
+b00000101 #
+b00000110 $
+b00000111 %
+b00001000 &
+b00001001 '
+b00001010 (
+b00001011 )
+b00001100 *
+b00001101 +
+b00001110 ,
+1-
+#65
+0-
+#70
+b00000000000000000000000000000111 "
+b00000110 #
+b00000111 $
+b00001000 %
+b00001001 &
+b00001010 '
+b00001011 (
+b00001100 )
+b00001101 *
+b00001110 +
+b00001111 ,
+1-
+#75
+0-
+#80
+b00000000000000000000000000001000 "
+b00000111 #
+b00001000 $
+b00001001 %
+b00001010 &
+b00001011 '
+b00001100 (
+b00001101 )
+b00001110 *
+b00001111 +
+b00010000 ,
+1-
+#85
+0-
+#90
+b00000000000000000000000000001001 "
+b00001000 #
+b00001001 $
+b00001010 %
+b00001011 &
+b00001100 '
+b00001101 (
+b00001110 )
+b00001111 *
+b00010000 +
+b00010001 ,
+1-
+#95
+0-
+#100
+b00000000000000000000000000001010 "
+b00001001 #
+b00001010 $
+b00001011 %
+b00001100 &
+b00001101 '
+b00001110 (
+b00001111 )
+b00010000 *
+b00010001 +
+b00010010 ,
+1-
diff --git a/test_regress/t/t_trace_struct_alias_vcd.py b/test_regress/t/t_trace_struct_alias_vcd.py
new file mode 100755
index 000000000..3fa9e9bce
--- /dev/null
+++ b/test_regress/t/t_trace_struct_alias_vcd.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_struct_alias_common
+
+test.scenarios('vlt_all')
+
+trace_struct_alias_common.run(test)
diff --git a/test_regress/t/t_trace_struct_array_multi_inst.v b/test_regress/t/t_trace_struct_array_multi_inst.v
new file mode 100644
index 000000000..0eabe6bf5
--- /dev/null
+++ b/test_regress/t/t_trace_struct_array_multi_inst.v
@@ -0,0 +1,56 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Wilson Snyder
+// SPDX-License-Identifier: CC0-1.0
+
+// Test that arrays of structs with nested sub-members produce
+// correct aliases (not empty scopes) across module instances.
+
+module t (
+    input clk
+);
+
+  int cnt;
+
+  initial cnt = 0;
+  always @(posedge clk) begin
+    cnt <= cnt + 1;
+    if (cnt == 3) begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+    end
+  end
+
+  sub sub_a (.clk, .seed(cnt));
+  sub sub_b (.clk, .seed(cnt + 100));
+endmodule
+
+module sub (
+    input clk,
+    input int seed
+);
+
+  typedef struct packed {
+    logic [7:0] x;
+    logic [7:0] y;
+  } inner_t;
+
+  typedef struct packed {
+    inner_t sub;
+    logic [1:0] [7:0] arr;
+    logic [7:0] simple;
+  } outer_t;
+
+  // Unpacked array of struct with nested sub-struct and packed array
+  outer_t uarr [1:0];
+
+  always @(posedge clk) begin
+    uarr[0] <= '{sub: '{x: seed[7:0], y: seed[15:8]},
+                 arr: '{seed[7:0], seed[7:0]+8'd1},
+                 simple: seed[7:0]};
+    uarr[1] <= '{sub: '{x: ~seed[7:0], y: ~seed[15:8]},
+                 arr: '{~seed[7:0], ~seed[7:0]+8'd1},
+                 simple: ~seed[7:0]};
+  end
+endmodule
diff --git a/test_regress/t/t_trace_struct_array_multi_inst_cc_fst.out b/test_regress/t/t_trace_struct_array_multi_inst_cc_fst.out
new file mode 100644
index 000000000..c80f33fe4
--- /dev/null
+++ b/test_regress/t/t_trace_struct_array_multi_inst_cc_fst.out
@@ -0,0 +1,198 @@
+$date
+Fri Apr 10 17:07:13 2026
+
+$end
+$version
+Generated by VerilatedFst
+$end
+$timescale
+1ps
+$end
+ $scope module top $end
+  $var wire 1 ! clk $end
+  $scope module t $end
+   $var wire 1 ! clk $end
+   $var int 32 " cnt [31:0] $end
+   $scope module sub_a $end
+    $var wire 1 ! clk $end
+    $var wire 32 " seed [31:0] $end
+    $attrbegin array unpacked bounds 4294967296 $end
+    $scope sv_array uarr $end
+     $attrbegin pack packed members 3 $end
+     $scope struct [1] $end
+      $attrbegin pack packed members 2 $end
+      $scope struct sub $end
+       $var logic 8 # x [7:0] $end
+       $var logic 8 $ y [7:0] $end
+      $upscope $end
+      $attrbegin array packed bounds 4294967296 $end
+      $scope sv_array arr $end
+       $var logic 8 % arr[1] [7:0] $end
+       $var logic 8 & arr[0] [7:0] $end
+      $upscope $end
+      $var logic 8 ' simple [7:0] $end
+     $upscope $end
+     $attrbegin pack packed members 3 $end
+     $scope struct [0] $end
+      $attrbegin pack packed members 2 $end
+      $scope struct sub $end
+       $var logic 8 ( x [7:0] $end
+       $var logic 8 ) y [7:0] $end
+      $upscope $end
+      $attrbegin array packed bounds 4294967296 $end
+      $scope sv_array arr $end
+       $var logic 8 * arr[1] [7:0] $end
+       $var logic 8 + arr[0] [7:0] $end
+      $upscope $end
+      $var logic 8 , simple [7:0] $end
+     $upscope $end
+    $upscope $end
+   $upscope $end
+   $scope module sub_b $end
+    $var wire 1 ! clk $end
+    $var wire 32 - seed [31:0] $end
+    $attrbegin array unpacked bounds 4294967296 $end
+    $scope sv_array uarr $end
+     $attrbegin pack packed members 3 $end
+     $scope struct [1] $end
+      $attrbegin pack packed members 2 $end
+      $scope struct sub $end
+       $var logic 8 . x [7:0] $end
+       $var logic 8 / y [7:0] $end
+      $upscope $end
+      $attrbegin array packed bounds 4294967296 $end
+      $scope sv_array arr $end
+       $var logic 8 0 arr[1] [7:0] $end
+       $var logic 8 1 arr[0] [7:0] $end
+      $upscope $end
+      $var logic 8 2 simple [7:0] $end
+     $upscope $end
+     $attrbegin pack packed members 3 $end
+     $scope struct [0] $end
+      $attrbegin pack packed members 2 $end
+      $scope struct sub $end
+       $var logic 8 3 x [7:0] $end
+       $var logic 8 4 y [7:0] $end
+      $upscope $end
+      $attrbegin array packed bounds 4294967296 $end
+      $scope sv_array arr $end
+       $var logic 8 5 arr[1] [7:0] $end
+       $var logic 8 6 arr[0] [7:0] $end
+      $upscope $end
+      $var logic 8 7 simple [7:0] $end
+     $upscope $end
+    $upscope $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b00000000 7
+b00000000 6
+b00000000 5
+b00000000 4
+b00000000 3
+b00000000 2
+b00000000 1
+b00000000 0
+b00000000 /
+b00000000 .
+b00000000000000000000000001100100 -
+b00000000 ,
+b00000000 +
+b00000000 *
+b00000000 )
+b00000000 (
+b00000000 '
+b00000000 &
+b00000000 %
+b00000000 $
+b00000000 #
+b00000000000000000000000000000000 "
+0!
+$end
+#10
+1!
+b00000000000000000000000000000001 "
+b11111111 #
+b11111111 $
+b11111111 %
+b11111111 '
+b00000001 +
+b00000000000000000000000001100101 -
+b10011011 .
+b11111111 /
+b10011011 0
+b10011100 1
+b10011011 2
+b01100100 3
+b01100100 5
+b01100101 6
+b01100100 7
+#15
+0!
+#20
+1!
+b01100101 7
+b01100110 6
+b01100101 5
+b01100101 3
+b10011010 2
+b10011011 1
+b10011010 0
+b10011010 .
+b00000000000000000000000001100110 -
+b00000010 +
+b11111110 '
+b11111110 %
+b11111110 #
+b00000000000000000000000000000010 "
+b11111111 &
+b00000001 (
+b00000001 *
+b00000001 ,
+#25
+0!
+#30
+1!
+b00000010 ,
+b00000010 *
+b00000010 (
+b11111110 &
+b00000000000000000000000000000011 "
+b11111101 #
+b11111101 %
+b11111101 '
+b00000011 +
+b00000000000000000000000001100111 -
+b10011001 .
+b10011001 0
+b10011010 1
+b10011001 2
+b01100110 3
+b01100110 5
+b01100111 6
+b01100110 7
+#35
+0!
+#40
+1!
+b01100111 7
+b01101000 6
+b01100111 5
+b01100111 3
+b10011000 2
+b10011001 1
+b10011000 0
+b10011000 .
+b00000000000000000000000001101000 -
+b00000100 +
+b11111100 '
+b11111100 %
+b11111100 #
+b00000000000000000000000000000100 "
+b11111101 &
+b00000011 (
+b00000011 *
+b00000011 ,
diff --git a/test_regress/t/t_trace_struct_array_multi_inst_cc_fst.py b/test_regress/t/t_trace_struct_array_multi_inst_cc_fst.py
new file mode 100755
index 000000000..7e778d937
--- /dev/null
+++ b/test_regress/t/t_trace_struct_array_multi_inst_cc_fst.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_struct_array_multi_inst_common
+
+test.scenarios('vlt_all')
+
+trace_struct_array_multi_inst_common.run(test)
diff --git a/test_regress/t/t_trace_struct_array_multi_inst_cc_saif.out b/test_regress/t/t_trace_struct_array_multi_inst_cc_saif.out
new file mode 100644
index 000000000..cd7b5186f
--- /dev/null
+++ b/test_regress/t/t_trace_struct_array_multi_inst_cc_saif.out
@@ -0,0 +1,317 @@
+// Generated by verilated_saif
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(PROGRAM_NAME "Verilator")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 40)
+ (INSTANCE top
+  (NET
+   (clk (T0 25) (T1 15) (TZ 0) (TX 0) (TB 0) (TC 7))
+  )
+  (INSTANCE t
+   (NET
+    (clk (T0 25) (T1 15) (TZ 0) (TX 0) (TB 0) (TC 7))
+    (cnt\[0\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+    (cnt\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
+    (cnt\[2\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (cnt\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[8\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[9\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[10\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[11\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[12\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[13\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[14\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[15\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[16\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[17\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[18\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[19\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[20\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[21\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[22\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[23\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[24\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[25\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[26\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[27\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[28\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[29\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[30\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[31\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   )
+   (INSTANCE sub_a
+    (NET
+     (clk (T0 25) (T1 15) (TZ 0) (TX 0) (TB 0) (TC 7))
+     (seed\[0\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+     (seed\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (seed\[2\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (seed\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[8\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[9\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[10\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[11\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[12\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[13\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[14\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[15\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[16\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[17\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[18\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[19\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[20\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[21\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[22\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[23\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[24\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[25\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[26\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[27\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[28\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[29\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[30\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[31\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    )
+    (INSTANCE uarr[1]
+     (NET
+      (arr[1]\[0\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+      (arr[1]\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (arr[1]\[2\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (arr[1]\[3\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (arr[1]\[4\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (arr[1]\[5\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (arr[1]\[6\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (arr[1]\[7\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (arr[0]\[0\] (T0 30) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 3))
+      (arr[0]\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (arr[0]\[2\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (arr[0]\[3\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (arr[0]\[4\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (arr[0]\[5\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (arr[0]\[6\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (arr[0]\[7\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (simple\[0\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+      (simple\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (simple\[2\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (simple\[3\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (simple\[4\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (simple\[5\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (simple\[6\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (simple\[7\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+     )
+     (INSTANCE sub
+      (NET
+       (x\[0\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (x\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (x\[2\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (x\[3\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (x\[4\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (x\[5\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (x\[6\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (x\[7\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (y\[0\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (y\[1\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (y\[2\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (y\[3\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (y\[4\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (y\[5\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (y\[6\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (y\[7\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      )
+     )
+    )
+    (INSTANCE uarr[0]
+     (NET
+      (arr[1]\[0\] (T0 30) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 3))
+      (arr[1]\[1\] (T0 30) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (arr[1]\[2\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (arr[1]\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (arr[1]\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (arr[1]\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (arr[1]\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (arr[1]\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (arr[0]\[0\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+      (arr[0]\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (arr[0]\[2\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (arr[0]\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (arr[0]\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (arr[0]\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (arr[0]\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (arr[0]\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (simple\[0\] (T0 30) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 3))
+      (simple\[1\] (T0 30) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (simple\[2\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (simple\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (simple\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (simple\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (simple\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (simple\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     )
+     (INSTANCE sub
+      (NET
+       (x\[0\] (T0 30) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (x\[1\] (T0 30) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (x\[2\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (x\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (x\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (x\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (x\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (x\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (y\[0\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (y\[1\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (y\[2\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (y\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (y\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (y\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (y\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (y\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+     )
+    )
+   )
+   (INSTANCE sub_b
+    (NET
+     (clk (T0 25) (T1 15) (TZ 0) (TX 0) (TB 0) (TC 7))
+     (seed\[0\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+     (seed\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (seed\[2\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (seed\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (seed\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[5\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (seed\[6\] (T0 0) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (seed\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[8\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[9\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[10\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[11\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[12\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[13\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[14\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[15\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[16\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[17\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[18\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[19\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[20\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[21\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[22\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[23\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[24\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[25\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[26\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[27\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[28\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[29\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[30\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (seed\[31\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    )
+    (INSTANCE uarr[1]
+     (NET
+      (arr[1]\[0\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+      (arr[1]\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (arr[1]\[2\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (arr[1]\[3\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (arr[1]\[4\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (arr[1]\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (arr[1]\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (arr[1]\[7\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (arr[0]\[0\] (T0 30) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 3))
+      (arr[0]\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (arr[0]\[2\] (T0 30) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (arr[0]\[3\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (arr[0]\[4\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (arr[0]\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (arr[0]\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (arr[0]\[7\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (simple\[0\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+      (simple\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (simple\[2\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (simple\[3\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (simple\[4\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (simple\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (simple\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (simple\[7\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+     )
+     (INSTANCE sub
+      (NET
+       (x\[0\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (x\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (x\[2\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (x\[3\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (x\[4\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (x\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (x\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (x\[7\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (y\[0\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (y\[1\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (y\[2\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (y\[3\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (y\[4\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (y\[5\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (y\[6\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (y\[7\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      )
+     )
+    )
+    (INSTANCE uarr[0]
+     (NET
+      (arr[1]\[0\] (T0 30) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 3))
+      (arr[1]\[1\] (T0 30) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (arr[1]\[2\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (arr[1]\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (arr[1]\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (arr[1]\[5\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (arr[1]\[6\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (arr[1]\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (arr[0]\[0\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+      (arr[0]\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (arr[0]\[2\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (arr[0]\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (arr[0]\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (arr[0]\[5\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (arr[0]\[6\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (arr[0]\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (simple\[0\] (T0 30) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 3))
+      (simple\[1\] (T0 30) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (simple\[2\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (simple\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (simple\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (simple\[5\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (simple\[6\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (simple\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     )
+     (INSTANCE sub
+      (NET
+       (x\[0\] (T0 30) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (x\[1\] (T0 30) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (x\[2\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (x\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (x\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (x\[5\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (x\[6\] (T0 10) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (x\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (y\[0\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (y\[1\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (y\[2\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (y\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (y\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (y\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (y\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (y\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+     )
+    )
+   )
+  )
+ )
+)
diff --git a/test_regress/t/t_trace_struct_array_multi_inst_cc_saif.py b/test_regress/t/t_trace_struct_array_multi_inst_cc_saif.py
new file mode 100755
index 000000000..7e778d937
--- /dev/null
+++ b/test_regress/t/t_trace_struct_array_multi_inst_cc_saif.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_struct_array_multi_inst_common
+
+test.scenarios('vlt_all')
+
+trace_struct_array_multi_inst_common.run(test)
diff --git a/test_regress/t/t_trace_struct_array_multi_inst_cc_vcd.out b/test_regress/t/t_trace_struct_array_multi_inst_cc_vcd.out
new file mode 100644
index 000000000..afc185f5f
--- /dev/null
+++ b/test_regress/t/t_trace_struct_array_multi_inst_cc_vcd.out
@@ -0,0 +1,164 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module top $end
+  $var wire 1 8 clk $end
+  $scope module t $end
+   $var wire 1 8 clk $end
+   $var wire 32 " cnt [31:0] $end
+   $scope module sub_a $end
+    $var wire 1 8 clk $end
+    $var wire 32 " seed [31:0] $end
+    $scope module uarr[1] $end
+     $scope module sub $end
+      $var wire 8 # x [7:0] $end
+      $var wire 8 $ y [7:0] $end
+     $upscope $end
+     $var wire 8 % arr[1] [7:0] $end
+     $var wire 8 & arr[0] [7:0] $end
+     $var wire 8 ' simple [7:0] $end
+    $upscope $end
+    $scope module uarr[0] $end
+     $scope module sub $end
+      $var wire 8 ( x [7:0] $end
+      $var wire 8 ) y [7:0] $end
+     $upscope $end
+     $var wire 8 * arr[1] [7:0] $end
+     $var wire 8 + arr[0] [7:0] $end
+     $var wire 8 , simple [7:0] $end
+    $upscope $end
+   $upscope $end
+   $scope module sub_b $end
+    $var wire 1 8 clk $end
+    $var wire 32 - seed [31:0] $end
+    $scope module uarr[1] $end
+     $scope module sub $end
+      $var wire 8 . x [7:0] $end
+      $var wire 8 / y [7:0] $end
+     $upscope $end
+     $var wire 8 0 arr[1] [7:0] $end
+     $var wire 8 1 arr[0] [7:0] $end
+     $var wire 8 2 simple [7:0] $end
+    $upscope $end
+    $scope module uarr[0] $end
+     $scope module sub $end
+      $var wire 8 3 x [7:0] $end
+      $var wire 8 4 y [7:0] $end
+     $upscope $end
+     $var wire 8 5 arr[1] [7:0] $end
+     $var wire 8 6 arr[0] [7:0] $end
+     $var wire 8 7 simple [7:0] $end
+    $upscope $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 "
+b00000000 #
+b00000000 $
+b00000000 %
+b00000000 &
+b00000000 '
+b00000000 (
+b00000000 )
+b00000000 *
+b00000000 +
+b00000000 ,
+b00000000000000000000000001100100 -
+b00000000 .
+b00000000 /
+b00000000 0
+b00000000 1
+b00000000 2
+b00000000 3
+b00000000 4
+b00000000 5
+b00000000 6
+b00000000 7
+08
+#10
+b00000000000000000000000000000001 "
+b11111111 #
+b11111111 $
+b11111111 %
+b11111111 '
+b00000001 +
+b00000000000000000000000001100101 -
+b10011011 .
+b11111111 /
+b10011011 0
+b10011100 1
+b10011011 2
+b01100100 3
+b01100100 5
+b01100101 6
+b01100100 7
+18
+#15
+08
+#20
+b00000000000000000000000000000010 "
+b11111110 #
+b11111110 %
+b11111111 &
+b11111110 '
+b00000001 (
+b00000001 *
+b00000010 +
+b00000001 ,
+b00000000000000000000000001100110 -
+b10011010 .
+b10011010 0
+b10011011 1
+b10011010 2
+b01100101 3
+b01100101 5
+b01100110 6
+b01100101 7
+18
+#25
+08
+#30
+b00000000000000000000000000000011 "
+b11111101 #
+b11111101 %
+b11111110 &
+b11111101 '
+b00000010 (
+b00000010 *
+b00000011 +
+b00000010 ,
+b00000000000000000000000001100111 -
+b10011001 .
+b10011001 0
+b10011010 1
+b10011001 2
+b01100110 3
+b01100110 5
+b01100111 6
+b01100110 7
+18
+#35
+08
+#40
+b00000000000000000000000000000100 "
+b11111100 #
+b11111100 %
+b11111101 &
+b11111100 '
+b00000011 (
+b00000011 *
+b00000100 +
+b00000011 ,
+b00000000000000000000000001101000 -
+b10011000 .
+b10011000 0
+b10011001 1
+b10011000 2
+b01100111 3
+b01100111 5
+b01101000 6
+b01100111 7
+18
diff --git a/test_regress/t/t_trace_struct_array_multi_inst_cc_vcd.py b/test_regress/t/t_trace_struct_array_multi_inst_cc_vcd.py
new file mode 100755
index 000000000..7e778d937
--- /dev/null
+++ b/test_regress/t/t_trace_struct_array_multi_inst_cc_vcd.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_struct_array_multi_inst_common
+
+test.scenarios('vlt_all')
+
+trace_struct_array_multi_inst_common.run(test)
diff --git a/test_regress/t/t_trace_struct_array_multi_inst_sc_fst.out b/test_regress/t/t_trace_struct_array_multi_inst_sc_fst.out
new file mode 100644
index 000000000..686146531
--- /dev/null
+++ b/test_regress/t/t_trace_struct_array_multi_inst_sc_fst.out
@@ -0,0 +1,198 @@
+$date
+Mon Apr 13 09:26:20 2026
+
+$end
+$version
+Generated by VerilatedFst
+$end
+$timescale
+1ps
+$end
+ $scope module top $end
+  $scope module t $end
+   $var wire 1 ! clk $end
+   $var int 32 " cnt [31:0] $end
+   $scope module sub_a $end
+    $var wire 1 ! clk $end
+    $var wire 32 " seed [31:0] $end
+    $attrbegin array unpacked bounds 4294967296 $end
+    $scope sv_array uarr $end
+     $attrbegin pack packed members 3 $end
+     $scope struct [1] $end
+      $attrbegin pack packed members 2 $end
+      $scope struct sub $end
+       $var logic 8 # x [7:0] $end
+       $var logic 8 $ y [7:0] $end
+      $upscope $end
+      $attrbegin array packed bounds 4294967296 $end
+      $scope sv_array arr $end
+       $var logic 8 % arr[1] [7:0] $end
+       $var logic 8 & arr[0] [7:0] $end
+      $upscope $end
+      $var logic 8 ' simple [7:0] $end
+     $upscope $end
+     $attrbegin pack packed members 3 $end
+     $scope struct [0] $end
+      $attrbegin pack packed members 2 $end
+      $scope struct sub $end
+       $var logic 8 ( x [7:0] $end
+       $var logic 8 ) y [7:0] $end
+      $upscope $end
+      $attrbegin array packed bounds 4294967296 $end
+      $scope sv_array arr $end
+       $var logic 8 * arr[1] [7:0] $end
+       $var logic 8 + arr[0] [7:0] $end
+      $upscope $end
+      $var logic 8 , simple [7:0] $end
+     $upscope $end
+    $upscope $end
+   $upscope $end
+   $scope module sub_b $end
+    $var wire 1 ! clk $end
+    $var wire 32 - seed [31:0] $end
+    $attrbegin array unpacked bounds 4294967296 $end
+    $scope sv_array uarr $end
+     $attrbegin pack packed members 3 $end
+     $scope struct [1] $end
+      $attrbegin pack packed members 2 $end
+      $scope struct sub $end
+       $var logic 8 . x [7:0] $end
+       $var logic 8 / y [7:0] $end
+      $upscope $end
+      $attrbegin array packed bounds 4294967296 $end
+      $scope sv_array arr $end
+       $var logic 8 0 arr[1] [7:0] $end
+       $var logic 8 1 arr[0] [7:0] $end
+      $upscope $end
+      $var logic 8 2 simple [7:0] $end
+     $upscope $end
+     $attrbegin pack packed members 3 $end
+     $scope struct [0] $end
+      $attrbegin pack packed members 2 $end
+      $scope struct sub $end
+       $var logic 8 3 x [7:0] $end
+       $var logic 8 4 y [7:0] $end
+      $upscope $end
+      $attrbegin array packed bounds 4294967296 $end
+      $scope sv_array arr $end
+       $var logic 8 5 arr[1] [7:0] $end
+       $var logic 8 6 arr[0] [7:0] $end
+      $upscope $end
+      $var logic 8 7 simple [7:0] $end
+     $upscope $end
+    $upscope $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b00000000 7
+b00000000 6
+b00000000 5
+b00000000 4
+b00000000 3
+b00000000 2
+b00000000 1
+b00000000 0
+b00000000 /
+b00000000 .
+b00000000000000000000000001100100 -
+b00000000 ,
+b00000000 +
+b00000000 *
+b00000000 )
+b00000000 (
+b00000000 '
+b00000000 &
+b00000000 %
+b00000000 $
+b00000000 #
+b00000000000000000000000000000000 "
+0!
+$end
+#10
+1!
+b00000000000000000000000000000001 "
+b11111111 #
+b11111111 $
+b11111111 %
+b11111111 '
+b00000001 +
+b00000000000000000000000001100101 -
+b10011011 .
+b11111111 /
+b10011011 0
+b10011100 1
+b10011011 2
+b01100100 3
+b01100100 5
+b01100101 6
+b01100100 7
+#15
+0!
+#20
+1!
+b01100101 7
+b01100110 6
+b01100101 5
+b01100101 3
+b10011010 2
+b10011011 1
+b10011010 0
+b10011010 .
+b00000000000000000000000001100110 -
+b00000010 +
+b11111110 '
+b11111110 %
+b11111110 #
+b00000000000000000000000000000010 "
+b11111111 &
+b00000001 (
+b00000001 *
+b00000001 ,
+#25
+0!
+#30
+1!
+b00000010 ,
+b00000010 *
+b00000010 (
+b11111110 &
+b00000000000000000000000000000011 "
+b11111101 #
+b11111101 %
+b11111101 '
+b00000011 +
+b00000000000000000000000001100111 -
+b10011001 .
+b10011001 0
+b10011010 1
+b10011001 2
+b01100110 3
+b01100110 5
+b01100111 6
+b01100110 7
+#35
+0!
+#40
+1!
+b01100111 7
+b01101000 6
+b01100111 5
+b01100111 3
+b10011000 2
+b10011001 1
+b10011000 0
+b10011000 .
+b00000000000000000000000001101000 -
+b00000100 +
+b11111100 '
+b11111100 %
+b11111100 #
+b00000000000000000000000000000100 "
+b11111101 &
+b00000011 (
+b00000011 *
+b00000011 ,
+#44
diff --git a/test_regress/t/t_trace_struct_array_multi_inst_sc_fst.py b/test_regress/t/t_trace_struct_array_multi_inst_sc_fst.py
new file mode 100755
index 000000000..7e778d937
--- /dev/null
+++ b/test_regress/t/t_trace_struct_array_multi_inst_sc_fst.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_struct_array_multi_inst_common
+
+test.scenarios('vlt_all')
+
+trace_struct_array_multi_inst_common.run(test)
diff --git a/test_regress/t/t_trace_struct_array_multi_inst_sc_vcd.out b/test_regress/t/t_trace_struct_array_multi_inst_sc_vcd.out
new file mode 100644
index 000000000..30c2d30d9
--- /dev/null
+++ b/test_regress/t/t_trace_struct_array_multi_inst_sc_vcd.out
@@ -0,0 +1,164 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module top $end
+  $scope module t $end
+   $var wire 1 8 clk $end
+   $var wire 32 " cnt [31:0] $end
+   $scope module sub_a $end
+    $var wire 1 8 clk $end
+    $var wire 32 " seed [31:0] $end
+    $scope module uarr[1] $end
+     $scope module sub $end
+      $var wire 8 # x [7:0] $end
+      $var wire 8 $ y [7:0] $end
+     $upscope $end
+     $var wire 8 % arr[1] [7:0] $end
+     $var wire 8 & arr[0] [7:0] $end
+     $var wire 8 ' simple [7:0] $end
+    $upscope $end
+    $scope module uarr[0] $end
+     $scope module sub $end
+      $var wire 8 ( x [7:0] $end
+      $var wire 8 ) y [7:0] $end
+     $upscope $end
+     $var wire 8 * arr[1] [7:0] $end
+     $var wire 8 + arr[0] [7:0] $end
+     $var wire 8 , simple [7:0] $end
+    $upscope $end
+   $upscope $end
+   $scope module sub_b $end
+    $var wire 1 8 clk $end
+    $var wire 32 - seed [31:0] $end
+    $scope module uarr[1] $end
+     $scope module sub $end
+      $var wire 8 . x [7:0] $end
+      $var wire 8 / y [7:0] $end
+     $upscope $end
+     $var wire 8 0 arr[1] [7:0] $end
+     $var wire 8 1 arr[0] [7:0] $end
+     $var wire 8 2 simple [7:0] $end
+    $upscope $end
+    $scope module uarr[0] $end
+     $scope module sub $end
+      $var wire 8 3 x [7:0] $end
+      $var wire 8 4 y [7:0] $end
+     $upscope $end
+     $var wire 8 5 arr[1] [7:0] $end
+     $var wire 8 6 arr[0] [7:0] $end
+     $var wire 8 7 simple [7:0] $end
+    $upscope $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 "
+b00000000 #
+b00000000 $
+b00000000 %
+b00000000 &
+b00000000 '
+b00000000 (
+b00000000 )
+b00000000 *
+b00000000 +
+b00000000 ,
+b00000000000000000000000001100100 -
+b00000000 .
+b00000000 /
+b00000000 0
+b00000000 1
+b00000000 2
+b00000000 3
+b00000000 4
+b00000000 5
+b00000000 6
+b00000000 7
+08
+#10
+b00000000000000000000000000000001 "
+b11111111 #
+b11111111 $
+b11111111 %
+b11111111 '
+b00000001 +
+b00000000000000000000000001100101 -
+b10011011 .
+b11111111 /
+b10011011 0
+b10011100 1
+b10011011 2
+b01100100 3
+b01100100 5
+b01100101 6
+b01100100 7
+18
+#15
+08
+#20
+b00000000000000000000000000000010 "
+b11111110 #
+b11111110 %
+b11111111 &
+b11111110 '
+b00000001 (
+b00000001 *
+b00000010 +
+b00000001 ,
+b00000000000000000000000001100110 -
+b10011010 .
+b10011010 0
+b10011011 1
+b10011010 2
+b01100101 3
+b01100101 5
+b01100110 6
+b01100101 7
+18
+#25
+08
+#30
+b00000000000000000000000000000011 "
+b11111101 #
+b11111101 %
+b11111110 &
+b11111101 '
+b00000010 (
+b00000010 *
+b00000011 +
+b00000010 ,
+b00000000000000000000000001100111 -
+b10011001 .
+b10011001 0
+b10011010 1
+b10011001 2
+b01100110 3
+b01100110 5
+b01100111 6
+b01100110 7
+18
+#35
+08
+#40
+b00000000000000000000000000000100 "
+b11111100 #
+b11111100 %
+b11111101 &
+b11111100 '
+b00000011 (
+b00000011 *
+b00000100 +
+b00000011 ,
+b00000000000000000000000001101000 -
+b10011000 .
+b10011000 0
+b10011001 1
+b10011000 2
+b01100111 3
+b01100111 5
+b01101000 6
+b01100111 7
+18
+#44
diff --git a/test_regress/t/t_trace_struct_array_multi_inst_sc_vcd.py b/test_regress/t/t_trace_struct_array_multi_inst_sc_vcd.py
new file mode 100755
index 000000000..7e778d937
--- /dev/null
+++ b/test_regress/t/t_trace_struct_array_multi_inst_sc_vcd.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_struct_array_multi_inst_common
+
+test.scenarios('vlt_all')
+
+trace_struct_array_multi_inst_common.run(test)
diff --git a/test_regress/t/t_trace_timescale.out b/test_regress/t/t_trace_timescale.out
index 02f18ab14..718a78759 100644
--- a/test_regress/t/t_trace_timescale.out
+++ b/test_regress/t/t_trace_timescale.out
@@ -1,69 +1,68 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ms $end
-
  $scope module top $end
-  $var wire 1 # clk $end
+  $var wire 1 " clk $end
   $scope module t $end
-   $var wire 1 # clk $end
-   $var wire 32 $ cyc [31:0] $end
+   $var wire 1 " clk $end
+   $var wire 32 # cyc [31:0] $end
   $upscope $end
  $upscope $end
 $enddefinitions $end
 
 
 #0
-0#
-b00000000000000000000000000000000 $
+0"
+b00000000000000000000000000000000 #
 #10
-1#
-b00000000000000000000000000000001 $
+1"
+b00000000000000000000000000000001 #
 #15
-0#
+0"
 #20
-1#
-b00000000000000000000000000000010 $
+1"
+b00000000000000000000000000000010 #
 #25
-0#
+0"
 #30
-1#
-b00000000000000000000000000000011 $
+1"
+b00000000000000000000000000000011 #
 #35
-0#
+0"
 #40
-1#
-b00000000000000000000000000000100 $
+1"
+b00000000000000000000000000000100 #
 #45
-0#
+0"
 #50
-1#
-b00000000000000000000000000000101 $
+1"
+b00000000000000000000000000000101 #
 #55
-0#
+0"
 #60
-1#
-b00000000000000000000000000000110 $
+1"
+b00000000000000000000000000000110 #
 #65
-0#
+0"
 #70
-1#
-b00000000000000000000000000000111 $
+1"
+b00000000000000000000000000000111 #
 #75
-0#
+0"
 #80
-1#
-b00000000000000000000000000001000 $
+1"
+b00000000000000000000000000001000 #
 #85
-0#
+0"
 #90
-1#
-b00000000000000000000000000001001 $
+1"
+b00000000000000000000000000001001 #
 #95
-0#
+0"
 #100
-1#
-b00000000000000000000000000001010 $
+1"
+b00000000000000000000000000001010 #
 #105
-0#
+0"
 #110
-1#
-b00000000000000000000000000001011 $
+1"
+b00000000000000000000000000001011 #
diff --git a/test_regress/t/t_trace_timing1.out b/test_regress/t/t_trace_timing1.out
index ac703d8cc..80c6d301a 100644
--- a/test_regress/t/t_trace_timing1.out
+++ b/test_regress/t/t_trace_timing1.out
@@ -1,23 +1,23 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module t $end
-  $var wire 32 % CLOCK_CYCLE [31:0] $end
-  $var wire 1 # rst $end
-  $var wire 1 $ clk $end
+  $var wire 32 $ CLOCK_CYCLE [31:0] $end
+  $var wire 1 " rst $end
+  $var wire 1 # clk $end
  $upscope $end
 $enddefinitions $end
 
 
 #0
-1#
-0$
-b00000000000000000000000000001010 %
-#5
-1$
-#10
+1"
+0#
+b00000000000000000000000000001010 $
+#5
+1#
+#10
+0"
 0#
-0$
 #15
-1$
+1#
 #20
-0$
+0#
diff --git a/test_regress/t/t_trace_timing_fst.out b/test_regress/t/t_trace_timing_fst.out
index e9a0ffb19..8c873ef80 100644
--- a/test_regress/t/t_trace_timing_fst.out
+++ b/test_regress/t/t_trace_timing_fst.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 14 09:17:24 2026
+Tue Apr 14 15:20:45 2026
 
 $end
 $version
diff --git a/test_regress/t/t_trace_timing_vcd.out b/test_regress/t/t_trace_timing_vcd.out
index 206cd8995..6f985e536 100644
--- a/test_regress/t/t_trace_timing_vcd.out
+++ b/test_regress/t/t_trace_timing_vcd.out
@@ -1,85 +1,85 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module t $end
-  $var wire 32 * CLK_PERIOD [31:0] $end
-  $var wire 32 + CLK_HALF_PERIOD [31:0] $end
-  $var wire 1 # rst $end
-  $var wire 1 ( clk $end
-  $var wire 1 $ a $end
-  $var wire 1 ) b $end
-  $var wire 1 % c $end
-  $var wire 1 & d $end
-  $var event 1 ' ev $end
+  $var wire 32 ) CLK_PERIOD [31:0] $end
+  $var wire 32 * CLK_HALF_PERIOD [31:0] $end
+  $var wire 1 " rst $end
+  $var wire 1 ' clk $end
+  $var wire 1 # a $end
+  $var wire 1 ( b $end
+  $var wire 1 $ c $end
+  $var wire 1 % d $end
+  $var event 1 & ev $end
  $upscope $end
 $enddefinitions $end
 
 
 #0
-1#
-0$
-1%
-0&
-1'
-0(
-1)
-b00000000000000000000000000001010 *
-b00000000000000000000000000000101 +
+1"
+0#
+1$
+0%
+1&
+0'
+1(
+b00000000000000000000000000001010 )
+b00000000000000000000000000000101 *
 #5
-1(
+1'
 #10
-0%
-1'
-0(
+0$
+1&
+0'
 #15
-1(
+1'
 #20
-1%
-1'
-0(
+1$
+1&
+0'
 #25
-1(
+1'
 #30
-0%
-1'
-0(
+0$
+1&
+0'
 #35
-1(
+1'
 #40
-1%
-1'
-0(
+1$
+1&
+0'
 #45
-1(
+1'
 #50
-0%
-1'
-0(
+0$
+1&
+0'
 #55
-1(
+1'
 #60
-1%
-1'
-0(
+1$
+1&
+0'
 #65
-1(
+1'
 #70
-0%
-1'
-0(
+0$
+1&
+0'
 #75
-1(
+1'
 #80
-1%
-1'
-0(
+1$
+1&
+0'
 #85
-1(
-#90
-0%
 1'
-0(
+#90
+0$
+1&
+0'
 #95
-1(
+1'
 #100
+0'
 0(
-0)
diff --git a/test_regress/t/t_trace_two_dump_cc_fst.out b/test_regress/t/t_trace_two_dump_cc_fst.out
index d968203ea..f4a7c4944 100644
--- a/test_regress/t/t_trace_two_dump_cc_fst.out
+++ b/test_regress/t/t_trace_two_dump_cc_fst.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 14 09:16:59 2026
+Tue Apr 14 15:20:45 2026
 
 $end
 $version
diff --git a/test_regress/t/t_trace_two_dump_cc_vcd.out b/test_regress/t/t_trace_two_dump_cc_vcd.out
index d65b1e2e9..b390ca2ef 100644
--- a/test_regress/t/t_trace_two_dump_cc_vcd.out
+++ b/test_regress/t/t_trace_two_dump_cc_vcd.out
@@ -1,25 +1,25 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module topa $end
-  $var wire 1 # clk $end
+  $var wire 1 " clk $end
   $scope module t $end
-   $var wire 1 # clk $end
-   $var wire 32 $ cyc [31:0] $end
-   $var wire 32 % c_trace_on [31:0] $end
+   $var wire 1 " clk $end
+   $var wire 32 # cyc [31:0] $end
+   $var wire 32 $ c_trace_on [31:0] $end
    $scope module sub $end
-    $var wire 32 & inside_sub_a [31:0] $end
+    $var wire 32 % inside_sub_a [31:0] $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module topb $end
-  $var wire 1 ( clk $end
+  $var wire 1 & clk $end
   $scope module t $end
-   $var wire 1 ( clk $end
-   $var wire 32 + cyc [31:0] $end
-   $var wire 32 , c_trace_on [31:0] $end
-   $var real 64 ) r $end
+   $var wire 1 & clk $end
+   $var wire 32 ) cyc [31:0] $end
+   $var wire 32 * c_trace_on [31:0] $end
+   $var real 64 ' r $end
    $scope module sub $end
-    $var wire 32 - inside_sub_a [31:0] $end
+    $var wire 32 + inside_sub_a [31:0] $end
    $upscope $end
   $upscope $end
  $upscope $end
@@ -27,102 +27,102 @@ $enddefinitions $end
 
 
 #10
-1#
-b00000000000000000000000000000001 $
-b00000000000000000000000000000000 %
-1(
-r0 )
-b00000000000000000000000000000001 &
-b00000000000000000000000000000001 +
-b00000000000000000000000000000000 ,
-b00000000000000000000000000000010 -
+1"
+b00000000000000000000000000000001 #
+b00000000000000000000000000000000 $
+1&
+r0 '
+b00000000000000000000000000000001 %
+b00000000000000000000000000000001 )
+b00000000000000000000000000000000 *
+b00000000000000000000000000000010 +
 #15
-0#
-0(
+0"
+0&
 #20
-1#
-b00000000000000000000000000000010 $
-b00000000000000000000000000000011 %
-1(
-r0.1 )
-#25
-0#
-0(
-#30
-1#
+1"
+b00000000000000000000000000000010 #
 b00000000000000000000000000000011 $
-b00000000000000000000000000000100 %
-1(
-r0.2 )
-#35
-0#
-0(
-#40
-1#
+1&
+r0.1 '
+#25
+0"
+0&
+#30
+1"
+b00000000000000000000000000000011 #
 b00000000000000000000000000000100 $
-b00000000000000000000000000000101 %
-1(
-r0.3 )
-#45
-0#
-0(
-#50
-1#
+1&
+r0.2 '
+#35
+0"
+0&
+#40
+1"
+b00000000000000000000000000000100 #
 b00000000000000000000000000000101 $
-b00000000000000000000000000000110 %
-1(
-r0.4 )
-#55
-0#
-0(
-#60
-1#
+1&
+r0.3 '
+#45
+0"
+0&
+#50
+1"
+b00000000000000000000000000000101 #
 b00000000000000000000000000000110 $
-b00000000000000000000000000000111 %
-1(
-r0.5 )
-#65
-0#
-0(
-#70
-1#
+1&
+r0.4 '
+#55
+0"
+0&
+#60
+1"
+b00000000000000000000000000000110 #
 b00000000000000000000000000000111 $
-b00000000000000000000000000001000 %
-1(
-r0.6 )
-#75
-0#
-0(
-#80
-1#
+1&
+r0.5 '
+#65
+0"
+0&
+#70
+1"
+b00000000000000000000000000000111 #
 b00000000000000000000000000001000 $
-b00000000000000000000000000001001 %
-1(
-r0.7 )
-#85
-0#
-0(
-#90
-1#
+1&
+r0.6 '
+#75
+0"
+0&
+#80
+1"
+b00000000000000000000000000001000 #
 b00000000000000000000000000001001 $
-b00000000000000000000000000001010 %
-1(
-r0.7999999999999999 )
-#95
-0#
-0(
-#100
-1#
+1&
+r0.7 '
+#85
+0"
+0&
+#90
+1"
+b00000000000000000000000000001001 #
 b00000000000000000000000000001010 $
-b00000000000000000000000000001011 %
-1(
-r0.8999999999999999 )
-#105
-0#
-0(
-#110
-1#
+1&
+r0.7999999999999999 '
+#95
+0"
+0&
+#100
+1"
+b00000000000000000000000000001010 #
 b00000000000000000000000000001011 $
-b00000000000000000000000000001100 %
-1(
-r0.9999999999999999 )
+1&
+r0.8999999999999999 '
+#105
+0"
+0&
+#110
+1"
+b00000000000000000000000000001011 #
+b00000000000000000000000000001100 $
+1&
+r0.9999999999999999 '
diff --git a/test_regress/t/t_trace_two_dump_sc_vcd.out b/test_regress/t/t_trace_two_dump_sc_vcd.out
index 20a892897..f836f2795 100644
--- a/test_regress/t/t_trace_two_dump_sc_vcd.out
+++ b/test_regress/t/t_trace_two_dump_sc_vcd.out
@@ -2,22 +2,22 @@ $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module topa $end
   $scope module t $end
-   $var wire 1 # clk $end
-   $var wire 32 $ cyc [31:0] $end
-   $var wire 32 % c_trace_on [31:0] $end
+   $var wire 1 " clk $end
+   $var wire 32 # cyc [31:0] $end
+   $var wire 32 $ c_trace_on [31:0] $end
    $scope module sub $end
-    $var wire 32 & inside_sub_a [31:0] $end
+    $var wire 32 % inside_sub_a [31:0] $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module topb $end
   $scope module t $end
-   $var wire 1 ( clk $end
-   $var wire 32 + cyc [31:0] $end
-   $var wire 32 , c_trace_on [31:0] $end
-   $var real 64 ) r $end
+   $var wire 1 & clk $end
+   $var wire 32 ) cyc [31:0] $end
+   $var wire 32 * c_trace_on [31:0] $end
+   $var real 64 ' r $end
    $scope module sub $end
-    $var wire 32 - inside_sub_a [31:0] $end
+    $var wire 32 + inside_sub_a [31:0] $end
    $upscope $end
   $upscope $end
  $upscope $end
@@ -25,99 +25,99 @@ $enddefinitions $end
 
 
 #0
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 b00000000000000000000000000001011 $
-b00000000000000000000000000001100 %
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+#100000
+1"
+b00000000000000000000000000001011 #
+b00000000000000000000000000001100 $
+1&
+r0.9999999999999999 '
diff --git a/test_regress/t/t_trace_two_hdr_cc_fst.out b/test_regress/t/t_trace_two_hdr_cc_fst.out
index cebd15197..0e9ace064 100644
--- a/test_regress/t/t_trace_two_hdr_cc_fst.out
+++ b/test_regress/t/t_trace_two_hdr_cc_fst.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 14 09:17:27 2026
+Tue Apr 14 15:20:45 2026
 
 $end
 $version
diff --git a/test_regress/t/t_trace_two_hdr_cc_vcd.out b/test_regress/t/t_trace_two_hdr_cc_vcd.out
index bbff00b3e..0f6ea0aa2 100644
--- a/test_regress/t/t_trace_two_hdr_cc_vcd.out
+++ b/test_regress/t/t_trace_two_hdr_cc_vcd.out
@@ -1,26 +1,25 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
-
  $scope module topa $end
-  $var wire 1 # clk $end
+  $var wire 1 " clk $end
   $scope module t $end
-   $var wire 1 # clk $end
-   $var wire 32 $ cyc [31:0] $end
-   $var wire 32 % c_trace_on [31:0] $end
+   $var wire 1 " clk $end
+   $var wire 32 # cyc [31:0] $end
+   $var wire 32 $ c_trace_on [31:0] $end
    $scope module sub $end
-    $var wire 32 & inside_sub_a [31:0] $end
+    $var wire 32 % inside_sub_a [31:0] $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module topb $end
-  $var wire 1 ( clk $end
+  $var wire 1 & clk $end
   $scope module t $end
-   $var wire 1 ( clk $end
-   $var wire 32 + cyc [31:0] $end
-   $var wire 32 , c_trace_on [31:0] $end
-   $var real 64 ) r $end
+   $var wire 1 & clk $end
+   $var wire 32 ) cyc [31:0] $end
+   $var wire 32 * c_trace_on [31:0] $end
+   $var real 64 ' r $end
    $scope module sub $end
-    $var wire 32 - inside_sub_a [31:0] $end
+    $var wire 32 + inside_sub_a [31:0] $end
    $upscope $end
   $upscope $end
  $upscope $end
@@ -28,99 +27,99 @@ $enddefinitions $end
 
 
 #0
-0#
-b00000000000000000000000000000001 $
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-r0 )
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-b00000000000000000000000000000000 ,
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 #10
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 b00000000000000000000000000001011 $
-b00000000000000000000000000001100 %
-1(
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+0&
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+1"
+b00000000000000000000000000001011 #
+b00000000000000000000000000001100 $
+1&
+r0.9999999999999999 '
diff --git a/test_regress/t/t_trace_two_hdr_sc_vcd.out b/test_regress/t/t_trace_two_hdr_sc_vcd.out
index 43f14b6ce..f836f2795 100644
--- a/test_regress/t/t_trace_two_hdr_sc_vcd.out
+++ b/test_regress/t/t_trace_two_hdr_sc_vcd.out
@@ -1,24 +1,23 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
-
  $scope module topa $end
   $scope module t $end
-   $var wire 1 # clk $end
-   $var wire 32 $ cyc [31:0] $end
-   $var wire 32 % c_trace_on [31:0] $end
+   $var wire 1 " clk $end
+   $var wire 32 # cyc [31:0] $end
+   $var wire 32 $ c_trace_on [31:0] $end
    $scope module sub $end
-    $var wire 32 & inside_sub_a [31:0] $end
+    $var wire 32 % inside_sub_a [31:0] $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module topb $end
   $scope module t $end
-   $var wire 1 ( clk $end
-   $var wire 32 + cyc [31:0] $end
-   $var wire 32 , c_trace_on [31:0] $end
-   $var real 64 ) r $end
+   $var wire 1 & clk $end
+   $var wire 32 ) cyc [31:0] $end
+   $var wire 32 * c_trace_on [31:0] $end
+   $var real 64 ' r $end
    $scope module sub $end
-    $var wire 32 - inside_sub_a [31:0] $end
+    $var wire 32 + inside_sub_a [31:0] $end
    $upscope $end
   $upscope $end
  $upscope $end
@@ -26,99 +25,99 @@ $enddefinitions $end
 
 
 #0
-0#
-b00000000000000000000000000000001 $
-b00000000000000000000000000000000 %
-0(
-r0 )
-b00000000000000000000000000000001 &
-b00000000000000000000000000000001 +
-b00000000000000000000000000000000 ,
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 #10000
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 b00000000000000000000000000000011 $
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 b00000000000000000000000000001000 $
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 b00000000000000000000000000001010 $
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 b00000000000000000000000000001011 $
-b00000000000000000000000000001100 %
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+0"
+0&
+#100000
+1"
+b00000000000000000000000000001011 #
+b00000000000000000000000000001100 $
+1&
+r0.9999999999999999 '
diff --git a/test_regress/t/t_trace_two_port_cc_fst.out b/test_regress/t/t_trace_two_port_cc_fst.out
index 1d4087f72..f4a7c4944 100644
--- a/test_regress/t/t_trace_two_port_cc_fst.out
+++ b/test_regress/t/t_trace_two_port_cc_fst.out
@@ -1,5 +1,5 @@
 $date
-Sat Mar 14 09:16:43 2026
+Tue Apr 14 15:20:45 2026
 
 $end
 $version
diff --git a/test_regress/t/t_trace_two_port_cc_vcd.out b/test_regress/t/t_trace_two_port_cc_vcd.out
index d65b1e2e9..b390ca2ef 100644
--- a/test_regress/t/t_trace_two_port_cc_vcd.out
+++ b/test_regress/t/t_trace_two_port_cc_vcd.out
@@ -1,25 +1,25 @@
 $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module topa $end
-  $var wire 1 # clk $end
+  $var wire 1 " clk $end
   $scope module t $end
-   $var wire 1 # clk $end
-   $var wire 32 $ cyc [31:0] $end
-   $var wire 32 % c_trace_on [31:0] $end
+   $var wire 1 " clk $end
+   $var wire 32 # cyc [31:0] $end
+   $var wire 32 $ c_trace_on [31:0] $end
    $scope module sub $end
-    $var wire 32 & inside_sub_a [31:0] $end
+    $var wire 32 % inside_sub_a [31:0] $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module topb $end
-  $var wire 1 ( clk $end
+  $var wire 1 & clk $end
   $scope module t $end
-   $var wire 1 ( clk $end
-   $var wire 32 + cyc [31:0] $end
-   $var wire 32 , c_trace_on [31:0] $end
-   $var real 64 ) r $end
+   $var wire 1 & clk $end
+   $var wire 32 ) cyc [31:0] $end
+   $var wire 32 * c_trace_on [31:0] $end
+   $var real 64 ' r $end
    $scope module sub $end
-    $var wire 32 - inside_sub_a [31:0] $end
+    $var wire 32 + inside_sub_a [31:0] $end
    $upscope $end
   $upscope $end
  $upscope $end
@@ -27,102 +27,102 @@ $enddefinitions $end
 
 
 #10
-1#
-b00000000000000000000000000000001 $
-b00000000000000000000000000000000 %
-1(
-r0 )
-b00000000000000000000000000000001 &
-b00000000000000000000000000000001 +
-b00000000000000000000000000000000 ,
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+1"
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+b00000000000000000000000000000001 )
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 #15
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 b00000000000000000000000000001010 $
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 b00000000000000000000000000001011 $
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+1"
+b00000000000000000000000000001011 #
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+1&
+r0.9999999999999999 '
diff --git a/test_regress/t/t_trace_two_port_sc_vcd.out b/test_regress/t/t_trace_two_port_sc_vcd.out
index 20a892897..f836f2795 100644
--- a/test_regress/t/t_trace_two_port_sc_vcd.out
+++ b/test_regress/t/t_trace_two_port_sc_vcd.out
@@ -2,22 +2,22 @@ $version Generated by VerilatedVcd $end
 $timescale 1ps $end
  $scope module topa $end
   $scope module t $end
-   $var wire 1 # clk $end
-   $var wire 32 $ cyc [31:0] $end
-   $var wire 32 % c_trace_on [31:0] $end
+   $var wire 1 " clk $end
+   $var wire 32 # cyc [31:0] $end
+   $var wire 32 $ c_trace_on [31:0] $end
    $scope module sub $end
-    $var wire 32 & inside_sub_a [31:0] $end
+    $var wire 32 % inside_sub_a [31:0] $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module topb $end
   $scope module t $end
-   $var wire 1 ( clk $end
-   $var wire 32 + cyc [31:0] $end
-   $var wire 32 , c_trace_on [31:0] $end
-   $var real 64 ) r $end
+   $var wire 1 & clk $end
+   $var wire 32 ) cyc [31:0] $end
+   $var wire 32 * c_trace_on [31:0] $end
+   $var real 64 ' r $end
    $scope module sub $end
-    $var wire 32 - inside_sub_a [31:0] $end
+    $var wire 32 + inside_sub_a [31:0] $end
    $upscope $end
   $upscope $end
  $upscope $end
@@ -25,99 +25,99 @@ $enddefinitions $end
 
 
 #0
-0#
-b00000000000000000000000000000001 $
-b00000000000000000000000000000000 %
-0(
-r0 )
-b00000000000000000000000000000001 &
-b00000000000000000000000000000001 +
-b00000000000000000000000000000000 ,
-b00000000000000000000000000000010 -
+0"
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+0&
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 #10000
-1#
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-#15000
-0#
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-1#
+1"
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 b00000000000000000000000000000011 $
-b00000000000000000000000000000100 %
-1(
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+1"
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 b00000000000000000000000000000100 $
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-1(
-r0.3 )
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+1"
+b00000000000000000000000000000100 #
 b00000000000000000000000000000101 $
-b00000000000000000000000000000110 %
-1(
-r0.4 )
-#45000
-0#
-0(
-#50000
-1#
+1&
+r0.3 '
+#35000
+0"
+0&
+#40000
+1"
+b00000000000000000000000000000101 #
 b00000000000000000000000000000110 $
-b00000000000000000000000000000111 %
-1(
-r0.5 )
-#55000
-0#
-0(
-#60000
-1#
+1&
+r0.4 '
+#45000
+0"
+0&
+#50000
+1"
+b00000000000000000000000000000110 #
 b00000000000000000000000000000111 $
-b00000000000000000000000000001000 %
-1(
-r0.6 )
-#65000
-0#
-0(
-#70000
-1#
+1&
+r0.5 '
+#55000
+0"
+0&
+#60000
+1"
+b00000000000000000000000000000111 #
 b00000000000000000000000000001000 $
-b00000000000000000000000000001001 %
-1(
-r0.7 )
-#75000
-0#
-0(
-#80000
-1#
+1&
+r0.6 '
+#65000
+0"
+0&
+#70000
+1"
+b00000000000000000000000000001000 #
 b00000000000000000000000000001001 $
-b00000000000000000000000000001010 %
-1(
-r0.7999999999999999 )
-#85000
-0#
-0(
-#90000
-1#
+1&
+r0.7 '
+#75000
+0"
+0&
+#80000
+1"
+b00000000000000000000000000001001 #
 b00000000000000000000000000001010 $
-b00000000000000000000000000001011 %
-1(
-r0.8999999999999999 )
-#95000
-0#
-0(
-#100000
-1#
+1&
+r0.7999999999999999 '
+#85000
+0"
+0&
+#90000
+1"
+b00000000000000000000000000001010 #
 b00000000000000000000000000001011 $
-b00000000000000000000000000001100 %
-1(
-r0.9999999999999999 )
+1&
+r0.8999999999999999 '
+#95000
+0"
+0&
+#100000
+1"
+b00000000000000000000000000001011 #
+b00000000000000000000000000001100 $
+1&
+r0.9999999999999999 '
diff --git a/test_regress/t/t_trace_type_alias.py b/test_regress/t/t_trace_type_alias.py
new file mode 100755
index 000000000..29345f414
--- /dev/null
+++ b/test_regress/t/t_trace_type_alias.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2024 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios("vlt_all")
+
+test.compile(v_flags2=["--trace-vcd --trace-structs"])
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_trace_type_alias.v b/test_regress/t/t_trace_type_alias.v
new file mode 100644
index 000000000..a139451df
--- /dev/null
+++ b/test_regress/t/t_trace_type_alias.v
@@ -0,0 +1,46 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Wilson Snyder
+// SPDX-License-Identifier: CC0-1.0
+
+module Sub #(
+    parameter int data_width
+)(
+    input clk,
+    output logic [data_width-1:0]       read_data
+);
+    logic [0:0][data_width-1:0] read_data_2d;
+    always_ff @(posedge clk) read_data_2d <= $random;
+    always_comb read_data = read_data_2d[0];
+endmodule
+
+module t ();
+    typedef struct packed {
+        logic [7:0] field_a;
+        logic [7:0] field_b;
+        logic [7:0] field_c;
+        logic field_d;
+        logic field_e;
+        logic field_f;
+        logic field_g;
+        logic field_h;
+        logic field_i;
+        logic field_j;
+        logic field_k;
+    } struct_t;
+    struct_t the_struct;
+    logic clk;
+
+    Sub #(
+        .data_width   ($bits(struct_t))
+    ) the_sub(
+        .clk,
+        .read_data (the_struct)
+    );
+
+    initial begin
+        $write("*-* All Finished *-*\n");
+        $finish;
+    end
+endmodule
diff --git a/test_regress/t/t_trace_type_dupes.v b/test_regress/t/t_trace_type_dupes.v
new file mode 100644
index 000000000..7cb009403
--- /dev/null
+++ b/test_regress/t/t_trace_type_dupes.v
@@ -0,0 +1,186 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Wilson Snyder
+// SPDX-License-Identifier: CC0-1.0
+
+`ifndef LAST_CYC
+`define LAST_CYC 9
+`endif
+
+`ifndef NUM_SUBS
+`define NUM_SUBS 4
+`endif
+
+
+module t (/*AUTOARG*/
+          // Inputs
+          clk
+          );
+  input clk;
+
+  int cyc;
+  logic [`NUM_SUBS - 1:0] x;
+  initial cyc = 0;
+
+  always_ff @(posedge clk) begin
+    cyc <= cyc + 1;
+    if (cyc == `LAST_CYC) begin
+      if (~|x) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+    end
+  end
+
+  for (genvar i = 0; i < `NUM_SUBS; i++) begin : gen_loop
+    int loop_cyc;
+    always_comb loop_cyc = cyc + i;
+    sub #(
+      .data_t (pkg::some_struct_t)
+    )
+    the_sub (
+      .a (loop_cyc[i%32]),
+      .b (loop_cyc[(i+1)%32]),
+      .x (x[i]),
+      .out_2d_unpacked (),
+      .data (),
+      .cyc (loop_cyc),
+      .clk
+    );
+  end
+
+  intf
+  the_intf_a (.*),
+  the_intf_b (.*);
+
+  for (genvar m = 0; m < 4; m++) begin : gen_intf_loop
+    always_comb begin
+      the_intf_a.data[m] = cyc[7:0] + m + 7'd1;
+      the_intf_b.data[m] = cyc[7:0] + m + 7'd2;
+    end
+  end
+
+endmodule
+
+package pkg;
+  typedef struct packed {
+    logic field_a;
+    logic [5:0] field_b;
+    logic [9:0] field_c;
+  } some_sub_struct_t;
+
+  typedef struct packed {
+    logic foo;
+    logic [3:0] [31:0] bar;
+    logic [15:0] baz;
+    logic [127:0] qux;
+    some_sub_struct_t sub_struct;
+  } some_struct_t;
+
+  parameter some_sub_struct_t SUB_ONES = '1;
+  parameter some_sub_struct_t SUB_ZEROS = '0;
+endpackage
+
+module sub #(
+  parameter type data_t = bit
+)(
+  input a,
+  input b,
+  output logic x,
+  output out_2d_unpacked [3][4],
+  output data_t data,
+  input int cyc,
+  input clk
+);
+  pkg::some_struct_t the_struct;
+  pkg::some_struct_t the_structs [3:0];
+  pkg::some_struct_t [2:0] the_packed_structs;
+
+  typedef struct packed {
+    logic abc;
+    logic def;
+    logic xyz;
+  } some_struct_t;
+  some_struct_t the_local_struct;
+  localparam some_struct_t const_struct = 3'b101;
+  typedef some_struct_t typedefed_struct_t;
+  typedefed_struct_t the_typedefed_struct;
+
+  typedef struct {
+    logic field_a;
+    logic field_b;
+    logic field_c;
+  } some_unpacked_struct_t;
+  some_unpacked_struct_t the_local_unpacked_struct;
+
+  typedef union packed {
+    struct packed {
+      logic [7:0] field_0;
+    } union_a;
+    struct packed {
+      logic [3:0] field_1;
+      logic [3:0] field_2;
+    } union_b;
+    struct packed {
+      logic [1:0] field_3;
+      logic [5:0] field_4;
+    } union_c;
+  } some_union_t;
+  some_union_t the_local_union;
+
+  typedef logic [1:0] [31:0] logic_array_t;
+  typedef logic [1:0] [31:0] logic_array_2_t;
+  logic_array_t the_logic_array;
+  logic_array_2_t the_other_logic_array;
+  logic [15:0] the_unpacked_array [5];
+  logic the_2d_unpacked [3][4];
+  string the_string_array [3:0];
+
+  typedef logic [3:0] four_bit_t;
+  typedef four_bit_t [1:0] two_fours_t;
+  localparam two_fours_t two_fours = 8'hab;
+  two_fours_t two_fours_var;
+
+  always_ff @(posedge clk) begin
+    x <= a ^ b;
+    the_struct <= '{
+      foo : cyc[0],
+      bar : '{cyc, cyc+1, cyc+2, cyc+3},
+      baz : cyc[15:0],
+      qux : 128'(cyc),
+      sub_struct : '{
+        field_a : cyc[0],
+        field_b : cyc[5:0],
+        field_c : cyc[9:0]
+      }
+    };
+    for (int i = 0; i < 4; i++) the_structs[i] <= {$bits(pkg::some_struct_t){cyc[i]}};
+    the_local_struct <= cyc[2:0];
+    the_typedefed_struct <= cyc[3:1];
+    the_local_unpacked_struct <= '{
+      field_a : cyc[0],
+      field_b : cyc[1],
+      field_c : cyc[2]
+    };
+    the_local_union <= cyc[7:0];
+    for (int i = 0; i < 2; i++) begin
+      the_logic_array[i] <= cyc + i;
+      the_other_logic_array[i] <= cyc + i + 123;
+    end
+    for (int i = 0; i < 5; i++) the_unpacked_array[i] <= cyc[15:0];
+    for (int i = 0; i < 3; i++)
+      for (int j = 0; j < 4; j++) begin
+        the_2d_unpacked [i][j] <= ~(cyc[i] ^ cyc[j]);
+        out_2d_unpacked [i][j] <= cyc[i] ^ cyc[j];
+      end
+  end
+
+  always_comb data = the_struct;
+endmodule
+
+interface intf
+  (input wire clk);
+  logic [3:0] [7:0] data;
+  int data_typed;
+  always_comb data_typed = data;
+endinterface
diff --git a/test_regress/t/t_trace_type_dupes_default_fst.out b/test_regress/t/t_trace_type_dupes_default_fst.out
new file mode 100644
index 000000000..b4e342c2d
--- /dev/null
+++ b/test_regress/t/t_trace_type_dupes_default_fst.out
@@ -0,0 +1,1676 @@
+$date
+Tue Mar 31 17:14:57 2026
+
+$end
+$version
+Generated by VerilatedFst
+$end
+$timescale
+1ps
+$end
+ $scope module top $end
+  $var wire 1 ! clk $end
+  $scope module pkg $end
+   $var parameter 17 " SUB_ONES [16:0] $end
+   $var parameter 17 # SUB_ZEROS [16:0] $end
+  $upscope $end
+  $scope module t $end
+   $var wire 1 ! clk $end
+   $var int 32 $ cyc [31:0] $end
+   $var logic 4 % x [3:0] $end
+   $scope module gen_loop[0] $end
+    $var int 32 $ loop_cyc [31:0] $end
+    $scope module the_sub $end
+     $var wire 1 & a $end
+     $var wire 1 ' b $end
+     $var wire 1 ( x $end
+     $attrbegin array unpacked bounds 2 $end
+     $scope sv_array out_2d_unpacked $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [0] $end
+       $var wire 1 ) out_2d_unpacked[0][0] $end
+       $var wire 1 * out_2d_unpacked[0][1] $end
+       $var wire 1 + out_2d_unpacked[0][2] $end
+       $var wire 1 , out_2d_unpacked[0][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [1] $end
+       $var wire 1 - out_2d_unpacked[1][0] $end
+       $var wire 1 . out_2d_unpacked[1][1] $end
+       $var wire 1 / out_2d_unpacked[1][2] $end
+       $var wire 1 0 out_2d_unpacked[1][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [2] $end
+       $var wire 1 1 out_2d_unpacked[2][0] $end
+       $var wire 1 2 out_2d_unpacked[2][1] $end
+       $var wire 1 3 out_2d_unpacked[2][2] $end
+       $var wire 1 4 out_2d_unpacked[2][3] $end
+      $upscope $end
+     $upscope $end
+     $var wire 290 5 data [289:0] $end
+     $var wire 32 $ cyc [31:0] $end
+     $var wire 1 ! clk $end
+     $var logic 290 5 the_struct [289:0] $end
+     $attrbegin array unpacked bounds 12884901888 $end
+     $scope sv_array the_structs $end
+      $var logic 290 6 the_structs[3] [289:0] $end
+      $var logic 290 7 the_structs[2] [289:0] $end
+      $var logic 290 8 the_structs[1] [289:0] $end
+      $var logic 290 9 the_structs[0] [289:0] $end
+     $upscope $end
+     $var logic 870 : the_packed_structs [869:0] $end
+     $var logic 3 ; the_local_struct [2:0] $end
+     $var parameter 3 < const_struct [2:0] $end
+     $var logic 3 = the_typedefed_struct [2:0] $end
+     $attrbegin pack unpacked members 3 $end
+     $scope struct the_local_unpacked_struct $end
+      $var logic 1 > field_a $end
+      $var logic 1 ? field_b $end
+      $var logic 1 @ field_c $end
+     $upscope $end
+     $var logic 8 A the_local_union [7:0] $end
+     $var logic 64 B the_logic_array [63:0] $end
+     $var logic 64 C the_other_logic_array [63:0] $end
+     $attrbegin array unpacked bounds 4 $end
+     $scope sv_array the_unpacked_array $end
+      $var logic 16 D the_unpacked_array[0] [15:0] $end
+      $var logic 16 E the_unpacked_array[1] [15:0] $end
+      $var logic 16 F the_unpacked_array[2] [15:0] $end
+      $var logic 16 G the_unpacked_array[3] [15:0] $end
+      $var logic 16 H the_unpacked_array[4] [15:0] $end
+     $upscope $end
+     $attrbegin array unpacked bounds 2 $end
+     $scope sv_array the_2d_unpacked $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [0] $end
+       $var logic 1 I the_2d_unpacked[0][0] $end
+       $var logic 1 J the_2d_unpacked[0][1] $end
+       $var logic 1 K the_2d_unpacked[0][2] $end
+       $var logic 1 L the_2d_unpacked[0][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [1] $end
+       $var logic 1 M the_2d_unpacked[1][0] $end
+       $var logic 1 N the_2d_unpacked[1][1] $end
+       $var logic 1 O the_2d_unpacked[1][2] $end
+       $var logic 1 P the_2d_unpacked[1][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [2] $end
+       $var logic 1 Q the_2d_unpacked[2][0] $end
+       $var logic 1 R the_2d_unpacked[2][1] $end
+       $var logic 1 S the_2d_unpacked[2][2] $end
+       $var logic 1 T the_2d_unpacked[2][3] $end
+      $upscope $end
+     $upscope $end
+     $var parameter 8 U two_fours [7:0] $end
+     $var logic 8 V two_fours_var [7:0] $end
+    $upscope $end
+   $upscope $end
+   $scope module gen_loop[1] $end
+    $var int 32 W loop_cyc [31:0] $end
+    $scope module the_sub $end
+     $var wire 1 X a $end
+     $var wire 1 Y b $end
+     $var wire 1 Z x $end
+     $attrbegin array unpacked bounds 2 $end
+     $scope sv_array out_2d_unpacked $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [0] $end
+       $var wire 1 [ out_2d_unpacked[0][0] $end
+       $var wire 1 \ out_2d_unpacked[0][1] $end
+       $var wire 1 ] out_2d_unpacked[0][2] $end
+       $var wire 1 ^ out_2d_unpacked[0][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [1] $end
+       $var wire 1 _ out_2d_unpacked[1][0] $end
+       $var wire 1 ` out_2d_unpacked[1][1] $end
+       $var wire 1 a out_2d_unpacked[1][2] $end
+       $var wire 1 b out_2d_unpacked[1][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [2] $end
+       $var wire 1 c out_2d_unpacked[2][0] $end
+       $var wire 1 d out_2d_unpacked[2][1] $end
+       $var wire 1 e out_2d_unpacked[2][2] $end
+       $var wire 1 f out_2d_unpacked[2][3] $end
+      $upscope $end
+     $upscope $end
+     $var wire 290 g data [289:0] $end
+     $var wire 32 W cyc [31:0] $end
+     $var wire 1 ! clk $end
+     $var logic 290 g the_struct [289:0] $end
+     $attrbegin array unpacked bounds 12884901888 $end
+     $scope sv_array the_structs $end
+      $var logic 290 h the_structs[3] [289:0] $end
+      $var logic 290 i the_structs[2] [289:0] $end
+      $var logic 290 j the_structs[1] [289:0] $end
+      $var logic 290 k the_structs[0] [289:0] $end
+     $upscope $end
+     $var logic 870 l the_packed_structs [869:0] $end
+     $var logic 3 m the_local_struct [2:0] $end
+     $var parameter 3 < const_struct [2:0] $end
+     $var logic 3 n the_typedefed_struct [2:0] $end
+     $attrbegin pack unpacked members 3 $end
+     $scope struct the_local_unpacked_struct $end
+      $var logic 1 o field_a $end
+      $var logic 1 p field_b $end
+      $var logic 1 q field_c $end
+     $upscope $end
+     $var logic 8 r the_local_union [7:0] $end
+     $var logic 64 s the_logic_array [63:0] $end
+     $var logic 64 t the_other_logic_array [63:0] $end
+     $attrbegin array unpacked bounds 4 $end
+     $scope sv_array the_unpacked_array $end
+      $var logic 16 u the_unpacked_array[0] [15:0] $end
+      $var logic 16 v the_unpacked_array[1] [15:0] $end
+      $var logic 16 w the_unpacked_array[2] [15:0] $end
+      $var logic 16 x the_unpacked_array[3] [15:0] $end
+      $var logic 16 y the_unpacked_array[4] [15:0] $end
+     $upscope $end
+     $attrbegin array unpacked bounds 2 $end
+     $scope sv_array the_2d_unpacked $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [0] $end
+       $var logic 1 z the_2d_unpacked[0][0] $end
+       $var logic 1 { the_2d_unpacked[0][1] $end
+       $var logic 1 | the_2d_unpacked[0][2] $end
+       $var logic 1 } the_2d_unpacked[0][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [1] $end
+       $var logic 1 ~ the_2d_unpacked[1][0] $end
+       $var logic 1 !! the_2d_unpacked[1][1] $end
+       $var logic 1 "! the_2d_unpacked[1][2] $end
+       $var logic 1 #! the_2d_unpacked[1][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [2] $end
+       $var logic 1 $! the_2d_unpacked[2][0] $end
+       $var logic 1 %! the_2d_unpacked[2][1] $end
+       $var logic 1 &! the_2d_unpacked[2][2] $end
+       $var logic 1 '! the_2d_unpacked[2][3] $end
+      $upscope $end
+     $upscope $end
+     $var parameter 8 U two_fours [7:0] $end
+     $var logic 8 (! two_fours_var [7:0] $end
+    $upscope $end
+   $upscope $end
+   $scope module gen_loop[2] $end
+    $var int 32 )! loop_cyc [31:0] $end
+    $scope module the_sub $end
+     $var wire 1 *! a $end
+     $var wire 1 +! b $end
+     $var wire 1 ,! x $end
+     $attrbegin array unpacked bounds 2 $end
+     $scope sv_array out_2d_unpacked $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [0] $end
+       $var wire 1 -! out_2d_unpacked[0][0] $end
+       $var wire 1 .! out_2d_unpacked[0][1] $end
+       $var wire 1 /! out_2d_unpacked[0][2] $end
+       $var wire 1 0! out_2d_unpacked[0][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [1] $end
+       $var wire 1 1! out_2d_unpacked[1][0] $end
+       $var wire 1 2! out_2d_unpacked[1][1] $end
+       $var wire 1 3! out_2d_unpacked[1][2] $end
+       $var wire 1 4! out_2d_unpacked[1][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [2] $end
+       $var wire 1 5! out_2d_unpacked[2][0] $end
+       $var wire 1 6! out_2d_unpacked[2][1] $end
+       $var wire 1 7! out_2d_unpacked[2][2] $end
+       $var wire 1 8! out_2d_unpacked[2][3] $end
+      $upscope $end
+     $upscope $end
+     $var wire 290 9! data [289:0] $end
+     $var wire 32 )! cyc [31:0] $end
+     $var wire 1 ! clk $end
+     $var logic 290 9! the_struct [289:0] $end
+     $attrbegin array unpacked bounds 12884901888 $end
+     $scope sv_array the_structs $end
+      $var logic 290 :! the_structs[3] [289:0] $end
+      $var logic 290 ;! the_structs[2] [289:0] $end
+      $var logic 290 <! the_structs[1] [289:0] $end
+      $var logic 290 =! the_structs[0] [289:0] $end
+     $upscope $end
+     $var logic 870 >! the_packed_structs [869:0] $end
+     $var logic 3 ?! the_local_struct [2:0] $end
+     $var parameter 3 < const_struct [2:0] $end
+     $var logic 3 @! the_typedefed_struct [2:0] $end
+     $attrbegin pack unpacked members 3 $end
+     $scope struct the_local_unpacked_struct $end
+      $var logic 1 A! field_a $end
+      $var logic 1 B! field_b $end
+      $var logic 1 C! field_c $end
+     $upscope $end
+     $var logic 8 D! the_local_union [7:0] $end
+     $var logic 64 E! the_logic_array [63:0] $end
+     $var logic 64 F! the_other_logic_array [63:0] $end
+     $attrbegin array unpacked bounds 4 $end
+     $scope sv_array the_unpacked_array $end
+      $var logic 16 G! the_unpacked_array[0] [15:0] $end
+      $var logic 16 H! the_unpacked_array[1] [15:0] $end
+      $var logic 16 I! the_unpacked_array[2] [15:0] $end
+      $var logic 16 J! the_unpacked_array[3] [15:0] $end
+      $var logic 16 K! the_unpacked_array[4] [15:0] $end
+     $upscope $end
+     $attrbegin array unpacked bounds 2 $end
+     $scope sv_array the_2d_unpacked $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [0] $end
+       $var logic 1 L! the_2d_unpacked[0][0] $end
+       $var logic 1 M! the_2d_unpacked[0][1] $end
+       $var logic 1 N! the_2d_unpacked[0][2] $end
+       $var logic 1 O! the_2d_unpacked[0][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [1] $end
+       $var logic 1 P! the_2d_unpacked[1][0] $end
+       $var logic 1 Q! the_2d_unpacked[1][1] $end
+       $var logic 1 R! the_2d_unpacked[1][2] $end
+       $var logic 1 S! the_2d_unpacked[1][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [2] $end
+       $var logic 1 T! the_2d_unpacked[2][0] $end
+       $var logic 1 U! the_2d_unpacked[2][1] $end
+       $var logic 1 V! the_2d_unpacked[2][2] $end
+       $var logic 1 W! the_2d_unpacked[2][3] $end
+      $upscope $end
+     $upscope $end
+     $var parameter 8 U two_fours [7:0] $end
+     $var logic 8 X! two_fours_var [7:0] $end
+    $upscope $end
+   $upscope $end
+   $scope module gen_loop[3] $end
+    $var int 32 Y! loop_cyc [31:0] $end
+    $scope module the_sub $end
+     $var wire 1 Z! a $end
+     $var wire 1 [! b $end
+     $var wire 1 \! x $end
+     $attrbegin array unpacked bounds 2 $end
+     $scope sv_array out_2d_unpacked $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [0] $end
+       $var wire 1 ]! out_2d_unpacked[0][0] $end
+       $var wire 1 ^! out_2d_unpacked[0][1] $end
+       $var wire 1 _! out_2d_unpacked[0][2] $end
+       $var wire 1 `! out_2d_unpacked[0][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [1] $end
+       $var wire 1 a! out_2d_unpacked[1][0] $end
+       $var wire 1 b! out_2d_unpacked[1][1] $end
+       $var wire 1 c! out_2d_unpacked[1][2] $end
+       $var wire 1 d! out_2d_unpacked[1][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [2] $end
+       $var wire 1 e! out_2d_unpacked[2][0] $end
+       $var wire 1 f! out_2d_unpacked[2][1] $end
+       $var wire 1 g! out_2d_unpacked[2][2] $end
+       $var wire 1 h! out_2d_unpacked[2][3] $end
+      $upscope $end
+     $upscope $end
+     $var wire 290 i! data [289:0] $end
+     $var wire 32 Y! cyc [31:0] $end
+     $var wire 1 ! clk $end
+     $var logic 290 i! the_struct [289:0] $end
+     $attrbegin array unpacked bounds 12884901888 $end
+     $scope sv_array the_structs $end
+      $var logic 290 j! the_structs[3] [289:0] $end
+      $var logic 290 k! the_structs[2] [289:0] $end
+      $var logic 290 l! the_structs[1] [289:0] $end
+      $var logic 290 m! the_structs[0] [289:0] $end
+     $upscope $end
+     $var logic 870 n! the_packed_structs [869:0] $end
+     $var logic 3 o! the_local_struct [2:0] $end
+     $var parameter 3 < const_struct [2:0] $end
+     $var logic 3 p! the_typedefed_struct [2:0] $end
+     $attrbegin pack unpacked members 3 $end
+     $scope struct the_local_unpacked_struct $end
+      $var logic 1 q! field_a $end
+      $var logic 1 r! field_b $end
+      $var logic 1 s! field_c $end
+     $upscope $end
+     $var logic 8 t! the_local_union [7:0] $end
+     $var logic 64 u! the_logic_array [63:0] $end
+     $var logic 64 v! the_other_logic_array [63:0] $end
+     $attrbegin array unpacked bounds 4 $end
+     $scope sv_array the_unpacked_array $end
+      $var logic 16 w! the_unpacked_array[0] [15:0] $end
+      $var logic 16 x! the_unpacked_array[1] [15:0] $end
+      $var logic 16 y! the_unpacked_array[2] [15:0] $end
+      $var logic 16 z! the_unpacked_array[3] [15:0] $end
+      $var logic 16 {! the_unpacked_array[4] [15:0] $end
+     $upscope $end
+     $attrbegin array unpacked bounds 2 $end
+     $scope sv_array the_2d_unpacked $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [0] $end
+       $var logic 1 |! the_2d_unpacked[0][0] $end
+       $var logic 1 }! the_2d_unpacked[0][1] $end
+       $var logic 1 ~! the_2d_unpacked[0][2] $end
+       $var logic 1 !" the_2d_unpacked[0][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [1] $end
+       $var logic 1 "" the_2d_unpacked[1][0] $end
+       $var logic 1 #" the_2d_unpacked[1][1] $end
+       $var logic 1 $" the_2d_unpacked[1][2] $end
+       $var logic 1 %" the_2d_unpacked[1][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [2] $end
+       $var logic 1 &" the_2d_unpacked[2][0] $end
+       $var logic 1 '" the_2d_unpacked[2][1] $end
+       $var logic 1 (" the_2d_unpacked[2][2] $end
+       $var logic 1 )" the_2d_unpacked[2][3] $end
+      $upscope $end
+     $upscope $end
+     $var parameter 8 U two_fours [7:0] $end
+     $var logic 8 *" two_fours_var [7:0] $end
+    $upscope $end
+   $upscope $end
+   $scope interface the_intf_a $end
+    $var wire 1 ! clk $end
+    $var logic 32 +" data [31:0] $end
+    $var int 32 ," data_typed [31:0] $end
+   $upscope $end
+   $scope interface the_intf_b $end
+    $var wire 1 ! clk $end
+    $var logic 32 -" data [31:0] $end
+    $var int 32 ." data_typed [31:0] $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
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diff --git a/test_regress/t/t_trace_type_dupes_default_fst.py b/test_regress/t/t_trace_type_dupes_default_fst.py
new file mode 100755
index 000000000..e2f71b23f
--- /dev/null
+++ b/test_regress/t/t_trace_type_dupes_default_fst.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_type_dupes_common
+
+test.scenarios('vlt_all')
+
+trace_type_dupes_common.run(test)
diff --git a/test_regress/t/t_trace_type_dupes_default_saif.out b/test_regress/t/t_trace_type_dupes_default_saif.out
new file mode 100644
index 000000000..2ffb4628f
--- /dev/null
+++ b/test_regress/t/t_trace_type_dupes_default_saif.out
@@ -0,0 +1,12063 @@
+// Generated by verilated_saif
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(PROGRAM_NAME "Verilator")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 100)
+ (INSTANCE top
+  (NET
+   (clk (T0 55) (T1 45) (TZ 0) (TX 0) (TB 0) (TC 19))
+  )
+  (INSTANCE pkg
+   (NET
+    (SUB_ONES\[0\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (SUB_ONES\[1\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (SUB_ONES\[2\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (SUB_ONES\[3\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (SUB_ONES\[4\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (SUB_ONES\[5\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (SUB_ONES\[6\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (SUB_ONES\[7\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (SUB_ONES\[8\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (SUB_ONES\[9\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (SUB_ONES\[10\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (SUB_ONES\[11\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (SUB_ONES\[12\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (SUB_ONES\[13\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (SUB_ONES\[14\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (SUB_ONES\[15\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (SUB_ONES\[16\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (SUB_ZEROS\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (SUB_ZEROS\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (SUB_ZEROS\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (SUB_ZEROS\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+     (loop_cyc\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+      (the_unpacked_array[4]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+      (the_2d_unpacked[0][1] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (the_2d_unpacked[0][2] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 6))
+      (the_2d_unpacked[0][3] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 8))
+      (the_2d_unpacked[1][0] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (the_2d_unpacked[1][1] (T0 10) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (the_2d_unpacked[1][2] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (the_2d_unpacked[1][3] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+      (the_2d_unpacked[2][0] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 6))
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+      (two_fours_var\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (two_fours_var\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (two_fours_var\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (two_fours_var\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     )
+     (INSTANCE the_local_unpacked_struct
+      (NET
+       (field_a (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (field_b (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (field_c (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+      )
+     )
+    )
+   )
+   (INSTANCE the_intf_a
+    (NET
+     (clk (T0 55) (T1 45) (TZ 0) (TX 0) (TB 0) (TC 19))
+     (data\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 11))
+     (data\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (data\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (data\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+     (data\[9\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
+     (data\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (data\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[16\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 11))
+     (data\[17\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+     (data\[18\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (data\[19\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[24\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+     (data\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (data\[26\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (data\[27\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 11))
+     (data_typed\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (data_typed\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (data_typed\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data_typed\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+     (data_typed\[9\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
+     (data_typed\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (data_typed\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data_typed\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[16\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 11))
+     (data_typed\[17\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+     (data_typed\[18\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (data_typed\[19\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data_typed\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[24\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+     (data_typed\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (data_typed\[26\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (data_typed\[27\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data_typed\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    )
+   )
+   (INSTANCE the_intf_b
+    (NET
+     (clk (T0 55) (T1 45) (TZ 0) (TX 0) (TB 0) (TC 19))
+     (data\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+     (data\[1\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
+     (data\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (data\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 11))
+     (data\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+     (data\[10\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (data\[11\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[16\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+     (data\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (data\[18\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (data\[19\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[24\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 11))
+     (data\[25\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (data\[26\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (data\[27\] (T0 30) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+     (data_typed\[1\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
+     (data_typed\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (data_typed\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data_typed\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 11))
+     (data_typed\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+     (data_typed\[10\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (data_typed\[11\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data_typed\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[16\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+     (data_typed\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (data_typed\[18\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (data_typed\[19\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data_typed\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[24\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 11))
+     (data_typed\[25\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (data_typed\[26\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (data_typed\[27\] (T0 30) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data_typed\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    )
+   )
+  )
+ )
+)
diff --git a/test_regress/t/t_trace_type_dupes_default_saif.py b/test_regress/t/t_trace_type_dupes_default_saif.py
new file mode 100755
index 000000000..e2f71b23f
--- /dev/null
+++ b/test_regress/t/t_trace_type_dupes_default_saif.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_type_dupes_common
+
+test.scenarios('vlt_all')
+
+trace_type_dupes_common.run(test)
diff --git a/test_regress/t/t_trace_type_dupes_default_vcd.out b/test_regress/t/t_trace_type_dupes_default_vcd.out
new file mode 100644
index 000000000..19f1a4fb4
--- /dev/null
+++ b/test_regress/t/t_trace_type_dupes_default_vcd.out
@@ -0,0 +1,1522 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module top $end
+  $var wire 1 !$ clk $end
+  $scope module pkg $end
+   $var wire 17 :% SUB_ONES [16:0] $end
+   $var wire 17 ;% SUB_ZEROS [16:0] $end
+  $upscope $end
+  $scope module t $end
+   $var wire 1 !$ clk $end
+   $var wire 32 " cyc [31:0] $end
+   $var wire 4 # x [3:0] $end
+   $scope module gen_loop[0] $end
+    $var wire 32 " loop_cyc [31:0] $end
+    $scope module the_sub $end
+     $var wire 1 $ a $end
+     $var wire 1 % b $end
+     $var wire 1 & x $end
+     $var wire 1 ' out_2d_unpacked[0][0] $end
+     $var wire 1 ( out_2d_unpacked[0][1] $end
+     $var wire 1 ) out_2d_unpacked[0][2] $end
+     $var wire 1 * out_2d_unpacked[0][3] $end
+     $var wire 1 + out_2d_unpacked[1][0] $end
+     $var wire 1 , out_2d_unpacked[1][1] $end
+     $var wire 1 - out_2d_unpacked[1][2] $end
+     $var wire 1 . out_2d_unpacked[1][3] $end
+     $var wire 1 / out_2d_unpacked[2][0] $end
+     $var wire 1 0 out_2d_unpacked[2][1] $end
+     $var wire 1 1 out_2d_unpacked[2][2] $end
+     $var wire 1 2 out_2d_unpacked[2][3] $end
+     $var wire 290 3 data [289:0] $end
+     $var wire 32 " cyc [31:0] $end
+     $var wire 1 !$ clk $end
+     $var wire 290 3 the_struct [289:0] $end
+     $var wire 290 = the_structs[0] [289:0] $end
+     $var wire 290 G the_structs[1] [289:0] $end
+     $var wire 290 Q the_structs[2] [289:0] $end
+     $var wire 290 [ the_structs[3] [289:0] $end
+     $var wire 870 "$ the_packed_structs [869:0] $end
+     $var wire 3 e the_local_struct [2:0] $end
+     $var wire 3 >$ const_struct [2:0] $end
+     $var wire 3 f the_typedefed_struct [2:0] $end
+     $scope module the_local_unpacked_struct $end
+      $var wire 1 g field_a $end
+      $var wire 1 h field_b $end
+      $var wire 1 i field_c $end
+     $upscope $end
+     $var wire 8 j the_local_union [7:0] $end
+     $var wire 64 k the_logic_array [63:0] $end
+     $var wire 64 m the_other_logic_array [63:0] $end
+     $var wire 16 o the_unpacked_array[0] [15:0] $end
+     $var wire 16 p the_unpacked_array[1] [15:0] $end
+     $var wire 16 q the_unpacked_array[2] [15:0] $end
+     $var wire 16 r the_unpacked_array[3] [15:0] $end
+     $var wire 16 s the_unpacked_array[4] [15:0] $end
+     $var wire 1 t the_2d_unpacked[0][0] $end
+     $var wire 1 u the_2d_unpacked[0][1] $end
+     $var wire 1 v the_2d_unpacked[0][2] $end
+     $var wire 1 w the_2d_unpacked[0][3] $end
+     $var wire 1 x the_2d_unpacked[1][0] $end
+     $var wire 1 y the_2d_unpacked[1][1] $end
+     $var wire 1 z the_2d_unpacked[1][2] $end
+     $var wire 1 { the_2d_unpacked[1][3] $end
+     $var wire 1 | the_2d_unpacked[2][0] $end
+     $var wire 1 } the_2d_unpacked[2][1] $end
+     $var wire 1 ~ the_2d_unpacked[2][2] $end
+     $var wire 1 !! the_2d_unpacked[2][3] $end
+     $var wire 8 ?$ two_fours [7:0] $end
+     $var wire 8 @$ two_fours_var [7:0] $end
+    $upscope $end
+   $upscope $end
+   $scope module gen_loop[1] $end
+    $var wire 32 "! loop_cyc [31:0] $end
+    $scope module the_sub $end
+     $var wire 1 #! a $end
+     $var wire 1 $! b $end
+     $var wire 1 %! x $end
+     $var wire 1 &! out_2d_unpacked[0][0] $end
+     $var wire 1 '! out_2d_unpacked[0][1] $end
+     $var wire 1 (! out_2d_unpacked[0][2] $end
+     $var wire 1 )! out_2d_unpacked[0][3] $end
+     $var wire 1 *! out_2d_unpacked[1][0] $end
+     $var wire 1 +! out_2d_unpacked[1][1] $end
+     $var wire 1 ,! out_2d_unpacked[1][2] $end
+     $var wire 1 -! out_2d_unpacked[1][3] $end
+     $var wire 1 .! out_2d_unpacked[2][0] $end
+     $var wire 1 /! out_2d_unpacked[2][1] $end
+     $var wire 1 0! out_2d_unpacked[2][2] $end
+     $var wire 1 1! out_2d_unpacked[2][3] $end
+     $var wire 290 2! data [289:0] $end
+     $var wire 32 "! cyc [31:0] $end
+     $var wire 1 !$ clk $end
+     $var wire 290 2! the_struct [289:0] $end
+     $var wire 290 <! the_structs[0] [289:0] $end
+     $var wire 290 F! the_structs[1] [289:0] $end
+     $var wire 290 P! the_structs[2] [289:0] $end
+     $var wire 290 Z! the_structs[3] [289:0] $end
+     $var wire 870 A$ the_packed_structs [869:0] $end
+     $var wire 3 d! the_local_struct [2:0] $end
+     $var wire 3 >$ const_struct [2:0] $end
+     $var wire 3 e! the_typedefed_struct [2:0] $end
+     $scope module the_local_unpacked_struct $end
+      $var wire 1 f! field_a $end
+      $var wire 1 g! field_b $end
+      $var wire 1 h! field_c $end
+     $upscope $end
+     $var wire 8 i! the_local_union [7:0] $end
+     $var wire 64 j! the_logic_array [63:0] $end
+     $var wire 64 l! the_other_logic_array [63:0] $end
+     $var wire 16 n! the_unpacked_array[0] [15:0] $end
+     $var wire 16 o! the_unpacked_array[1] [15:0] $end
+     $var wire 16 p! the_unpacked_array[2] [15:0] $end
+     $var wire 16 q! the_unpacked_array[3] [15:0] $end
+     $var wire 16 r! the_unpacked_array[4] [15:0] $end
+     $var wire 1 s! the_2d_unpacked[0][0] $end
+     $var wire 1 t! the_2d_unpacked[0][1] $end
+     $var wire 1 u! the_2d_unpacked[0][2] $end
+     $var wire 1 v! the_2d_unpacked[0][3] $end
+     $var wire 1 w! the_2d_unpacked[1][0] $end
+     $var wire 1 x! the_2d_unpacked[1][1] $end
+     $var wire 1 y! the_2d_unpacked[1][2] $end
+     $var wire 1 z! the_2d_unpacked[1][3] $end
+     $var wire 1 {! the_2d_unpacked[2][0] $end
+     $var wire 1 |! the_2d_unpacked[2][1] $end
+     $var wire 1 }! the_2d_unpacked[2][2] $end
+     $var wire 1 ~! the_2d_unpacked[2][3] $end
+     $var wire 8 ?$ two_fours [7:0] $end
+     $var wire 8 ]$ two_fours_var [7:0] $end
+    $upscope $end
+   $upscope $end
+   $scope module gen_loop[2] $end
+    $var wire 32 !" loop_cyc [31:0] $end
+    $scope module the_sub $end
+     $var wire 1 "" a $end
+     $var wire 1 #" b $end
+     $var wire 1 $" x $end
+     $var wire 1 %" out_2d_unpacked[0][0] $end
+     $var wire 1 &" out_2d_unpacked[0][1] $end
+     $var wire 1 '" out_2d_unpacked[0][2] $end
+     $var wire 1 (" out_2d_unpacked[0][3] $end
+     $var wire 1 )" out_2d_unpacked[1][0] $end
+     $var wire 1 *" out_2d_unpacked[1][1] $end
+     $var wire 1 +" out_2d_unpacked[1][2] $end
+     $var wire 1 ," out_2d_unpacked[1][3] $end
+     $var wire 1 -" out_2d_unpacked[2][0] $end
+     $var wire 1 ." out_2d_unpacked[2][1] $end
+     $var wire 1 /" out_2d_unpacked[2][2] $end
+     $var wire 1 0" out_2d_unpacked[2][3] $end
+     $var wire 290 1" data [289:0] $end
+     $var wire 32 !" cyc [31:0] $end
+     $var wire 1 !$ clk $end
+     $var wire 290 1" the_struct [289:0] $end
+     $var wire 290 ;" the_structs[0] [289:0] $end
+     $var wire 290 E" the_structs[1] [289:0] $end
+     $var wire 290 O" the_structs[2] [289:0] $end
+     $var wire 290 Y" the_structs[3] [289:0] $end
+     $var wire 870 ^$ the_packed_structs [869:0] $end
+     $var wire 3 c" the_local_struct [2:0] $end
+     $var wire 3 >$ const_struct [2:0] $end
+     $var wire 3 d" the_typedefed_struct [2:0] $end
+     $scope module the_local_unpacked_struct $end
+      $var wire 1 e" field_a $end
+      $var wire 1 f" field_b $end
+      $var wire 1 g" field_c $end
+     $upscope $end
+     $var wire 8 h" the_local_union [7:0] $end
+     $var wire 64 i" the_logic_array [63:0] $end
+     $var wire 64 k" the_other_logic_array [63:0] $end
+     $var wire 16 m" the_unpacked_array[0] [15:0] $end
+     $var wire 16 n" the_unpacked_array[1] [15:0] $end
+     $var wire 16 o" the_unpacked_array[2] [15:0] $end
+     $var wire 16 p" the_unpacked_array[3] [15:0] $end
+     $var wire 16 q" the_unpacked_array[4] [15:0] $end
+     $var wire 1 r" the_2d_unpacked[0][0] $end
+     $var wire 1 s" the_2d_unpacked[0][1] $end
+     $var wire 1 t" the_2d_unpacked[0][2] $end
+     $var wire 1 u" the_2d_unpacked[0][3] $end
+     $var wire 1 v" the_2d_unpacked[1][0] $end
+     $var wire 1 w" the_2d_unpacked[1][1] $end
+     $var wire 1 x" the_2d_unpacked[1][2] $end
+     $var wire 1 y" the_2d_unpacked[1][3] $end
+     $var wire 1 z" the_2d_unpacked[2][0] $end
+     $var wire 1 {" the_2d_unpacked[2][1] $end
+     $var wire 1 |" the_2d_unpacked[2][2] $end
+     $var wire 1 }" the_2d_unpacked[2][3] $end
+     $var wire 8 ?$ two_fours [7:0] $end
+     $var wire 8 z$ two_fours_var [7:0] $end
+    $upscope $end
+   $upscope $end
+   $scope module gen_loop[3] $end
+    $var wire 32 ~" loop_cyc [31:0] $end
+    $scope module the_sub $end
+     $var wire 1 !# a $end
+     $var wire 1 "# b $end
+     $var wire 1 ## x $end
+     $var wire 1 $# out_2d_unpacked[0][0] $end
+     $var wire 1 %# out_2d_unpacked[0][1] $end
+     $var wire 1 &# out_2d_unpacked[0][2] $end
+     $var wire 1 '# out_2d_unpacked[0][3] $end
+     $var wire 1 (# out_2d_unpacked[1][0] $end
+     $var wire 1 )# out_2d_unpacked[1][1] $end
+     $var wire 1 *# out_2d_unpacked[1][2] $end
+     $var wire 1 +# out_2d_unpacked[1][3] $end
+     $var wire 1 ,# out_2d_unpacked[2][0] $end
+     $var wire 1 -# out_2d_unpacked[2][1] $end
+     $var wire 1 .# out_2d_unpacked[2][2] $end
+     $var wire 1 /# out_2d_unpacked[2][3] $end
+     $var wire 290 0# data [289:0] $end
+     $var wire 32 ~" cyc [31:0] $end
+     $var wire 1 !$ clk $end
+     $var wire 290 0# the_struct [289:0] $end
+     $var wire 290 :# the_structs[0] [289:0] $end
+     $var wire 290 D# the_structs[1] [289:0] $end
+     $var wire 290 N# the_structs[2] [289:0] $end
+     $var wire 290 X# the_structs[3] [289:0] $end
+     $var wire 870 {$ the_packed_structs [869:0] $end
+     $var wire 3 b# the_local_struct [2:0] $end
+     $var wire 3 >$ const_struct [2:0] $end
+     $var wire 3 c# the_typedefed_struct [2:0] $end
+     $scope module the_local_unpacked_struct $end
+      $var wire 1 d# field_a $end
+      $var wire 1 e# field_b $end
+      $var wire 1 f# field_c $end
+     $upscope $end
+     $var wire 8 g# the_local_union [7:0] $end
+     $var wire 64 h# the_logic_array [63:0] $end
+     $var wire 64 j# the_other_logic_array [63:0] $end
+     $var wire 16 l# the_unpacked_array[0] [15:0] $end
+     $var wire 16 m# the_unpacked_array[1] [15:0] $end
+     $var wire 16 n# the_unpacked_array[2] [15:0] $end
+     $var wire 16 o# the_unpacked_array[3] [15:0] $end
+     $var wire 16 p# the_unpacked_array[4] [15:0] $end
+     $var wire 1 q# the_2d_unpacked[0][0] $end
+     $var wire 1 r# the_2d_unpacked[0][1] $end
+     $var wire 1 s# the_2d_unpacked[0][2] $end
+     $var wire 1 t# the_2d_unpacked[0][3] $end
+     $var wire 1 u# the_2d_unpacked[1][0] $end
+     $var wire 1 v# the_2d_unpacked[1][1] $end
+     $var wire 1 w# the_2d_unpacked[1][2] $end
+     $var wire 1 x# the_2d_unpacked[1][3] $end
+     $var wire 1 y# the_2d_unpacked[2][0] $end
+     $var wire 1 z# the_2d_unpacked[2][1] $end
+     $var wire 1 {# the_2d_unpacked[2][2] $end
+     $var wire 1 |# the_2d_unpacked[2][3] $end
+     $var wire 8 ?$ two_fours [7:0] $end
+     $var wire 8 9% two_fours_var [7:0] $end
+    $upscope $end
+   $upscope $end
+   $scope module the_intf_a $end
+    $var wire 1 !$ clk $end
+    $var wire 32 }# data [31:0] $end
+    $var wire 32 }# data_typed [31:0] $end
+   $upscope $end
+   $scope module the_intf_b $end
+    $var wire 1 !$ clk $end
+    $var wire 32 ~# data [31:0] $end
+    $var wire 32 ~# data_typed [31:0] $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
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diff --git a/test_regress/t/t_trace_type_dupes_default_vcd.py b/test_regress/t/t_trace_type_dupes_default_vcd.py
new file mode 100755
index 000000000..e2f71b23f
--- /dev/null
+++ b/test_regress/t/t_trace_type_dupes_default_vcd.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_type_dupes_common
+
+test.scenarios('vlt_all')
+
+trace_type_dupes_common.run(test)
diff --git a/test_regress/t/t_trace_type_dupes_structs_fst.out b/test_regress/t/t_trace_type_dupes_structs_fst.out
new file mode 100644
index 000000000..bfb474050
--- /dev/null
+++ b/test_regress/t/t_trace_type_dupes_structs_fst.out
@@ -0,0 +1,4119 @@
+$date
+Mon Apr 13 14:47:24 2026
+
+$end
+$version
+Generated by VerilatedFst
+$end
+$timescale
+1ps
+$end
+ $scope module top $end
+  $var wire 1 ! clk $end
+  $scope module pkg $end
+   $attrbegin pack packed members 3 $end
+   $scope struct SUB_ONES $end
+    $var parameter 1 " field_a $end
+    $var parameter 6 # field_b [5:0] $end
+    $var parameter 10 $ field_c [9:0] $end
+   $upscope $end
+   $attrbegin pack packed members 3 $end
+   $scope struct SUB_ZEROS $end
+    $var parameter 1 % field_a $end
+    $var parameter 6 & field_b [5:0] $end
+    $var parameter 10 ' field_c [9:0] $end
+   $upscope $end
+  $upscope $end
+  $scope module t $end
+   $var wire 1 ! clk $end
+   $var int 32 ( cyc [31:0] $end
+   $var logic 4 ) x [3:0] $end
+   $scope module gen_loop[0] $end
+    $var int 32 ( loop_cyc [31:0] $end
+    $scope module the_sub $end
+     $var wire 1 * a $end
+     $var wire 1 + b $end
+     $var wire 1 , x $end
+     $attrbegin array unpacked bounds 2 $end
+     $scope sv_array out_2d_unpacked $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [0] $end
+       $var wire 1 - out_2d_unpacked[0][0] $end
+       $var wire 1 . out_2d_unpacked[0][1] $end
+       $var wire 1 / out_2d_unpacked[0][2] $end
+       $var wire 1 0 out_2d_unpacked[0][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [1] $end
+       $var wire 1 1 out_2d_unpacked[1][0] $end
+       $var wire 1 2 out_2d_unpacked[1][1] $end
+       $var wire 1 3 out_2d_unpacked[1][2] $end
+       $var wire 1 4 out_2d_unpacked[1][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [2] $end
+       $var wire 1 5 out_2d_unpacked[2][0] $end
+       $var wire 1 6 out_2d_unpacked[2][1] $end
+       $var wire 1 7 out_2d_unpacked[2][2] $end
+       $var wire 1 8 out_2d_unpacked[2][3] $end
+      $upscope $end
+     $upscope $end
+     $attrbegin pack packed members 5 $end
+     $scope struct data $end
+      $var wire 1 9 foo $end
+      $attrbegin array packed bounds 12884901888 $end
+      $scope sv_array bar $end
+       $var wire 32 : bar[3] [31:0] $end
+       $var wire 32 ; bar[2] [31:0] $end
+       $var wire 32 < bar[1] [31:0] $end
+       $var wire 32 = bar[0] [31:0] $end
+      $upscope $end
+      $var wire 16 > baz [15:0] $end
+      $var wire 128 ? qux [127:0] $end
+      $attrbegin pack packed members 3 $end
+      $scope struct sub_struct $end
+       $var wire 1 @ field_a $end
+       $var wire 6 A field_b [5:0] $end
+       $var wire 10 B field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $var wire 32 ( cyc [31:0] $end
+     $var wire 1 ! clk $end
+     $attrbegin pack packed members 5 $end
+     $scope struct the_struct $end
+      $var logic 1 9 foo $end
+      $attrbegin array packed bounds 12884901888 $end
+      $scope sv_array bar $end
+       $var logic 32 : bar[3] [31:0] $end
+       $var logic 32 ; bar[2] [31:0] $end
+       $var logic 32 < bar[1] [31:0] $end
+       $var logic 32 = bar[0] [31:0] $end
+      $upscope $end
+      $var logic 16 > baz [15:0] $end
+      $var logic 128 ? qux [127:0] $end
+      $attrbegin pack packed members 3 $end
+      $scope struct sub_struct $end
+       $var logic 1 @ field_a $end
+       $var logic 6 A field_b [5:0] $end
+       $var logic 10 B field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $attrbegin array unpacked bounds 12884901888 $end
+     $scope sv_array the_structs $end
+      $attrbegin pack packed members 5 $end
+      $scope struct [3] $end
+       $var logic 1 C foo $end
+       $attrbegin array packed bounds 12884901888 $end
+       $scope sv_array bar $end
+        $var logic 32 D bar[3] [31:0] $end
+        $var logic 32 E bar[2] [31:0] $end
+        $var logic 32 F bar[1] [31:0] $end
+        $var logic 32 G bar[0] [31:0] $end
+       $upscope $end
+       $var logic 16 H baz [15:0] $end
+       $var logic 128 I qux [127:0] $end
+       $attrbegin pack packed members 3 $end
+       $scope struct sub_struct $end
+        $var logic 1 J field_a $end
+        $var logic 6 K field_b [5:0] $end
+        $var logic 10 L field_c [9:0] $end
+       $upscope $end
+      $upscope $end
+      $attrbegin pack packed members 5 $end
+      $scope struct [2] $end
+       $var logic 1 M foo $end
+       $attrbegin array packed bounds 12884901888 $end
+       $scope sv_array bar $end
+        $var logic 32 N bar[3] [31:0] $end
+        $var logic 32 O bar[2] [31:0] $end
+        $var logic 32 P bar[1] [31:0] $end
+        $var logic 32 Q bar[0] [31:0] $end
+       $upscope $end
+       $var logic 16 R baz [15:0] $end
+       $var logic 128 S qux [127:0] $end
+       $attrbegin pack packed members 3 $end
+       $scope struct sub_struct $end
+        $var logic 1 T field_a $end
+        $var logic 6 U field_b [5:0] $end
+        $var logic 10 V field_c [9:0] $end
+       $upscope $end
+      $upscope $end
+      $attrbegin pack packed members 5 $end
+      $scope struct [1] $end
+       $var logic 1 W foo $end
+       $attrbegin array packed bounds 12884901888 $end
+       $scope sv_array bar $end
+        $var logic 32 X bar[3] [31:0] $end
+        $var logic 32 Y bar[2] [31:0] $end
+        $var logic 32 Z bar[1] [31:0] $end
+        $var logic 32 [ bar[0] [31:0] $end
+       $upscope $end
+       $var logic 16 \ baz [15:0] $end
+       $var logic 128 ] qux [127:0] $end
+       $attrbegin pack packed members 3 $end
+       $scope struct sub_struct $end
+        $var logic 1 ^ field_a $end
+        $var logic 6 _ field_b [5:0] $end
+        $var logic 10 ` field_c [9:0] $end
+       $upscope $end
+      $upscope $end
+      $attrbegin pack packed members 5 $end
+      $scope struct [0] $end
+       $var logic 1 a foo $end
+       $attrbegin array packed bounds 12884901888 $end
+       $scope sv_array bar $end
+        $var logic 32 b bar[3] [31:0] $end
+        $var logic 32 c bar[2] [31:0] $end
+        $var logic 32 d bar[1] [31:0] $end
+        $var logic 32 e bar[0] [31:0] $end
+       $upscope $end
+       $var logic 16 f baz [15:0] $end
+       $var logic 128 g qux [127:0] $end
+       $attrbegin pack packed members 3 $end
+       $scope struct sub_struct $end
+        $var logic 1 h field_a $end
+        $var logic 6 i field_b [5:0] $end
+        $var logic 10 j field_c [9:0] $end
+       $upscope $end
+      $upscope $end
+     $upscope $end
+     $attrbegin array packed bounds 8589934592 $end
+     $scope sv_array the_packed_structs $end
+      $attrbegin pack packed members 5 $end
+      $scope struct [2] $end
+       $var logic 1 k foo $end
+       $attrbegin array packed bounds 12884901888 $end
+       $scope sv_array bar $end
+        $var logic 32 l bar[3] [31:0] $end
+        $var logic 32 m bar[2] [31:0] $end
+        $var logic 32 n bar[1] [31:0] $end
+        $var logic 32 o bar[0] [31:0] $end
+       $upscope $end
+       $var logic 16 p baz [15:0] $end
+       $var logic 128 q qux [127:0] $end
+       $attrbegin pack packed members 3 $end
+       $scope struct sub_struct $end
+        $var logic 1 r field_a $end
+        $var logic 6 s field_b [5:0] $end
+        $var logic 10 t field_c [9:0] $end
+       $upscope $end
+      $upscope $end
+      $attrbegin pack packed members 5 $end
+      $scope struct [1] $end
+       $var logic 1 u foo $end
+       $attrbegin array packed bounds 12884901888 $end
+       $scope sv_array bar $end
+        $var logic 32 v bar[3] [31:0] $end
+        $var logic 32 w bar[2] [31:0] $end
+        $var logic 32 x bar[1] [31:0] $end
+        $var logic 32 y bar[0] [31:0] $end
+       $upscope $end
+       $var logic 16 z baz [15:0] $end
+       $var logic 128 { qux [127:0] $end
+       $attrbegin pack packed members 3 $end
+       $scope struct sub_struct $end
+        $var logic 1 | field_a $end
+        $var logic 6 } field_b [5:0] $end
+        $var logic 10 ~ field_c [9:0] $end
+       $upscope $end
+      $upscope $end
+      $attrbegin pack packed members 5 $end
+      $scope struct [0] $end
+       $var logic 1 !! foo $end
+       $attrbegin array packed bounds 12884901888 $end
+       $scope sv_array bar $end
+        $var logic 32 "! bar[3] [31:0] $end
+        $var logic 32 #! bar[2] [31:0] $end
+        $var logic 32 $! bar[1] [31:0] $end
+        $var logic 32 %! bar[0] [31:0] $end
+       $upscope $end
+       $var logic 16 &! baz [15:0] $end
+       $var logic 128 '! qux [127:0] $end
+       $attrbegin pack packed members 3 $end
+       $scope struct sub_struct $end
+        $var logic 1 (! field_a $end
+        $var logic 6 )! field_b [5:0] $end
+        $var logic 10 *! field_c [9:0] $end
+       $upscope $end
+      $upscope $end
+     $upscope $end
+     $attrbegin pack packed members 3 $end
+     $scope struct the_local_struct $end
+      $var logic 1 +! abc $end
+      $var logic 1 ,! def $end
+      $var logic 1 -! xyz $end
+     $upscope $end
+     $attrbegin pack packed members 3 $end
+     $scope struct const_struct $end
+      $var parameter 1 " abc $end
+      $var parameter 1 % def $end
+      $var parameter 1 " xyz $end
+     $upscope $end
+     $attrbegin pack packed members 3 $end
+     $scope struct the_typedefed_struct $end
+      $var logic 1 .! abc $end
+      $var logic 1 /! def $end
+      $var logic 1 0! xyz $end
+     $upscope $end
+     $attrbegin pack unpacked members 3 $end
+     $scope struct the_local_unpacked_struct $end
+      $var logic 1 1! field_a $end
+      $var logic 1 2! field_b $end
+      $var logic 1 3! field_c $end
+     $upscope $end
+     $attrbegin pack packed members 3 $end
+     $scope union the_local_union $end
+      $attrbegin pack packed members 1 $end
+      $scope struct union_a $end
+       $var logic 8 4! field_0 [7:0] $end
+      $upscope $end
+      $attrbegin pack packed members 2 $end
+      $scope struct union_b $end
+       $var logic 4 5! field_1 [3:0] $end
+       $var logic 4 6! field_2 [3:0] $end
+      $upscope $end
+      $attrbegin pack packed members 2 $end
+      $scope struct union_c $end
+       $var logic 2 7! field_3 [1:0] $end
+       $var logic 6 8! field_4 [5:0] $end
+      $upscope $end
+     $upscope $end
+     $attrbegin array packed bounds 4294967296 $end
+     $scope sv_array the_logic_array $end
+      $var logic 32 9! the_logic_array[1] [31:0] $end
+      $var logic 32 :! the_logic_array[0] [31:0] $end
+     $upscope $end
+     $attrbegin array packed bounds 4294967296 $end
+     $scope sv_array the_other_logic_array $end
+      $var logic 32 ;! the_other_logic_array[1] [31:0] $end
+      $var logic 32 <! the_other_logic_array[0] [31:0] $end
+     $upscope $end
+     $attrbegin array unpacked bounds 4 $end
+     $scope sv_array the_unpacked_array $end
+      $var logic 16 =! the_unpacked_array[0] [15:0] $end
+      $var logic 16 >! the_unpacked_array[1] [15:0] $end
+      $var logic 16 ?! the_unpacked_array[2] [15:0] $end
+      $var logic 16 @! the_unpacked_array[3] [15:0] $end
+      $var logic 16 A! the_unpacked_array[4] [15:0] $end
+     $upscope $end
+     $attrbegin array unpacked bounds 2 $end
+     $scope sv_array the_2d_unpacked $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [0] $end
+       $var logic 1 B! the_2d_unpacked[0][0] $end
+       $var logic 1 C! the_2d_unpacked[0][1] $end
+       $var logic 1 D! the_2d_unpacked[0][2] $end
+       $var logic 1 E! the_2d_unpacked[0][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [1] $end
+       $var logic 1 F! the_2d_unpacked[1][0] $end
+       $var logic 1 G! the_2d_unpacked[1][1] $end
+       $var logic 1 H! the_2d_unpacked[1][2] $end
+       $var logic 1 I! the_2d_unpacked[1][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [2] $end
+       $var logic 1 J! the_2d_unpacked[2][0] $end
+       $var logic 1 K! the_2d_unpacked[2][1] $end
+       $var logic 1 L! the_2d_unpacked[2][2] $end
+       $var logic 1 M! the_2d_unpacked[2][3] $end
+      $upscope $end
+     $upscope $end
+     $attrbegin array packed bounds 4294967296 $end
+     $scope sv_array two_fours $end
+      $var parameter 4 N! two_fours[1] [3:0] $end
+      $var parameter 4 O! two_fours[0] [3:0] $end
+     $upscope $end
+     $attrbegin array packed bounds 4294967296 $end
+     $scope sv_array two_fours_var $end
+      $var logic 4 P! two_fours_var[1] [3:0] $end
+      $var logic 4 Q! two_fours_var[0] [3:0] $end
+     $upscope $end
+    $upscope $end
+   $upscope $end
+   $scope module gen_loop[1] $end
+    $var int 32 R! loop_cyc [31:0] $end
+    $scope module the_sub $end
+     $var wire 1 S! a $end
+     $var wire 1 T! b $end
+     $var wire 1 U! x $end
+     $attrbegin array unpacked bounds 2 $end
+     $scope sv_array out_2d_unpacked $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [0] $end
+       $var wire 1 V! out_2d_unpacked[0][0] $end
+       $var wire 1 W! out_2d_unpacked[0][1] $end
+       $var wire 1 X! out_2d_unpacked[0][2] $end
+       $var wire 1 Y! out_2d_unpacked[0][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [1] $end
+       $var wire 1 Z! out_2d_unpacked[1][0] $end
+       $var wire 1 [! out_2d_unpacked[1][1] $end
+       $var wire 1 \! out_2d_unpacked[1][2] $end
+       $var wire 1 ]! out_2d_unpacked[1][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [2] $end
+       $var wire 1 ^! out_2d_unpacked[2][0] $end
+       $var wire 1 _! out_2d_unpacked[2][1] $end
+       $var wire 1 `! out_2d_unpacked[2][2] $end
+       $var wire 1 a! out_2d_unpacked[2][3] $end
+      $upscope $end
+     $upscope $end
+     $attrbegin pack packed members 5 $end
+     $scope struct data $end
+      $var wire 1 b! foo $end
+      $attrbegin array packed bounds 12884901888 $end
+      $scope sv_array bar $end
+       $var wire 32 c! bar[3] [31:0] $end
+       $var wire 32 d! bar[2] [31:0] $end
+       $var wire 32 e! bar[1] [31:0] $end
+       $var wire 32 f! bar[0] [31:0] $end
+      $upscope $end
+      $var wire 16 g! baz [15:0] $end
+      $var wire 128 h! qux [127:0] $end
+      $attrbegin pack packed members 3 $end
+      $scope struct sub_struct $end
+       $var wire 1 i! field_a $end
+       $var wire 6 j! field_b [5:0] $end
+       $var wire 10 k! field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $var wire 32 R! cyc [31:0] $end
+     $var wire 1 ! clk $end
+     $attrbegin pack packed members 5 $end
+     $scope struct the_struct $end
+      $var logic 1 b! foo $end
+      $attrbegin array packed bounds 12884901888 $end
+      $scope sv_array bar $end
+       $var logic 32 c! bar[3] [31:0] $end
+       $var logic 32 d! bar[2] [31:0] $end
+       $var logic 32 e! bar[1] [31:0] $end
+       $var logic 32 f! bar[0] [31:0] $end
+      $upscope $end
+      $var logic 16 g! baz [15:0] $end
+      $var logic 128 h! qux [127:0] $end
+      $attrbegin pack packed members 3 $end
+      $scope struct sub_struct $end
+       $var logic 1 i! field_a $end
+       $var logic 6 j! field_b [5:0] $end
+       $var logic 10 k! field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $attrbegin array unpacked bounds 12884901888 $end
+     $scope sv_array the_structs $end
+      $attrbegin pack packed members 5 $end
+      $scope struct [3] $end
+       $var logic 1 l! foo $end
+       $attrbegin array packed bounds 12884901888 $end
+       $scope sv_array bar $end
+        $var logic 32 m! bar[3] [31:0] $end
+        $var logic 32 n! bar[2] [31:0] $end
+        $var logic 32 o! bar[1] [31:0] $end
+        $var logic 32 p! bar[0] [31:0] $end
+       $upscope $end
+       $var logic 16 q! baz [15:0] $end
+       $var logic 128 r! qux [127:0] $end
+       $attrbegin pack packed members 3 $end
+       $scope struct sub_struct $end
+        $var logic 1 s! field_a $end
+        $var logic 6 t! field_b [5:0] $end
+        $var logic 10 u! field_c [9:0] $end
+       $upscope $end
+      $upscope $end
+      $attrbegin pack packed members 5 $end
+      $scope struct [2] $end
+       $var logic 1 v! foo $end
+       $attrbegin array packed bounds 12884901888 $end
+       $scope sv_array bar $end
+        $var logic 32 w! bar[3] [31:0] $end
+        $var logic 32 x! bar[2] [31:0] $end
+        $var logic 32 y! bar[1] [31:0] $end
+        $var logic 32 z! bar[0] [31:0] $end
+       $upscope $end
+       $var logic 16 {! baz [15:0] $end
+       $var logic 128 |! qux [127:0] $end
+       $attrbegin pack packed members 3 $end
+       $scope struct sub_struct $end
+        $var logic 1 }! field_a $end
+        $var logic 6 ~! field_b [5:0] $end
+        $var logic 10 !" field_c [9:0] $end
+       $upscope $end
+      $upscope $end
+      $attrbegin pack packed members 5 $end
+      $scope struct [1] $end
+       $var logic 1 "" foo $end
+       $attrbegin array packed bounds 12884901888 $end
+       $scope sv_array bar $end
+        $var logic 32 #" bar[3] [31:0] $end
+        $var logic 32 $" bar[2] [31:0] $end
+        $var logic 32 %" bar[1] [31:0] $end
+        $var logic 32 &" bar[0] [31:0] $end
+       $upscope $end
+       $var logic 16 '" baz [15:0] $end
+       $var logic 128 (" qux [127:0] $end
+       $attrbegin pack packed members 3 $end
+       $scope struct sub_struct $end
+        $var logic 1 )" field_a $end
+        $var logic 6 *" field_b [5:0] $end
+        $var logic 10 +" field_c [9:0] $end
+       $upscope $end
+      $upscope $end
+      $attrbegin pack packed members 5 $end
+      $scope struct [0] $end
+       $var logic 1 ," foo $end
+       $attrbegin array packed bounds 12884901888 $end
+       $scope sv_array bar $end
+        $var logic 32 -" bar[3] [31:0] $end
+        $var logic 32 ." bar[2] [31:0] $end
+        $var logic 32 /" bar[1] [31:0] $end
+        $var logic 32 0" bar[0] [31:0] $end
+       $upscope $end
+       $var logic 16 1" baz [15:0] $end
+       $var logic 128 2" qux [127:0] $end
+       $attrbegin pack packed members 3 $end
+       $scope struct sub_struct $end
+        $var logic 1 3" field_a $end
+        $var logic 6 4" field_b [5:0] $end
+        $var logic 10 5" field_c [9:0] $end
+       $upscope $end
+      $upscope $end
+     $upscope $end
+     $attrbegin array packed bounds 8589934592 $end
+     $scope sv_array the_packed_structs $end
+      $attrbegin pack packed members 5 $end
+      $scope struct [2] $end
+       $var logic 1 6" foo $end
+       $attrbegin array packed bounds 12884901888 $end
+       $scope sv_array bar $end
+        $var logic 32 7" bar[3] [31:0] $end
+        $var logic 32 8" bar[2] [31:0] $end
+        $var logic 32 9" bar[1] [31:0] $end
+        $var logic 32 :" bar[0] [31:0] $end
+       $upscope $end
+       $var logic 16 ;" baz [15:0] $end
+       $var logic 128 <" qux [127:0] $end
+       $attrbegin pack packed members 3 $end
+       $scope struct sub_struct $end
+        $var logic 1 =" field_a $end
+        $var logic 6 >" field_b [5:0] $end
+        $var logic 10 ?" field_c [9:0] $end
+       $upscope $end
+      $upscope $end
+      $attrbegin pack packed members 5 $end
+      $scope struct [1] $end
+       $var logic 1 @" foo $end
+       $attrbegin array packed bounds 12884901888 $end
+       $scope sv_array bar $end
+        $var logic 32 A" bar[3] [31:0] $end
+        $var logic 32 B" bar[2] [31:0] $end
+        $var logic 32 C" bar[1] [31:0] $end
+        $var logic 32 D" bar[0] [31:0] $end
+       $upscope $end
+       $var logic 16 E" baz [15:0] $end
+       $var logic 128 F" qux [127:0] $end
+       $attrbegin pack packed members 3 $end
+       $scope struct sub_struct $end
+        $var logic 1 G" field_a $end
+        $var logic 6 H" field_b [5:0] $end
+        $var logic 10 I" field_c [9:0] $end
+       $upscope $end
+      $upscope $end
+      $attrbegin pack packed members 5 $end
+      $scope struct [0] $end
+       $var logic 1 J" foo $end
+       $attrbegin array packed bounds 12884901888 $end
+       $scope sv_array bar $end
+        $var logic 32 K" bar[3] [31:0] $end
+        $var logic 32 L" bar[2] [31:0] $end
+        $var logic 32 M" bar[1] [31:0] $end
+        $var logic 32 N" bar[0] [31:0] $end
+       $upscope $end
+       $var logic 16 O" baz [15:0] $end
+       $var logic 128 P" qux [127:0] $end
+       $attrbegin pack packed members 3 $end
+       $scope struct sub_struct $end
+        $var logic 1 Q" field_a $end
+        $var logic 6 R" field_b [5:0] $end
+        $var logic 10 S" field_c [9:0] $end
+       $upscope $end
+      $upscope $end
+     $upscope $end
+     $attrbegin pack packed members 3 $end
+     $scope struct the_local_struct $end
+      $var logic 1 T" abc $end
+      $var logic 1 U" def $end
+      $var logic 1 V" xyz $end
+     $upscope $end
+     $attrbegin pack packed members 3 $end
+     $scope struct const_struct $end
+      $var parameter 1 " abc $end
+      $var parameter 1 % def $end
+      $var parameter 1 " xyz $end
+     $upscope $end
+     $attrbegin pack packed members 3 $end
+     $scope struct the_typedefed_struct $end
+      $var logic 1 W" abc $end
+      $var logic 1 X" def $end
+      $var logic 1 Y" xyz $end
+     $upscope $end
+     $attrbegin pack unpacked members 3 $end
+     $scope struct the_local_unpacked_struct $end
+      $var logic 1 Z" field_a $end
+      $var logic 1 [" field_b $end
+      $var logic 1 \" field_c $end
+     $upscope $end
+     $attrbegin pack packed members 3 $end
+     $scope union the_local_union $end
+      $attrbegin pack packed members 1 $end
+      $scope struct union_a $end
+       $var logic 8 ]" field_0 [7:0] $end
+      $upscope $end
+      $attrbegin pack packed members 2 $end
+      $scope struct union_b $end
+       $var logic 4 ^" field_1 [3:0] $end
+       $var logic 4 _" field_2 [3:0] $end
+      $upscope $end
+      $attrbegin pack packed members 2 $end
+      $scope struct union_c $end
+       $var logic 2 `" field_3 [1:0] $end
+       $var logic 6 a" field_4 [5:0] $end
+      $upscope $end
+     $upscope $end
+     $attrbegin array packed bounds 4294967296 $end
+     $scope sv_array the_logic_array $end
+      $var logic 32 b" the_logic_array[1] [31:0] $end
+      $var logic 32 c" the_logic_array[0] [31:0] $end
+     $upscope $end
+     $attrbegin array packed bounds 4294967296 $end
+     $scope sv_array the_other_logic_array $end
+      $var logic 32 d" the_other_logic_array[1] [31:0] $end
+      $var logic 32 e" the_other_logic_array[0] [31:0] $end
+     $upscope $end
+     $attrbegin array unpacked bounds 4 $end
+     $scope sv_array the_unpacked_array $end
+      $var logic 16 f" the_unpacked_array[0] [15:0] $end
+      $var logic 16 g" the_unpacked_array[1] [15:0] $end
+      $var logic 16 h" the_unpacked_array[2] [15:0] $end
+      $var logic 16 i" the_unpacked_array[3] [15:0] $end
+      $var logic 16 j" the_unpacked_array[4] [15:0] $end
+     $upscope $end
+     $attrbegin array unpacked bounds 2 $end
+     $scope sv_array the_2d_unpacked $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [0] $end
+       $var logic 1 k" the_2d_unpacked[0][0] $end
+       $var logic 1 l" the_2d_unpacked[0][1] $end
+       $var logic 1 m" the_2d_unpacked[0][2] $end
+       $var logic 1 n" the_2d_unpacked[0][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [1] $end
+       $var logic 1 o" the_2d_unpacked[1][0] $end
+       $var logic 1 p" the_2d_unpacked[1][1] $end
+       $var logic 1 q" the_2d_unpacked[1][2] $end
+       $var logic 1 r" the_2d_unpacked[1][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [2] $end
+       $var logic 1 s" the_2d_unpacked[2][0] $end
+       $var logic 1 t" the_2d_unpacked[2][1] $end
+       $var logic 1 u" the_2d_unpacked[2][2] $end
+       $var logic 1 v" the_2d_unpacked[2][3] $end
+      $upscope $end
+     $upscope $end
+     $attrbegin array packed bounds 4294967296 $end
+     $scope sv_array two_fours $end
+      $var parameter 4 N! two_fours[1] [3:0] $end
+      $var parameter 4 O! two_fours[0] [3:0] $end
+     $upscope $end
+     $attrbegin array packed bounds 4294967296 $end
+     $scope sv_array two_fours_var $end
+      $var logic 4 w" two_fours_var[1] [3:0] $end
+      $var logic 4 x" two_fours_var[0] [3:0] $end
+     $upscope $end
+    $upscope $end
+   $upscope $end
+   $scope module gen_loop[2] $end
+    $var int 32 y" loop_cyc [31:0] $end
+    $scope module the_sub $end
+     $var wire 1 z" a $end
+     $var wire 1 {" b $end
+     $var wire 1 |" x $end
+     $attrbegin array unpacked bounds 2 $end
+     $scope sv_array out_2d_unpacked $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [0] $end
+       $var wire 1 }" out_2d_unpacked[0][0] $end
+       $var wire 1 ~" out_2d_unpacked[0][1] $end
+       $var wire 1 !# out_2d_unpacked[0][2] $end
+       $var wire 1 "# out_2d_unpacked[0][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [1] $end
+       $var wire 1 ## out_2d_unpacked[1][0] $end
+       $var wire 1 $# out_2d_unpacked[1][1] $end
+       $var wire 1 %# out_2d_unpacked[1][2] $end
+       $var wire 1 &# out_2d_unpacked[1][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [2] $end
+       $var wire 1 '# out_2d_unpacked[2][0] $end
+       $var wire 1 (# out_2d_unpacked[2][1] $end
+       $var wire 1 )# out_2d_unpacked[2][2] $end
+       $var wire 1 *# out_2d_unpacked[2][3] $end
+      $upscope $end
+     $upscope $end
+     $attrbegin pack packed members 5 $end
+     $scope struct data $end
+      $var wire 1 +# foo $end
+      $attrbegin array packed bounds 12884901888 $end
+      $scope sv_array bar $end
+       $var wire 32 ,# bar[3] [31:0] $end
+       $var wire 32 -# bar[2] [31:0] $end
+       $var wire 32 .# bar[1] [31:0] $end
+       $var wire 32 /# bar[0] [31:0] $end
+      $upscope $end
+      $var wire 16 0# baz [15:0] $end
+      $var wire 128 1# qux [127:0] $end
+      $attrbegin pack packed members 3 $end
+      $scope struct sub_struct $end
+       $var wire 1 2# field_a $end
+       $var wire 6 3# field_b [5:0] $end
+       $var wire 10 4# field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $var wire 32 y" cyc [31:0] $end
+     $var wire 1 ! clk $end
+     $attrbegin pack packed members 5 $end
+     $scope struct the_struct $end
+      $var logic 1 +# foo $end
+      $attrbegin array packed bounds 12884901888 $end
+      $scope sv_array bar $end
+       $var logic 32 ,# bar[3] [31:0] $end
+       $var logic 32 -# bar[2] [31:0] $end
+       $var logic 32 .# bar[1] [31:0] $end
+       $var logic 32 /# bar[0] [31:0] $end
+      $upscope $end
+      $var logic 16 0# baz [15:0] $end
+      $var logic 128 1# qux [127:0] $end
+      $attrbegin pack packed members 3 $end
+      $scope struct sub_struct $end
+       $var logic 1 2# field_a $end
+       $var logic 6 3# field_b [5:0] $end
+       $var logic 10 4# field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $attrbegin array unpacked bounds 12884901888 $end
+     $scope sv_array the_structs $end
+      $attrbegin pack packed members 5 $end
+      $scope struct [3] $end
+       $var logic 1 5# foo $end
+       $attrbegin array packed bounds 12884901888 $end
+       $scope sv_array bar $end
+        $var logic 32 6# bar[3] [31:0] $end
+        $var logic 32 7# bar[2] [31:0] $end
+        $var logic 32 8# bar[1] [31:0] $end
+        $var logic 32 9# bar[0] [31:0] $end
+       $upscope $end
+       $var logic 16 :# baz [15:0] $end
+       $var logic 128 ;# qux [127:0] $end
+       $attrbegin pack packed members 3 $end
+       $scope struct sub_struct $end
+        $var logic 1 <# field_a $end
+        $var logic 6 =# field_b [5:0] $end
+        $var logic 10 ># field_c [9:0] $end
+       $upscope $end
+      $upscope $end
+      $attrbegin pack packed members 5 $end
+      $scope struct [2] $end
+       $var logic 1 ?# foo $end
+       $attrbegin array packed bounds 12884901888 $end
+       $scope sv_array bar $end
+        $var logic 32 @# bar[3] [31:0] $end
+        $var logic 32 A# bar[2] [31:0] $end
+        $var logic 32 B# bar[1] [31:0] $end
+        $var logic 32 C# bar[0] [31:0] $end
+       $upscope $end
+       $var logic 16 D# baz [15:0] $end
+       $var logic 128 E# qux [127:0] $end
+       $attrbegin pack packed members 3 $end
+       $scope struct sub_struct $end
+        $var logic 1 F# field_a $end
+        $var logic 6 G# field_b [5:0] $end
+        $var logic 10 H# field_c [9:0] $end
+       $upscope $end
+      $upscope $end
+      $attrbegin pack packed members 5 $end
+      $scope struct [1] $end
+       $var logic 1 I# foo $end
+       $attrbegin array packed bounds 12884901888 $end
+       $scope sv_array bar $end
+        $var logic 32 J# bar[3] [31:0] $end
+        $var logic 32 K# bar[2] [31:0] $end
+        $var logic 32 L# bar[1] [31:0] $end
+        $var logic 32 M# bar[0] [31:0] $end
+       $upscope $end
+       $var logic 16 N# baz [15:0] $end
+       $var logic 128 O# qux [127:0] $end
+       $attrbegin pack packed members 3 $end
+       $scope struct sub_struct $end
+        $var logic 1 P# field_a $end
+        $var logic 6 Q# field_b [5:0] $end
+        $var logic 10 R# field_c [9:0] $end
+       $upscope $end
+      $upscope $end
+      $attrbegin pack packed members 5 $end
+      $scope struct [0] $end
+       $var logic 1 S# foo $end
+       $attrbegin array packed bounds 12884901888 $end
+       $scope sv_array bar $end
+        $var logic 32 T# bar[3] [31:0] $end
+        $var logic 32 U# bar[2] [31:0] $end
+        $var logic 32 V# bar[1] [31:0] $end
+        $var logic 32 W# bar[0] [31:0] $end
+       $upscope $end
+       $var logic 16 X# baz [15:0] $end
+       $var logic 128 Y# qux [127:0] $end
+       $attrbegin pack packed members 3 $end
+       $scope struct sub_struct $end
+        $var logic 1 Z# field_a $end
+        $var logic 6 [# field_b [5:0] $end
+        $var logic 10 \# field_c [9:0] $end
+       $upscope $end
+      $upscope $end
+     $upscope $end
+     $attrbegin array packed bounds 8589934592 $end
+     $scope sv_array the_packed_structs $end
+      $attrbegin pack packed members 5 $end
+      $scope struct [2] $end
+       $var logic 1 ]# foo $end
+       $attrbegin array packed bounds 12884901888 $end
+       $scope sv_array bar $end
+        $var logic 32 ^# bar[3] [31:0] $end
+        $var logic 32 _# bar[2] [31:0] $end
+        $var logic 32 `# bar[1] [31:0] $end
+        $var logic 32 a# bar[0] [31:0] $end
+       $upscope $end
+       $var logic 16 b# baz [15:0] $end
+       $var logic 128 c# qux [127:0] $end
+       $attrbegin pack packed members 3 $end
+       $scope struct sub_struct $end
+        $var logic 1 d# field_a $end
+        $var logic 6 e# field_b [5:0] $end
+        $var logic 10 f# field_c [9:0] $end
+       $upscope $end
+      $upscope $end
+      $attrbegin pack packed members 5 $end
+      $scope struct [1] $end
+       $var logic 1 g# foo $end
+       $attrbegin array packed bounds 12884901888 $end
+       $scope sv_array bar $end
+        $var logic 32 h# bar[3] [31:0] $end
+        $var logic 32 i# bar[2] [31:0] $end
+        $var logic 32 j# bar[1] [31:0] $end
+        $var logic 32 k# bar[0] [31:0] $end
+       $upscope $end
+       $var logic 16 l# baz [15:0] $end
+       $var logic 128 m# qux [127:0] $end
+       $attrbegin pack packed members 3 $end
+       $scope struct sub_struct $end
+        $var logic 1 n# field_a $end
+        $var logic 6 o# field_b [5:0] $end
+        $var logic 10 p# field_c [9:0] $end
+       $upscope $end
+      $upscope $end
+      $attrbegin pack packed members 5 $end
+      $scope struct [0] $end
+       $var logic 1 q# foo $end
+       $attrbegin array packed bounds 12884901888 $end
+       $scope sv_array bar $end
+        $var logic 32 r# bar[3] [31:0] $end
+        $var logic 32 s# bar[2] [31:0] $end
+        $var logic 32 t# bar[1] [31:0] $end
+        $var logic 32 u# bar[0] [31:0] $end
+       $upscope $end
+       $var logic 16 v# baz [15:0] $end
+       $var logic 128 w# qux [127:0] $end
+       $attrbegin pack packed members 3 $end
+       $scope struct sub_struct $end
+        $var logic 1 x# field_a $end
+        $var logic 6 y# field_b [5:0] $end
+        $var logic 10 z# field_c [9:0] $end
+       $upscope $end
+      $upscope $end
+     $upscope $end
+     $attrbegin pack packed members 3 $end
+     $scope struct the_local_struct $end
+      $var logic 1 {# abc $end
+      $var logic 1 |# def $end
+      $var logic 1 }# xyz $end
+     $upscope $end
+     $attrbegin pack packed members 3 $end
+     $scope struct const_struct $end
+      $var parameter 1 " abc $end
+      $var parameter 1 % def $end
+      $var parameter 1 " xyz $end
+     $upscope $end
+     $attrbegin pack packed members 3 $end
+     $scope struct the_typedefed_struct $end
+      $var logic 1 ~# abc $end
+      $var logic 1 !$ def $end
+      $var logic 1 "$ xyz $end
+     $upscope $end
+     $attrbegin pack unpacked members 3 $end
+     $scope struct the_local_unpacked_struct $end
+      $var logic 1 #$ field_a $end
+      $var logic 1 $$ field_b $end
+      $var logic 1 %$ field_c $end
+     $upscope $end
+     $attrbegin pack packed members 3 $end
+     $scope union the_local_union $end
+      $attrbegin pack packed members 1 $end
+      $scope struct union_a $end
+       $var logic 8 &$ field_0 [7:0] $end
+      $upscope $end
+      $attrbegin pack packed members 2 $end
+      $scope struct union_b $end
+       $var logic 4 '$ field_1 [3:0] $end
+       $var logic 4 ($ field_2 [3:0] $end
+      $upscope $end
+      $attrbegin pack packed members 2 $end
+      $scope struct union_c $end
+       $var logic 2 )$ field_3 [1:0] $end
+       $var logic 6 *$ field_4 [5:0] $end
+      $upscope $end
+     $upscope $end
+     $attrbegin array packed bounds 4294967296 $end
+     $scope sv_array the_logic_array $end
+      $var logic 32 +$ the_logic_array[1] [31:0] $end
+      $var logic 32 ,$ the_logic_array[0] [31:0] $end
+     $upscope $end
+     $attrbegin array packed bounds 4294967296 $end
+     $scope sv_array the_other_logic_array $end
+      $var logic 32 -$ the_other_logic_array[1] [31:0] $end
+      $var logic 32 .$ the_other_logic_array[0] [31:0] $end
+     $upscope $end
+     $attrbegin array unpacked bounds 4 $end
+     $scope sv_array the_unpacked_array $end
+      $var logic 16 /$ the_unpacked_array[0] [15:0] $end
+      $var logic 16 0$ the_unpacked_array[1] [15:0] $end
+      $var logic 16 1$ the_unpacked_array[2] [15:0] $end
+      $var logic 16 2$ the_unpacked_array[3] [15:0] $end
+      $var logic 16 3$ the_unpacked_array[4] [15:0] $end
+     $upscope $end
+     $attrbegin array unpacked bounds 2 $end
+     $scope sv_array the_2d_unpacked $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [0] $end
+       $var logic 1 4$ the_2d_unpacked[0][0] $end
+       $var logic 1 5$ the_2d_unpacked[0][1] $end
+       $var logic 1 6$ the_2d_unpacked[0][2] $end
+       $var logic 1 7$ the_2d_unpacked[0][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [1] $end
+       $var logic 1 8$ the_2d_unpacked[1][0] $end
+       $var logic 1 9$ the_2d_unpacked[1][1] $end
+       $var logic 1 :$ the_2d_unpacked[1][2] $end
+       $var logic 1 ;$ the_2d_unpacked[1][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [2] $end
+       $var logic 1 <$ the_2d_unpacked[2][0] $end
+       $var logic 1 =$ the_2d_unpacked[2][1] $end
+       $var logic 1 >$ the_2d_unpacked[2][2] $end
+       $var logic 1 ?$ the_2d_unpacked[2][3] $end
+      $upscope $end
+     $upscope $end
+     $attrbegin array packed bounds 4294967296 $end
+     $scope sv_array two_fours $end
+      $var parameter 4 N! two_fours[1] [3:0] $end
+      $var parameter 4 O! two_fours[0] [3:0] $end
+     $upscope $end
+     $attrbegin array packed bounds 4294967296 $end
+     $scope sv_array two_fours_var $end
+      $var logic 4 @$ two_fours_var[1] [3:0] $end
+      $var logic 4 A$ two_fours_var[0] [3:0] $end
+     $upscope $end
+    $upscope $end
+   $upscope $end
+   $scope module gen_loop[3] $end
+    $var int 32 B$ loop_cyc [31:0] $end
+    $scope module the_sub $end
+     $var wire 1 C$ a $end
+     $var wire 1 D$ b $end
+     $var wire 1 E$ x $end
+     $attrbegin array unpacked bounds 2 $end
+     $scope sv_array out_2d_unpacked $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [0] $end
+       $var wire 1 F$ out_2d_unpacked[0][0] $end
+       $var wire 1 G$ out_2d_unpacked[0][1] $end
+       $var wire 1 H$ out_2d_unpacked[0][2] $end
+       $var wire 1 I$ out_2d_unpacked[0][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [1] $end
+       $var wire 1 J$ out_2d_unpacked[1][0] $end
+       $var wire 1 K$ out_2d_unpacked[1][1] $end
+       $var wire 1 L$ out_2d_unpacked[1][2] $end
+       $var wire 1 M$ out_2d_unpacked[1][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [2] $end
+       $var wire 1 N$ out_2d_unpacked[2][0] $end
+       $var wire 1 O$ out_2d_unpacked[2][1] $end
+       $var wire 1 P$ out_2d_unpacked[2][2] $end
+       $var wire 1 Q$ out_2d_unpacked[2][3] $end
+      $upscope $end
+     $upscope $end
+     $attrbegin pack packed members 5 $end
+     $scope struct data $end
+      $var wire 1 R$ foo $end
+      $attrbegin array packed bounds 12884901888 $end
+      $scope sv_array bar $end
+       $var wire 32 S$ bar[3] [31:0] $end
+       $var wire 32 T$ bar[2] [31:0] $end
+       $var wire 32 U$ bar[1] [31:0] $end
+       $var wire 32 V$ bar[0] [31:0] $end
+      $upscope $end
+      $var wire 16 W$ baz [15:0] $end
+      $var wire 128 X$ qux [127:0] $end
+      $attrbegin pack packed members 3 $end
+      $scope struct sub_struct $end
+       $var wire 1 Y$ field_a $end
+       $var wire 6 Z$ field_b [5:0] $end
+       $var wire 10 [$ field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $var wire 32 B$ cyc [31:0] $end
+     $var wire 1 ! clk $end
+     $attrbegin pack packed members 5 $end
+     $scope struct the_struct $end
+      $var logic 1 R$ foo $end
+      $attrbegin array packed bounds 12884901888 $end
+      $scope sv_array bar $end
+       $var logic 32 S$ bar[3] [31:0] $end
+       $var logic 32 T$ bar[2] [31:0] $end
+       $var logic 32 U$ bar[1] [31:0] $end
+       $var logic 32 V$ bar[0] [31:0] $end
+      $upscope $end
+      $var logic 16 W$ baz [15:0] $end
+      $var logic 128 X$ qux [127:0] $end
+      $attrbegin pack packed members 3 $end
+      $scope struct sub_struct $end
+       $var logic 1 Y$ field_a $end
+       $var logic 6 Z$ field_b [5:0] $end
+       $var logic 10 [$ field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $attrbegin array unpacked bounds 12884901888 $end
+     $scope sv_array the_structs $end
+      $attrbegin pack packed members 5 $end
+      $scope struct [3] $end
+       $var logic 1 \$ foo $end
+       $attrbegin array packed bounds 12884901888 $end
+       $scope sv_array bar $end
+        $var logic 32 ]$ bar[3] [31:0] $end
+        $var logic 32 ^$ bar[2] [31:0] $end
+        $var logic 32 _$ bar[1] [31:0] $end
+        $var logic 32 `$ bar[0] [31:0] $end
+       $upscope $end
+       $var logic 16 a$ baz [15:0] $end
+       $var logic 128 b$ qux [127:0] $end
+       $attrbegin pack packed members 3 $end
+       $scope struct sub_struct $end
+        $var logic 1 c$ field_a $end
+        $var logic 6 d$ field_b [5:0] $end
+        $var logic 10 e$ field_c [9:0] $end
+       $upscope $end
+      $upscope $end
+      $attrbegin pack packed members 5 $end
+      $scope struct [2] $end
+       $var logic 1 f$ foo $end
+       $attrbegin array packed bounds 12884901888 $end
+       $scope sv_array bar $end
+        $var logic 32 g$ bar[3] [31:0] $end
+        $var logic 32 h$ bar[2] [31:0] $end
+        $var logic 32 i$ bar[1] [31:0] $end
+        $var logic 32 j$ bar[0] [31:0] $end
+       $upscope $end
+       $var logic 16 k$ baz [15:0] $end
+       $var logic 128 l$ qux [127:0] $end
+       $attrbegin pack packed members 3 $end
+       $scope struct sub_struct $end
+        $var logic 1 m$ field_a $end
+        $var logic 6 n$ field_b [5:0] $end
+        $var logic 10 o$ field_c [9:0] $end
+       $upscope $end
+      $upscope $end
+      $attrbegin pack packed members 5 $end
+      $scope struct [1] $end
+       $var logic 1 p$ foo $end
+       $attrbegin array packed bounds 12884901888 $end
+       $scope sv_array bar $end
+        $var logic 32 q$ bar[3] [31:0] $end
+        $var logic 32 r$ bar[2] [31:0] $end
+        $var logic 32 s$ bar[1] [31:0] $end
+        $var logic 32 t$ bar[0] [31:0] $end
+       $upscope $end
+       $var logic 16 u$ baz [15:0] $end
+       $var logic 128 v$ qux [127:0] $end
+       $attrbegin pack packed members 3 $end
+       $scope struct sub_struct $end
+        $var logic 1 w$ field_a $end
+        $var logic 6 x$ field_b [5:0] $end
+        $var logic 10 y$ field_c [9:0] $end
+       $upscope $end
+      $upscope $end
+      $attrbegin pack packed members 5 $end
+      $scope struct [0] $end
+       $var logic 1 z$ foo $end
+       $attrbegin array packed bounds 12884901888 $end
+       $scope sv_array bar $end
+        $var logic 32 {$ bar[3] [31:0] $end
+        $var logic 32 |$ bar[2] [31:0] $end
+        $var logic 32 }$ bar[1] [31:0] $end
+        $var logic 32 ~$ bar[0] [31:0] $end
+       $upscope $end
+       $var logic 16 !% baz [15:0] $end
+       $var logic 128 "% qux [127:0] $end
+       $attrbegin pack packed members 3 $end
+       $scope struct sub_struct $end
+        $var logic 1 #% field_a $end
+        $var logic 6 $% field_b [5:0] $end
+        $var logic 10 %% field_c [9:0] $end
+       $upscope $end
+      $upscope $end
+     $upscope $end
+     $attrbegin array packed bounds 8589934592 $end
+     $scope sv_array the_packed_structs $end
+      $attrbegin pack packed members 5 $end
+      $scope struct [2] $end
+       $var logic 1 &% foo $end
+       $attrbegin array packed bounds 12884901888 $end
+       $scope sv_array bar $end
+        $var logic 32 '% bar[3] [31:0] $end
+        $var logic 32 (% bar[2] [31:0] $end
+        $var logic 32 )% bar[1] [31:0] $end
+        $var logic 32 *% bar[0] [31:0] $end
+       $upscope $end
+       $var logic 16 +% baz [15:0] $end
+       $var logic 128 ,% qux [127:0] $end
+       $attrbegin pack packed members 3 $end
+       $scope struct sub_struct $end
+        $var logic 1 -% field_a $end
+        $var logic 6 .% field_b [5:0] $end
+        $var logic 10 /% field_c [9:0] $end
+       $upscope $end
+      $upscope $end
+      $attrbegin pack packed members 5 $end
+      $scope struct [1] $end
+       $var logic 1 0% foo $end
+       $attrbegin array packed bounds 12884901888 $end
+       $scope sv_array bar $end
+        $var logic 32 1% bar[3] [31:0] $end
+        $var logic 32 2% bar[2] [31:0] $end
+        $var logic 32 3% bar[1] [31:0] $end
+        $var logic 32 4% bar[0] [31:0] $end
+       $upscope $end
+       $var logic 16 5% baz [15:0] $end
+       $var logic 128 6% qux [127:0] $end
+       $attrbegin pack packed members 3 $end
+       $scope struct sub_struct $end
+        $var logic 1 7% field_a $end
+        $var logic 6 8% field_b [5:0] $end
+        $var logic 10 9% field_c [9:0] $end
+       $upscope $end
+      $upscope $end
+      $attrbegin pack packed members 5 $end
+      $scope struct [0] $end
+       $var logic 1 :% foo $end
+       $attrbegin array packed bounds 12884901888 $end
+       $scope sv_array bar $end
+        $var logic 32 ;% bar[3] [31:0] $end
+        $var logic 32 <% bar[2] [31:0] $end
+        $var logic 32 =% bar[1] [31:0] $end
+        $var logic 32 >% bar[0] [31:0] $end
+       $upscope $end
+       $var logic 16 ?% baz [15:0] $end
+       $var logic 128 @% qux [127:0] $end
+       $attrbegin pack packed members 3 $end
+       $scope struct sub_struct $end
+        $var logic 1 A% field_a $end
+        $var logic 6 B% field_b [5:0] $end
+        $var logic 10 C% field_c [9:0] $end
+       $upscope $end
+      $upscope $end
+     $upscope $end
+     $attrbegin pack packed members 3 $end
+     $scope struct the_local_struct $end
+      $var logic 1 D% abc $end
+      $var logic 1 E% def $end
+      $var logic 1 F% xyz $end
+     $upscope $end
+     $attrbegin pack packed members 3 $end
+     $scope struct const_struct $end
+      $var parameter 1 " abc $end
+      $var parameter 1 % def $end
+      $var parameter 1 " xyz $end
+     $upscope $end
+     $attrbegin pack packed members 3 $end
+     $scope struct the_typedefed_struct $end
+      $var logic 1 G% abc $end
+      $var logic 1 H% def $end
+      $var logic 1 I% xyz $end
+     $upscope $end
+     $attrbegin pack unpacked members 3 $end
+     $scope struct the_local_unpacked_struct $end
+      $var logic 1 J% field_a $end
+      $var logic 1 K% field_b $end
+      $var logic 1 L% field_c $end
+     $upscope $end
+     $attrbegin pack packed members 3 $end
+     $scope union the_local_union $end
+      $attrbegin pack packed members 1 $end
+      $scope struct union_a $end
+       $var logic 8 M% field_0 [7:0] $end
+      $upscope $end
+      $attrbegin pack packed members 2 $end
+      $scope struct union_b $end
+       $var logic 4 N% field_1 [3:0] $end
+       $var logic 4 O% field_2 [3:0] $end
+      $upscope $end
+      $attrbegin pack packed members 2 $end
+      $scope struct union_c $end
+       $var logic 2 P% field_3 [1:0] $end
+       $var logic 6 Q% field_4 [5:0] $end
+      $upscope $end
+     $upscope $end
+     $attrbegin array packed bounds 4294967296 $end
+     $scope sv_array the_logic_array $end
+      $var logic 32 R% the_logic_array[1] [31:0] $end
+      $var logic 32 S% the_logic_array[0] [31:0] $end
+     $upscope $end
+     $attrbegin array packed bounds 4294967296 $end
+     $scope sv_array the_other_logic_array $end
+      $var logic 32 T% the_other_logic_array[1] [31:0] $end
+      $var logic 32 U% the_other_logic_array[0] [31:0] $end
+     $upscope $end
+     $attrbegin array unpacked bounds 4 $end
+     $scope sv_array the_unpacked_array $end
+      $var logic 16 V% the_unpacked_array[0] [15:0] $end
+      $var logic 16 W% the_unpacked_array[1] [15:0] $end
+      $var logic 16 X% the_unpacked_array[2] [15:0] $end
+      $var logic 16 Y% the_unpacked_array[3] [15:0] $end
+      $var logic 16 Z% the_unpacked_array[4] [15:0] $end
+     $upscope $end
+     $attrbegin array unpacked bounds 2 $end
+     $scope sv_array the_2d_unpacked $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [0] $end
+       $var logic 1 [% the_2d_unpacked[0][0] $end
+       $var logic 1 \% the_2d_unpacked[0][1] $end
+       $var logic 1 ]% the_2d_unpacked[0][2] $end
+       $var logic 1 ^% the_2d_unpacked[0][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [1] $end
+       $var logic 1 _% the_2d_unpacked[1][0] $end
+       $var logic 1 `% the_2d_unpacked[1][1] $end
+       $var logic 1 a% the_2d_unpacked[1][2] $end
+       $var logic 1 b% the_2d_unpacked[1][3] $end
+      $upscope $end
+      $attrbegin array unpacked bounds 3 $end
+      $scope sv_array [2] $end
+       $var logic 1 c% the_2d_unpacked[2][0] $end
+       $var logic 1 d% the_2d_unpacked[2][1] $end
+       $var logic 1 e% the_2d_unpacked[2][2] $end
+       $var logic 1 f% the_2d_unpacked[2][3] $end
+      $upscope $end
+     $upscope $end
+     $attrbegin array packed bounds 4294967296 $end
+     $scope sv_array two_fours $end
+      $var parameter 4 N! two_fours[1] [3:0] $end
+      $var parameter 4 O! two_fours[0] [3:0] $end
+     $upscope $end
+     $attrbegin array packed bounds 4294967296 $end
+     $scope sv_array two_fours_var $end
+      $var logic 4 g% two_fours_var[1] [3:0] $end
+      $var logic 4 h% two_fours_var[0] [3:0] $end
+     $upscope $end
+    $upscope $end
+   $upscope $end
+   $scope interface the_intf_a $end
+    $var wire 1 ! clk $end
+    $attrbegin array packed bounds 12884901888 $end
+    $scope sv_array data $end
+     $var logic 8 i% data[3] [7:0] $end
+     $var logic 8 j% data[2] [7:0] $end
+     $var logic 8 k% data[1] [7:0] $end
+     $var logic 8 l% data[0] [7:0] $end
+    $upscope $end
+    $var int 32 m% data_typed [31:0] $end
+   $upscope $end
+   $scope interface the_intf_b $end
+    $var wire 1 ! clk $end
+    $attrbegin array packed bounds 12884901888 $end
+    $scope sv_array data $end
+     $var logic 8 n% data[3] [7:0] $end
+     $var logic 8 i% data[2] [7:0] $end
+     $var logic 8 j% data[1] [7:0] $end
+     $var logic 8 k% data[0] [7:0] $end
+    $upscope $end
+    $var int 32 o% data_typed [31:0] $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
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diff --git a/test_regress/t/t_trace_type_dupes_structs_fst.py b/test_regress/t/t_trace_type_dupes_structs_fst.py
new file mode 100755
index 000000000..e2f71b23f
--- /dev/null
+++ b/test_regress/t/t_trace_type_dupes_structs_fst.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_type_dupes_common
+
+test.scenarios('vlt_all')
+
+trace_type_dupes_common.run(test)
diff --git a/test_regress/t/t_trace_type_dupes_structs_saif.out b/test_regress/t/t_trace_type_dupes_structs_saif.out
new file mode 100644
index 000000000..fcaf1e747
--- /dev/null
+++ b/test_regress/t/t_trace_type_dupes_structs_saif.out
@@ -0,0 +1,23407 @@
+// Generated by verilated_saif
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(PROGRAM_NAME "Verilator")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 100)
+ (INSTANCE top
+  (NET
+   (clk (T0 55) (T1 45) (TZ 0) (TX 0) (TB 0) (TC 19))
+  )
+  (INSTANCE pkg
+   (INSTANCE SUB_ONES
+    (NET
+     (field_a (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_b\[0\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_b\[1\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_b\[2\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_b\[3\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_b\[4\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_b\[5\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_c\[0\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_c\[1\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_c\[2\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_c\[3\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_c\[4\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_c\[5\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_c\[6\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_c\[7\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_c\[8\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_c\[9\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+    )
+   )
+   (INSTANCE SUB_ONES
+    (NET
+     (field_a (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_b\[0\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_b\[1\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_b\[2\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_b\[3\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_b\[4\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_b\[5\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_c\[0\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_c\[1\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_c\[2\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_c\[3\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_c\[4\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_c\[5\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_c\[6\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_c\[7\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_c\[8\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (field_c\[9\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+    )
+   )
+   (INSTANCE SUB_ZEROS
+    (NET
+     (field_a (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_b\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_b\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_b\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_b\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_c\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_c\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_c\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_c\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    )
+   )
+   (INSTANCE SUB_ZEROS
+    (NET
+     (field_a (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_b\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_b\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_b\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_b\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_c\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_c\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_c\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_c\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    )
+   )
+  )
+  (INSTANCE t
+   (NET
+    (clk (T0 55) (T1 45) (TZ 0) (TX 0) (TB 0) (TC 19))
+    (cyc\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+    (cyc\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+    (cyc\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+    (cyc\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (cyc\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (x\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+    (x\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+    (x\[2\] (T0 30) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (x\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+   )
+   (INSTANCE gen_loop[0]
+    (NET
+     (loop_cyc\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+     (loop_cyc\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (loop_cyc\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (loop_cyc\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (loop_cyc\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    )
+    (INSTANCE the_sub
+     (NET
+      (a (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+      (b (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (x (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (out_2d_unpacked[0][0] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (out_2d_unpacked[0][1] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (out_2d_unpacked[0][2] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 7))
+      (out_2d_unpacked[0][3] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 8))
+      (out_2d_unpacked[1][0] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (out_2d_unpacked[1][1] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (out_2d_unpacked[1][2] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (out_2d_unpacked[1][3] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 3))
+      (out_2d_unpacked[2][0] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 7))
+      (out_2d_unpacked[2][1] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (out_2d_unpacked[2][2] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (out_2d_unpacked[2][3] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (cyc\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+      (cyc\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (cyc\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (cyc\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (cyc\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (clk (T0 55) (T1 45) (TZ 0) (TX 0) (TB 0) (TC 19))
+      (the_logic_array[1]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+      (the_logic_array[1]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (the_logic_array[1]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (the_logic_array[1]\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (the_logic_array[1]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+      (the_unpacked_array[4]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_2d_unpacked[0][0] (T0 10) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (the_2d_unpacked[0][1] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+      (the_2d_unpacked[0][2] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 8))
+      (the_2d_unpacked[0][3] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+      (the_2d_unpacked[1][0] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+      (the_2d_unpacked[1][1] (T0 10) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (the_2d_unpacked[1][2] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 3))
+      (the_2d_unpacked[1][3] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+      (the_2d_unpacked[2][0] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 8))
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+      (two_fours_var[0]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+      (two_fours_var[0]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (two_fours_var[0]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     )
+     (INSTANCE data
+      (NET
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+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[3\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[3\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE data
+      (NET
+       (foo (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[3\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[1]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[1]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[0]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (baz\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (baz\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[3\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[3\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[32\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[33\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[34\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[35\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[36\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[37\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[38\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[39\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[40\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[41\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[42\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[43\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[44\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[45\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[46\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[47\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[48\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[49\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[50\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[51\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[52\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[53\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[54\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[55\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[56\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[57\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[58\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[59\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[60\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[61\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[62\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[63\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[64\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[65\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[66\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[67\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[68\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[69\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[70\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[71\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[72\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[73\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[74\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[75\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[76\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[77\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[78\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[79\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[80\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[81\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[82\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[83\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[84\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[85\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[86\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[87\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[88\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[89\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[90\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[91\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[92\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[93\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[94\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[95\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[96\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[97\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[98\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[99\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[100\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[101\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[102\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[103\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[104\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[105\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[106\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[107\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[3\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[3\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_struct
+      (NET
+       (foo (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[3\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[3\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[3\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_struct
+      (NET
+       (foo (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[3\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[1]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[1]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[1]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[1]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[0]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[0]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[0]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[0]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[0]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (baz\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (baz\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
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+       (baz\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (baz\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (baz\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (baz\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[40\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[41\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[42\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[43\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[44\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[45\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[46\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[47\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[48\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[49\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[50\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[51\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[52\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[53\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[54\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[55\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[56\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[57\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[58\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[59\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[60\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[61\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[62\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[63\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[64\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[65\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[66\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[67\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[68\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[69\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[70\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[71\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[72\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[73\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[74\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[75\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[76\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[77\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[78\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[79\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[80\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[81\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[82\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[83\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[84\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[85\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[86\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[87\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[88\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[89\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[90\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[91\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[92\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[93\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[94\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[95\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[96\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[97\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[98\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[99\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[100\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[101\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[102\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[103\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[104\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[105\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[106\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[107\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[3\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[3\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_structs[3]
+      (NET
+       (foo (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[0\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[1\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[2\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[3\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[4\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[5\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[6\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[7\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[8\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[9\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[10\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[11\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[12\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[13\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[14\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[15\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[16\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[17\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[18\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[19\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[20\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[21\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[22\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[23\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[24\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[25\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[26\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[27\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[28\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[29\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[30\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[31\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[0\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[1\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[2\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[3\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[4\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[5\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[6\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[7\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[8\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[9\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[10\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[11\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[12\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[13\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[14\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[15\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[16\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[17\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[18\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[19\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[20\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[21\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[22\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[23\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[24\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[25\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[26\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[27\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[28\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[29\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[30\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[31\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[0\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[1\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[2\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[3\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[4\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[5\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[6\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[7\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[8\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[9\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[10\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[11\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[12\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[13\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[14\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[15\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[16\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[17\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[18\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[19\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[20\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[21\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[22\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[23\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[24\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[25\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[26\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[27\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[28\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[29\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[30\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[31\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[0\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[1\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[2\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[3\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[4\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[5\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[6\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[7\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[8\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[9\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[10\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[11\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[12\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[13\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[14\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[15\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[16\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[17\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[18\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[19\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[20\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[21\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[22\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[23\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[24\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[25\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[26\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[27\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[28\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[29\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[30\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[31\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[0\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[1\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[2\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[3\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[4\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[5\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[6\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[7\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[8\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[9\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[10\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[11\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[12\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[13\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[14\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[15\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[0\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[1\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[2\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[3\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[4\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[5\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[6\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[7\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[8\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[9\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[10\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[11\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[12\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[13\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[14\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[15\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[16\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[17\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[18\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[19\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[20\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[21\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[22\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[23\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[24\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[25\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[26\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[27\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[28\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[29\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[30\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[31\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[32\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[33\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[34\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[35\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[36\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[37\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[38\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[39\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[40\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[41\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[42\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[43\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[44\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[45\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[46\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[47\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[48\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[49\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[50\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[51\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[52\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[53\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[54\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[55\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[56\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[57\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[58\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[59\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[60\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[61\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[62\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[63\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[64\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[65\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[66\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[67\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[68\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[69\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[70\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[71\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[72\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[73\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[74\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[75\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[76\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[77\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[78\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[79\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[80\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[81\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[82\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[83\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[84\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[85\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[86\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[87\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[88\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[89\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[90\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[91\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[92\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[93\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[94\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[95\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[96\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[97\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[98\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[99\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[100\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[101\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[102\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[103\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[104\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[105\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[106\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[107\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[108\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[109\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[110\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[111\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[112\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[113\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[114\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[115\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[116\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[117\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[118\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[119\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[120\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[121\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[122\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[123\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[124\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[125\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[126\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[127\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[0\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[1\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[2\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[3\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[4\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[5\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[0\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[1\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[2\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[3\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[4\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[5\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[6\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[7\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[8\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[9\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       )
+      )
+     )
+     (INSTANCE the_structs[2]
+      (NET
+       (foo (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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+       (qux\[120\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[121\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[122\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[123\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[124\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[125\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[126\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[127\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       )
+      )
+     )
+     (INSTANCE the_structs[1]
+      (NET
+       (foo (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
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+       (bar[1]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
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+       (bar[1]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
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+       (bar[1]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
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+       (bar[1]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
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+       (bar[1]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
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+       (bar[0]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
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+       (bar[0]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
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+       (baz\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (baz\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
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+       (baz\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
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+       (qux\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
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+       (qux\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
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+       (qux\[36\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
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+       (qux\[46\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[47\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
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+       (qux\[54\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
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+       (qux\[61\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
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+       (qux\[110\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[111\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[112\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[113\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[114\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[115\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[116\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[117\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[118\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[119\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[120\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[121\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[122\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[123\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[124\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[125\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[126\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[127\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_b\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_b\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_b\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_b\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_b\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_c\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_c\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_c\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_c\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_c\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_c\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_c\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_c\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_c\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       )
+      )
+     )
+     (INSTANCE the_structs[0]
+      (NET
+       (foo (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
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+       (bar[3]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
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+       (bar[3]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
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+       (bar[2]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
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+       (bar[2]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
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+       (bar[2]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
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+       (bar[2]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
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+       (bar[2]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
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+       (bar[2]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
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+       (bar[1]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[1]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
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+       (bar[1]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[1]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[1]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[1]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[1]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[1]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[1]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
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+       (bar[1]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
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+       (bar[0]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[0]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[0]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[0]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[0]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[0]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[0]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[0]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[0]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[0]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[0]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
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+       (bar[0]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
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+       (bar[0]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
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+       (bar[0]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[0]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[0]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[0]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[0]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[0]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[0]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[0]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[0]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[0]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[0]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[0]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (baz\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (baz\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (baz\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (baz\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (baz\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (baz\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (baz\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (baz\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (baz\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (baz\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (baz\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (baz\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (baz\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (baz\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (baz\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (baz\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[32\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[33\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[34\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[35\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[36\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[37\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[38\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[39\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[40\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[41\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[42\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[43\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[44\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[45\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[46\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[47\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[48\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[49\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[50\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[51\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[52\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[53\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[54\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[55\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[56\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[57\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[58\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[59\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[60\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[61\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[62\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[63\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[64\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[65\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[66\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[67\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[68\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[69\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[70\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[71\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[72\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[73\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[74\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[75\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[76\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[77\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[78\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[79\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[80\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[81\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[82\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[83\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[84\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[85\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[86\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[87\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[88\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[89\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[90\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[91\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[92\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[93\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[94\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[95\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[96\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[97\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[98\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[99\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[100\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[101\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[102\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[103\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[104\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[105\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[106\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[107\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[108\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[109\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[110\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[111\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[112\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[113\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[114\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[115\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[116\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[117\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[118\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[119\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[120\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[121\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[122\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[123\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[124\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[125\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[126\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[127\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       )
+      )
+     )
+     (INSTANCE the_structs[3]
+      (NET
+       (foo (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[0\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[1\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[2\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[3\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[4\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[5\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[6\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[7\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[8\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[9\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[10\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[11\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[12\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[13\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[14\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[15\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[16\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[17\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[18\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[19\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[20\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[21\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[22\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[23\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[24\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[25\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[26\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[27\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[28\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[29\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[30\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[31\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[0\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[1\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[2\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[3\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[4\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[5\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[6\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[7\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[8\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[9\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[10\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[11\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[12\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[13\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
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+       (qux\[125\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[126\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[127\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[0\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[1\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[2\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[3\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[4\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[5\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[0\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[1\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[2\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[3\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[4\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[5\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[6\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[7\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[8\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[9\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       )
+      )
+     )
+     (INSTANCE the_structs[2]
+      (NET
+       (foo (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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+       (bar[1]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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+       (bar[1]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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+       (bar[1]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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+       (bar[1]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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+       (bar[0]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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+       (bar[0]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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+       (baz\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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+       (baz\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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+       (baz\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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+       (qux\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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+       (qux\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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+       (qux\[50\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[51\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[52\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[53\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[54\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[55\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[56\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[57\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[58\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[59\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[60\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[61\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[62\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[63\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[64\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[65\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[66\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[67\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[68\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[69\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[70\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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+       (qux\[72\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[73\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[74\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[75\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[76\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[77\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[78\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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+       (qux\[80\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[81\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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+       (qux\[93\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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+       (qux\[102\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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+       (qux\[105\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[106\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[107\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[108\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[109\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[110\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[111\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[112\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[113\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[114\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[115\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[116\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[117\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[118\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[119\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[120\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[121\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[122\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[123\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[124\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[125\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[126\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[127\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       )
+      )
+     )
+     (INSTANCE the_structs[1]
+      (NET
+       (foo (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[3]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (baz\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (baz\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (baz\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (baz\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (baz\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (baz\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (baz\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (baz\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (baz\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (baz\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (baz\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (baz\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (baz\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (baz\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (baz\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (baz\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[32\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[33\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[34\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
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+       (qux\[109\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[110\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[111\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[112\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[113\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[114\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[115\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[116\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[117\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[118\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[119\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[120\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[121\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[122\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[123\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[124\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[125\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[126\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (qux\[127\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_b\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_b\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_b\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_b\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_b\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_c\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_c\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_c\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_c\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_c\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_c\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_c\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_c\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_c\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       )
+      )
+     )
+     (INSTANCE the_structs[0]
+      (NET
+       (foo (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
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+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       )
+      )
+     )
+     (INSTANCE the_packed_structs[2]
+      (NET
+       (foo (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (baz\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (baz\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[55\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[56\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[57\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[58\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[59\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[60\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[61\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[62\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[63\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[64\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[65\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[66\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[67\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[68\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[69\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[70\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[71\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[72\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[73\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[74\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[75\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[76\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[77\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[78\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[79\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[80\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[81\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[82\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[83\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[84\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[85\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[86\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[87\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[88\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[89\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[91\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[92\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[93\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[101\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[102\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[103\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[104\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[105\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[106\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[107\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_packed_structs[1]
+      (NET
+       (foo (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[1]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[1]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[32\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[33\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[34\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[35\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[36\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[38\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[39\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[40\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[41\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[42\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[43\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[44\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[45\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[46\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[47\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[48\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[49\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[50\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[51\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[52\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[53\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[54\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[55\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[56\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[57\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[58\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[59\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[60\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[61\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[62\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[63\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[66\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[67\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[68\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[71\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[72\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[73\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[74\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[75\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[82\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[88\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[89\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[91\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[92\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[93\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[102\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[103\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[104\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[105\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[106\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[107\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_packed_structs[0]
+      (NET
+       (foo (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+        (field_b\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_packed_structs[2]
+      (NET
+       (foo (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[2]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[61\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[62\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[63\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[64\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[65\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[66\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[67\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[68\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[69\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[70\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[71\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[72\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[73\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[74\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[75\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[76\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[77\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[78\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[79\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[80\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[81\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[82\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[83\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[84\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[85\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[86\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[87\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[88\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[89\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[92\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[102\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[103\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[106\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[107\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_packed_structs[1]
+      (NET
+       (foo (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[1]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[1]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[1]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[0]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[0]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[0]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[0]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[0]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[32\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[33\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[34\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[35\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[36\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[37\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[38\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[39\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[40\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[41\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[42\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[43\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[44\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[45\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[46\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[47\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[48\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[49\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[50\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[51\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[52\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[53\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[54\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[55\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[56\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[57\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[58\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[59\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[60\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[61\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[62\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[63\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[64\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[65\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[66\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[67\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[68\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[69\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[70\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[71\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[72\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[73\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[74\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[75\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[76\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[77\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[78\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[79\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[80\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[81\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[82\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[83\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[84\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[85\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[86\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[87\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[88\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[89\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[90\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[91\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[92\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[93\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[94\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[95\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[96\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[97\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[98\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[99\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[100\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[101\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[102\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[103\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[104\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[105\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[106\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[107\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_packed_structs[0]
+      (NET
+       (foo (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_local_struct
+      (NET
+       (abc (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (def (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (xyz (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+      )
+     )
+     (INSTANCE the_local_struct
+      (NET
+       (abc (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (def (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (xyz (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+      )
+     )
+     (INSTANCE const_struct
+      (NET
+       (abc (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (def (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (xyz (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+      )
+     )
+     (INSTANCE const_struct
+      (NET
+       (abc (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (def (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (xyz (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+      )
+     )
+     (INSTANCE the_typedefed_struct
+      (NET
+       (abc (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (def (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (xyz (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+      )
+     )
+     (INSTANCE the_typedefed_struct
+      (NET
+       (abc (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (def (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (xyz (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+      )
+     )
+     (INSTANCE the_local_unpacked_struct
+      (NET
+       (field_a (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (field_b (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (field_c (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+      )
+     )
+     (INSTANCE the_local_unpacked_struct
+      (NET
+       (field_a (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (field_b (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (field_c (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+      )
+     )
+     (INSTANCE the_local_union
+      (INSTANCE union_a
+       (NET
+        (field_0\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_0\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_0\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_0\[3\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_0\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_0\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_0\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_0\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+      (INSTANCE union_b
+       (NET
+        (field_1\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_1\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_1\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_1\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_2\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_2\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_2\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_2\[3\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+       )
+      )
+      (INSTANCE union_c
+       (NET
+        (field_3\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_3\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_4\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_4\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+        (field_4\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_4\[3\] (T0 90) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_4\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_4\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+    )
+   )
+   (INSTANCE gen_loop[1]
+    (NET
+     (loop_cyc\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 11))
+     (loop_cyc\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (loop_cyc\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (loop_cyc\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (loop_cyc\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    )
+    (INSTANCE the_sub
+     (NET
+      (a (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (b (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (x (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+      (out_2d_unpacked[0][0] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (out_2d_unpacked[0][1] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (out_2d_unpacked[0][2] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 8))
+      (out_2d_unpacked[0][3] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 9))
+      (out_2d_unpacked[1][0] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (out_2d_unpacked[1][1] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (out_2d_unpacked[1][2] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+      (out_2d_unpacked[1][3] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 4))
+      (out_2d_unpacked[2][0] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 8))
+      (out_2d_unpacked[2][1] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+      (out_2d_unpacked[2][2] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (out_2d_unpacked[2][3] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (cyc\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 11))
+      (cyc\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (cyc\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (cyc\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (cyc\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (clk (T0 55) (T1 45) (TZ 0) (TX 0) (TB 0) (TC 19))
+      (the_logic_array[1]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+      (the_logic_array[1]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (the_logic_array[1]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (the_logic_array[1]\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (the_logic_array[1]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+      (the_logic_array[0]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (the_logic_array[0]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (the_logic_array[0]\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (the_logic_array[0]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_other_logic_array[1]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+      (the_other_logic_array[1]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
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+      (the_unpacked_array[4]\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
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+      (the_unpacked_array[4]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_unpacked_array[4]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_2d_unpacked[0][0] (T0 10) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (the_2d_unpacked[0][1] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+      (the_2d_unpacked[0][2] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 7))
+      (the_2d_unpacked[0][3] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 8))
+      (the_2d_unpacked[1][0] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+      (the_2d_unpacked[1][1] (T0 10) (T1 90) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (the_2d_unpacked[1][2] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 4))
+      (the_2d_unpacked[1][3] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 5))
+      (the_2d_unpacked[2][0] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 7))
+      (the_2d_unpacked[2][1] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 4))
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+      (the_2d_unpacked[2][3] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 2))
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+      (two_fours[1]\[3\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
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+      (two_fours[0]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (two_fours[0]\[3\] (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
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+      (two_fours_var[1]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (two_fours_var[1]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (two_fours_var[1]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (two_fours_var[0]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (two_fours_var[0]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (two_fours_var[0]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (two_fours_var[0]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     )
+     (INSTANCE data
+      (NET
+       (foo (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
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+       (bar[3]\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[93\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[94\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[95\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[101\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[102\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[103\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[106\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE data
+      (NET
+       (foo (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[1]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[1]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[1]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[1]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[1]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[0]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[0]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[0]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[0]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[0]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (baz\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (baz\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
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+       (qux\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[32\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[33\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[34\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[35\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[36\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[37\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[38\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[39\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[40\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[41\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[42\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[43\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[44\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[45\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[46\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[47\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[48\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[49\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[50\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[51\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[52\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[53\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[54\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[55\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[56\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[57\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[58\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[59\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[60\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[61\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[62\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[63\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[64\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[65\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[66\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[67\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[68\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[69\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[70\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[71\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[72\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[73\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[74\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[75\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[76\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[77\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[78\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[79\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[80\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[81\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[82\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[83\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[84\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[85\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[86\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[87\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[88\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[89\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[90\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[91\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[92\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[93\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[94\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[95\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[96\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[97\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[98\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[99\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[100\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[101\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[102\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[103\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[104\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[105\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[106\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[107\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_struct
+      (NET
+       (foo (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[1]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[0]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[0]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (baz\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (baz\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[32\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[33\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[34\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[35\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[36\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[37\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[38\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[39\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[40\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[41\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[42\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[43\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[44\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[45\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[46\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[47\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[48\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[49\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[50\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[51\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[52\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[53\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[54\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[55\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[56\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[57\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[58\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[59\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[60\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[61\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[62\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[63\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[64\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[65\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[66\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[67\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[68\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[69\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[70\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[71\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[72\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[73\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[74\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[75\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[76\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[77\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[78\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[79\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[80\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[81\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[82\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[83\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[84\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[85\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[86\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[87\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[88\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[89\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[90\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[91\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[92\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[93\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[94\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[95\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[96\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[97\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[98\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[99\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[100\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[101\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[102\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[103\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[104\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[105\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[106\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[107\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_struct
+      (NET
+       (foo (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[97\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[98\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[99\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[100\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[101\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[102\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[103\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[104\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[105\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[106\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[107\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_structs[3]
+      (NET
+       (foo (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[0\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[1\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[2\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[4\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[5\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[6\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[7\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[8\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[9\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[10\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[11\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[12\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[13\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[14\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[15\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[16\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[17\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[18\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[19\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[20\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[21\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[22\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[23\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[24\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[25\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[26\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[27\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[28\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[29\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[30\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[31\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[0\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[1\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[2\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[4\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[5\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[6\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[7\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[8\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[9\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[10\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[11\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[12\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[13\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[14\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[15\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[16\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[17\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[18\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[19\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[20\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[21\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[22\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[23\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[24\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[25\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[26\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[27\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[28\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[29\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[30\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[31\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[0\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[1\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[2\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[4\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[5\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[6\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[7\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[8\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[9\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[10\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[11\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[12\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[13\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[14\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[15\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[16\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[17\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[18\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[19\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[20\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[21\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[22\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[23\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[24\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[25\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[26\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[27\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[28\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[29\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[30\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[31\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[0\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[1\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[2\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[4\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[5\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[6\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[7\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[8\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[9\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[10\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[11\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[12\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[13\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[14\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[15\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[16\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[17\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[18\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[19\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[20\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[21\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[22\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[23\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[24\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[25\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[26\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[27\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[28\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[29\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[30\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[31\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[0\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[1\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[2\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[4\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[5\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[6\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[7\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[8\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[9\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[10\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[11\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[12\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[13\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[14\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[15\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[0\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[1\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[2\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[4\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[5\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[6\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[7\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[8\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[9\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[10\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[11\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[12\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[13\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[14\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[15\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[16\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[17\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[18\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[19\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[20\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[21\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[22\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[23\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[24\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[25\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[26\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[27\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[28\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[29\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[30\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[31\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[32\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[33\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[34\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[35\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[36\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[37\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[38\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[39\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[40\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[41\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[42\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[43\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[44\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[45\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[46\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[47\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[48\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[49\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[50\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[51\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[52\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[53\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[54\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[55\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[56\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[57\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[58\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[59\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[60\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[61\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[62\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[63\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[64\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[65\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[66\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[67\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[68\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[69\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[70\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[71\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[72\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[73\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[74\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[75\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[76\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[77\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[78\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[79\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[80\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[81\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[82\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[83\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[84\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[85\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[86\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[87\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[88\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[89\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[90\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[91\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[92\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[93\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[94\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[95\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[96\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[97\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[98\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[99\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[100\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[101\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[102\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[103\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[104\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[105\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[106\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[107\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[108\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[109\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[110\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[111\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[112\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[113\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[114\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[115\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[116\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[117\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[118\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[119\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[120\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[121\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[122\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[123\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[124\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[125\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[126\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[127\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[0\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[1\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[2\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[4\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[5\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[0\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[1\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[2\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[4\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[5\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[6\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[7\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[8\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[9\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       )
+      )
+     )
+     (INSTANCE the_structs[2]
+      (NET
+       (foo (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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+       (bar[0]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[32\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[33\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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+       (qux\[102\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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+       (qux\[104\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[105\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[106\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[107\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[108\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[109\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[110\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[111\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[112\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[113\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[114\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[115\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[116\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[117\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[118\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[119\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[120\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[121\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[122\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[123\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[124\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[125\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[126\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[127\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       )
+      )
+     )
+     (INSTANCE the_structs[1]
+      (NET
+       (foo (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
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+       (qux\[102\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[103\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[104\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[105\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[106\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[107\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[108\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[109\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[110\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[111\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[112\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[113\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[114\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[115\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[116\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[117\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[118\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[119\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[120\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[121\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[122\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[123\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[124\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[125\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[126\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[127\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       )
+      )
+     )
+     (INSTANCE the_structs[0]
+      (NET
+       (foo (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[10\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[11\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[12\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[13\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[14\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[15\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[16\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[17\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[18\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[19\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[20\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[21\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[22\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[23\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[24\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[25\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[26\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[27\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[28\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[29\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[30\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[31\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[10\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[11\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[12\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[13\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[14\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[15\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[16\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[17\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[18\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[19\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[20\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[21\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[22\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[23\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[24\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[25\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[26\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[27\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[28\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[29\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[30\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[31\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[10\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[11\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[12\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[13\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
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+       (bar[1]\[15\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[16\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[17\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[18\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[19\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[20\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[21\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[22\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[23\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[24\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[25\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[26\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
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+       (bar[1]\[29\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
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+       (bar[1]\[31\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
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+       (bar[0]\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
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+       (baz\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (baz\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
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+       (baz\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
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+       (baz\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
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+       (baz\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
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+       (baz\[11\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (baz\[12\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (baz\[13\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (baz\[14\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (baz\[15\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
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+       (qux\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
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+       (qux\[10\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
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+       (qux\[15\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[16\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[17\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[18\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[19\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[20\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[21\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[22\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[23\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[24\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[25\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[26\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[27\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[28\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[29\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[30\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[31\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[32\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[33\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[34\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[35\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[36\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[37\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[38\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[39\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[40\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[41\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[42\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[43\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[44\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[45\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[46\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[47\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[48\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[49\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[50\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[51\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[52\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[53\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[54\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[55\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[56\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[57\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[58\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[59\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[60\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[61\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[62\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[63\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[64\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[65\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[66\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[67\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[68\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[69\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[70\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[71\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[72\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[73\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[74\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[75\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[76\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[77\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[78\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[79\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[80\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[81\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[82\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[83\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[84\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[85\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[86\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[87\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[88\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[89\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[90\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[91\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[92\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[93\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[94\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[95\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[96\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[97\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[98\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[99\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[100\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[101\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[102\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[103\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[104\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[105\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[106\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[107\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[108\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[109\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[110\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[111\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[112\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[113\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[114\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[115\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[116\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[117\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[118\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[119\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[120\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[121\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[122\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[123\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[124\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[125\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[126\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[127\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       )
+      )
+     )
+     (INSTANCE the_structs[3]
+      (NET
+       (foo (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[0\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[1\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[2\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[4\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[5\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[6\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[7\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[8\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[9\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[10\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[11\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[12\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[13\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[14\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[15\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[16\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[17\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[18\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[19\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[20\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[21\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[22\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[23\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[24\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[25\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[26\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[27\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[28\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[29\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[30\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[31\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[0\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[1\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[2\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[4\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[5\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[6\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[7\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[8\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[9\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[10\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[11\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[12\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[13\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[14\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[15\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[16\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[17\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[18\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[19\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[20\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[21\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[22\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[23\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[24\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[25\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[26\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[27\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[28\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[29\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[30\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[31\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[0\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[1\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[2\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[4\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[5\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[6\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[7\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[8\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[9\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[10\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[11\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[12\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[13\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[14\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[15\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[16\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[17\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[18\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[19\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[20\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[21\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[22\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[23\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[24\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[25\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[26\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[27\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[28\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[29\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[30\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[31\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[0\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[1\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[2\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[4\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[5\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[6\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[7\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[8\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[9\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[10\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[11\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[12\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[13\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[14\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[15\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[16\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[17\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[18\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[19\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[20\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[21\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[22\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[23\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[24\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[25\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[26\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[27\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[28\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[29\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[30\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[31\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[0\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[1\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[2\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[4\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[5\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[6\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[7\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[8\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[9\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[10\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[11\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[12\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[13\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[14\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[15\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[0\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[1\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[2\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[4\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[5\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[6\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[7\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[8\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[9\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[10\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[11\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[12\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[13\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[14\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[15\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[16\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[17\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[18\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[19\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[20\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[21\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[22\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[23\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[24\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[25\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[26\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[27\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[28\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[29\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[30\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[31\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[32\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[33\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[34\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[35\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[36\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[37\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[38\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[39\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[40\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[41\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[42\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[43\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[44\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[45\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[46\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[47\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[48\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[49\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[50\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[51\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[52\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[53\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[54\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[55\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[56\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[57\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[58\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[59\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[60\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[61\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[62\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[63\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[64\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[65\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[66\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[67\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[68\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[69\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[70\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[71\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[72\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[73\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[74\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[75\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[76\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[77\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[78\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[79\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[80\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[81\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[82\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[83\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[84\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[85\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[86\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[87\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[88\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[89\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[90\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[91\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[92\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[93\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[94\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[95\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[96\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[97\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[98\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[99\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[100\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[101\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[102\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[103\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[104\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[105\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[106\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[107\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[108\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[109\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[110\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[111\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[112\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[113\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[114\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[115\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[116\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[117\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[118\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[119\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[120\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[121\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[122\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[123\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[124\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[125\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[126\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[127\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[0\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[1\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[2\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[4\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[5\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[0\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[1\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[2\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[4\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[5\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[6\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[7\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[8\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[9\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       )
+      )
+     )
+     (INSTANCE the_structs[2]
+      (NET
+       (foo (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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+       (qux\[107\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[108\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[109\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[110\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[111\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[112\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[113\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[114\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[115\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[116\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[117\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[118\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[119\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[120\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[121\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[122\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[123\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[124\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[125\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[126\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[127\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       )
+      )
+     )
+     (INSTANCE the_structs[1]
+      (NET
+       (foo (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[1]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[1]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[1]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[1]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[1]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[1]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[1]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[1]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[1]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[1]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[1]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[1]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
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+       (baz\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (baz\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
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+       (qux\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
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+       (qux\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
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+       (qux\[112\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[113\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[114\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
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+       (qux\[118\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
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+       (qux\[120\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[121\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
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+       (qux\[123\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[124\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
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+       (qux\[126\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[127\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       )
+      )
+     )
+     (INSTANCE the_structs[0]
+      (NET
+       (foo (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[10\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[11\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[12\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[13\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[14\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[15\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[16\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[17\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[18\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[19\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[20\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[21\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[22\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[23\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[24\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[25\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[26\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[27\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[28\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[29\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[30\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[31\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
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+       (bar[2]\[11\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
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+       (bar[2]\[13\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[14\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[15\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[16\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[17\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[18\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[19\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[20\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[21\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[22\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[23\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[24\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[25\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[26\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[27\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[28\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[29\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[30\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[31\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[10\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[11\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[12\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
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+       (bar[1]\[15\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
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+       (bar[1]\[18\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
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+       (bar[1]\[25\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
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+       (bar[1]\[31\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
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+       (bar[0]\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[10\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[11\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[12\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[13\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[14\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[15\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[16\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[17\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[18\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[19\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[20\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[21\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[22\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[23\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[24\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[25\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[26\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[27\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[28\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[29\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[30\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[31\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (baz\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (baz\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (baz\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (baz\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (baz\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (baz\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (baz\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (baz\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (baz\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (baz\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (baz\[10\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (baz\[11\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (baz\[12\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (baz\[13\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (baz\[14\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (baz\[15\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[10\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[11\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[12\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[13\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[14\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[15\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[16\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[17\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[18\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[19\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[20\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[21\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[22\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[23\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[24\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[25\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[26\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[27\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[28\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[29\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[30\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[31\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[32\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[33\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[34\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[35\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[36\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[37\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[38\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[39\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[40\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[41\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[42\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[43\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[44\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[45\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[46\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[47\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[48\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[49\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[50\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[51\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[52\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[53\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[54\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[55\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[56\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[57\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[58\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[59\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[60\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[61\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[62\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[63\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[64\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[65\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[66\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[67\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[68\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[69\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[70\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[71\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[72\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[73\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[74\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[75\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[76\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
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+       (qux\[78\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[79\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
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+       (qux\[81\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[82\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
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+       (qux\[84\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
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+       (qux\[87\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[88\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[89\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[90\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[91\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[92\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[93\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[94\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[95\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[96\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[97\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[98\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[99\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[100\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[101\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[102\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[103\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[104\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[105\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[106\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[107\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[108\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[109\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[110\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[111\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[112\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[113\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[114\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[115\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[116\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[117\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[118\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[119\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[120\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[121\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[122\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[123\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[124\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[125\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[126\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[127\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       )
+      )
+     )
+     (INSTANCE the_packed_structs[2]
+      (NET
+       (foo (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_packed_structs[1]
+      (NET
+       (foo (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[1]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[1]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[1]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[0]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (baz\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (baz\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (baz\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[35\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[37\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[38\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[39\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[40\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[41\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[42\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[43\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[44\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[45\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[46\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[47\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[48\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[49\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[50\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[51\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[52\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[53\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[54\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[55\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[56\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[57\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[59\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[60\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[61\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[102\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[106\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[107\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_packed_structs[0]
+      (NET
+       (foo (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[32\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[33\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[34\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[35\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[36\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[37\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[38\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[39\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[40\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[41\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[42\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[43\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[44\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[45\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[46\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[47\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[48\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[49\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[50\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[51\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[52\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[53\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[54\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[55\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[56\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[57\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[58\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[59\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[60\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[61\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[62\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[63\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[64\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[65\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[66\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[67\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[68\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[69\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[70\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[71\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[72\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[73\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[74\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[75\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[76\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[77\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[78\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[79\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[80\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[81\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[82\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[83\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[84\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[85\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[86\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[87\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[88\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[89\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[90\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[91\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[92\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[93\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[94\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[95\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[96\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[97\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[98\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[99\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[100\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[101\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[102\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[103\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[104\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[105\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[106\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[107\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_packed_structs[2]
+      (NET
+       (foo (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_packed_structs[1]
+      (NET
+       (foo (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[1]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[1]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[0]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[0]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (baz\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (baz\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (baz\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[38\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[40\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[41\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[42\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[43\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[44\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[45\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[46\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[47\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[48\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[49\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[50\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[51\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[52\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[53\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[54\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[55\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[56\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[57\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[58\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[59\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[60\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[61\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[106\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[107\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_packed_structs[0]
+      (NET
+       (foo (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[32\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[33\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[34\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[35\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[36\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[37\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[38\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[39\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[40\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[41\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[42\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[43\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[44\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[45\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[46\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[47\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[48\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[49\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[50\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[51\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[52\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[53\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[54\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[55\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[56\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[57\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[58\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[59\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[60\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[61\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[62\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[63\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[64\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[65\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[66\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[67\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[68\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[69\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[70\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[71\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[72\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[73\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[74\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[75\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[76\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[77\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[78\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[79\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[80\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[81\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[82\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[83\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[84\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[85\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[86\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[87\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[88\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[89\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[90\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[91\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[92\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[93\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[94\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[95\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[96\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[97\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[98\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[99\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[100\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[101\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[102\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[103\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[104\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[105\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[106\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[107\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_local_struct
+      (NET
+       (abc (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (def (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (xyz (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+      )
+     )
+     (INSTANCE the_local_struct
+      (NET
+       (abc (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (def (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (xyz (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+      )
+     )
+     (INSTANCE const_struct
+      (NET
+       (abc (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (def (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (xyz (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+      )
+     )
+     (INSTANCE const_struct
+      (NET
+       (abc (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (def (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (xyz (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+      )
+     )
+     (INSTANCE the_typedefed_struct
+      (NET
+       (abc (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (def (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (xyz (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+      )
+     )
+     (INSTANCE the_typedefed_struct
+      (NET
+       (abc (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (def (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (xyz (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+      )
+     )
+     (INSTANCE the_local_unpacked_struct
+      (NET
+       (field_a (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (field_b (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (field_c (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+      )
+     )
+     (INSTANCE the_local_unpacked_struct
+      (NET
+       (field_a (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (field_b (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (field_c (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+      )
+     )
+     (INSTANCE the_local_union
+      (INSTANCE union_a
+       (NET
+        (field_0\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_0\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_0\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_0\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_0\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_0\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_0\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_0\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+      (INSTANCE union_b
+       (NET
+        (field_1\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_1\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_1\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_1\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_2\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_2\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_2\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_2\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+       )
+      )
+      (INSTANCE union_c
+       (NET
+        (field_3\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_3\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_4\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_4\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_4\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_4\[3\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_4\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_4\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+    )
+   )
+   (INSTANCE gen_loop[2]
+    (NET
+     (loop_cyc\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+     (loop_cyc\[1\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
+     (loop_cyc\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (loop_cyc\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (loop_cyc\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    )
+    (INSTANCE the_sub
+     (NET
+      (a (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+      (b (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (x (T0 30) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (out_2d_unpacked[0][0] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (out_2d_unpacked[0][1] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+      (out_2d_unpacked[0][2] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 7))
+      (out_2d_unpacked[0][3] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 8))
+      (out_2d_unpacked[1][0] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+      (out_2d_unpacked[1][1] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (out_2d_unpacked[1][2] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 3))
+      (out_2d_unpacked[1][3] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 4))
+      (out_2d_unpacked[2][0] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 7))
+      (out_2d_unpacked[2][1] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 3))
+      (out_2d_unpacked[2][2] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (out_2d_unpacked[2][3] (T0 30) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (cyc\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+      (cyc\[1\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
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+      (cyc\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (cyc\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+      (cyc\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (cyc\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (clk (T0 55) (T1 45) (TZ 0) (TX 0) (TB 0) (TC 19))
+      (the_logic_array[1]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+      (the_logic_array[1]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+      (the_logic_array[1]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+      (the_logic_array[1]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (the_logic_array[1]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+      (the_logic_array[1]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+      (the_logic_array[1]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+      (the_logic_array[1]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+      (the_logic_array[1]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[1]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+      (the_logic_array[0]\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (the_logic_array[0]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_logic_array[0]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+      (the_logic_array[0]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_other_logic_array[1]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+      (the_other_logic_array[1]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
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+      (the_other_logic_array[1]\[5\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (the_other_logic_array[1]\[6\] (T0 80) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
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+      (the_other_logic_array[1]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_other_logic_array[1]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_other_logic_array[1]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+      (the_other_logic_array[1]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+      (the_other_logic_array[1]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+      (the_other_logic_array[0]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 3))
+      (the_other_logic_array[0]\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (the_other_logic_array[0]\[4\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (the_other_logic_array[0]\[5\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (the_other_logic_array[0]\[6\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 2))
+      (the_other_logic_array[0]\[7\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (the_other_logic_array[0]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_other_logic_array[0]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (the_other_logic_array[0]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+      (two_fours_var[0]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     )
+     (INSTANCE data
+      (NET
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+       (bar[1]\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[0]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[3\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (baz\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (baz\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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+       (qux\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[102\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[103\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[104\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[105\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[106\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[107\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE data
+      (NET
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+       (bar[3]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
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+       (bar[3]\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[75\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[76\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[77\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[78\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[79\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[80\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[81\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[82\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[83\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[84\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[85\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[86\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[87\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[88\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[89\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[90\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[91\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[92\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[93\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[94\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[95\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[96\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[97\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[98\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[99\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[100\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[101\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[102\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[103\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[104\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[105\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[106\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[107\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_struct
+      (NET
+       (foo (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[1]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[0]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[3\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (baz\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (baz\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[32\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[33\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[34\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[35\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[36\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[37\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[38\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[39\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[40\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[41\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[42\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[43\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[44\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[45\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[46\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[47\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[48\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[49\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[50\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[51\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[52\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[53\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[54\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[55\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[56\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[57\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[58\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[59\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[60\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[61\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[62\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[63\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[64\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[65\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[66\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[67\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[68\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[69\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[70\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[71\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[72\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[73\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[74\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[75\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[76\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[77\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[78\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[79\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[80\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[81\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[82\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[83\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[84\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[85\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[86\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[87\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[88\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[89\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[90\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[91\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[92\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[93\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[94\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[95\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[96\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[97\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[98\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[99\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[100\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[101\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[102\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[103\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[104\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[105\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[106\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[107\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_struct
+      (NET
+       (foo (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[1]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[1]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[0]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[0]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[3\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (baz\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (baz\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[32\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[33\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[34\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[35\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[36\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[37\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[38\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[39\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[40\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[41\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[42\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[43\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[44\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[45\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[46\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[47\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[48\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[49\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[50\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[51\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[52\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[53\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[54\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[55\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[56\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[57\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[58\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[59\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[60\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[61\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[62\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[63\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[64\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[65\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[66\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[67\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[68\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[69\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[70\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[71\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[72\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[73\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[74\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[75\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[76\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[77\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[78\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[79\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[80\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[81\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[82\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[83\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[84\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[85\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[86\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[87\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[88\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[89\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[90\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[91\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[92\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[93\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[94\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[95\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[96\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[97\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[98\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[99\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[100\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[101\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[102\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[103\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[104\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[105\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[106\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[107\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_structs[3]
+      (NET
+       (foo (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[0\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[1\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[2\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
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+       (qux\[80\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[81\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[82\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[83\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[84\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[85\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[86\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[87\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[88\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[89\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[90\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[91\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[92\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[93\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[94\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[95\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[96\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[97\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[98\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[99\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[100\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[101\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[102\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[103\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[104\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[105\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[106\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[107\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[108\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[109\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[110\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[111\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[112\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[113\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[114\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[115\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[116\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[117\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[118\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[119\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[120\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[121\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[122\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[123\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[124\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[125\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[126\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[127\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[0\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[1\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[2\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[4\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[5\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[0\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[1\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[2\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[4\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[5\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[6\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[7\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[8\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[9\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       )
+      )
+     )
+     (INSTANCE the_structs[2]
+      (NET
+       (foo (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[32\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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+       (qux\[107\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[108\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[109\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[110\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[111\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[112\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[113\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[114\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[115\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[116\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[117\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[118\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[119\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[120\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[121\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[122\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[123\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[124\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[125\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[126\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[127\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       )
+      )
+     )
+     (INSTANCE the_structs[1]
+      (NET
+       (foo (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[10\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[11\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[12\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[13\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[14\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[15\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[16\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[17\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[18\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[19\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[20\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[21\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[22\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[23\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[24\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[25\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[26\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[27\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[28\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[29\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[30\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[31\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[10\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[11\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[12\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[13\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[14\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[15\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[16\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[17\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[18\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[19\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[20\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[21\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[22\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[23\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[24\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[25\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[26\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[27\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[28\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[29\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[30\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[2]\[31\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[1]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[1]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[1]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[1]\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[1]\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[1]\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[1]\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[1]\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[1]\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[1]\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[1]\[10\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[1]\[11\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[1]\[12\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[1]\[13\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
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+       (qux\[109\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[110\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[111\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[112\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[113\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[114\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[115\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[116\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[117\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[118\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[119\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[120\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[121\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[122\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[123\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[124\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[125\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[126\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[127\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       )
+      )
+     )
+     (INSTANCE the_structs[0]
+      (NET
+       (foo (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
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+       (qux\[85\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[86\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[87\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[88\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[89\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[90\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[91\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[92\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[93\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[94\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[95\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[96\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[97\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[98\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[99\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[100\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[101\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[102\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[103\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[104\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[105\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[106\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[107\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[108\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[109\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[110\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[111\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[112\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[113\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[114\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[115\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[116\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[117\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[118\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[119\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[120\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[121\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[122\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[123\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[124\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[125\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[126\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[127\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       )
+      )
+     )
+     (INSTANCE the_structs[3]
+      (NET
+       (foo (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[0\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[1\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[2\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[4\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[5\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[6\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[7\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[8\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[9\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[10\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[11\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[12\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[13\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[14\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[15\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[16\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[17\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[18\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[19\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[20\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[21\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[22\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[23\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[24\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[25\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[26\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[27\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[28\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[29\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[30\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[31\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[0\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[1\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[2\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[4\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[5\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[6\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[7\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[8\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[9\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[10\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[11\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[12\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[13\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[14\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[15\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[16\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[17\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[18\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[19\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[20\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[21\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[22\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[23\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[24\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[25\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[26\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[27\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[28\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[29\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[30\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[31\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[0\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[1\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[2\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[4\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[5\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[6\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[7\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[8\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[9\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[10\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[11\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[12\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[13\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[14\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[15\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[16\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[17\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[18\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[19\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[20\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[21\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[22\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[23\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[24\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[25\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[26\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[27\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[28\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[29\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[30\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[31\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[0\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[1\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[2\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[4\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[5\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[6\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[7\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[8\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[9\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[10\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[11\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[12\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[13\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[14\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[15\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[16\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[17\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[18\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[19\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[20\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[21\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[22\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[23\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[24\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[25\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[26\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[27\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[28\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[29\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[30\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[31\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[0\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[1\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[2\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[4\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[5\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[6\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[7\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[8\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[9\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[10\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[11\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[12\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[13\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[14\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[15\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[0\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[1\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[2\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[4\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[5\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[6\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[7\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[8\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[9\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[10\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[11\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[12\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[13\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[14\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[15\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[16\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[17\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[18\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[19\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[20\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[21\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[22\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[23\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[24\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[25\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[26\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[27\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[28\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[29\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[30\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[31\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[32\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[33\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[34\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[35\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[36\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[37\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[38\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[39\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[40\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[41\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[42\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[43\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[44\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[45\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[46\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[47\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[48\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[49\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[50\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[51\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[52\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[53\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[54\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[55\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[56\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[57\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[58\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[59\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[60\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[61\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[62\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[63\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[64\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[65\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[66\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[67\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[68\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[69\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[70\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[71\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[72\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[73\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[74\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[75\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[76\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[77\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[78\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[79\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[80\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[81\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[82\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[83\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[84\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[85\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[86\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[87\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[88\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[89\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[90\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[91\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[92\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[93\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[94\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[95\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[96\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[97\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[98\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[99\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[100\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[101\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[102\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[103\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[104\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[105\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[106\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[107\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[108\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[109\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[110\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[111\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[112\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[113\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[114\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[115\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[116\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[117\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[118\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[119\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[120\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[121\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[122\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[123\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[124\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[125\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[126\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[127\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[0\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[1\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[2\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[4\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[5\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[0\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[1\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[2\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[4\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[5\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[6\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[7\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[8\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[9\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       )
+      )
+     )
+     (INSTANCE the_structs[2]
+      (NET
+       (foo (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[3]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[2]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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+       (bar[1]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[1]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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+       (bar[0]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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+       (bar[0]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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+       (bar[0]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (bar[0]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (baz\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[32\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[33\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
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+       (qux\[100\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[101\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[102\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[103\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[104\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[105\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[106\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[107\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[108\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[109\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[110\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[111\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[112\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[113\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[114\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[115\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[116\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[117\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[118\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[119\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[120\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[121\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[122\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[123\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[124\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[125\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[126\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (qux\[127\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_b\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_c\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       )
+      )
+     )
+     (INSTANCE the_structs[1]
+      (NET
+       (foo (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[10\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[3]\[11\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
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+       (qux\[109\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
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+       (qux\[111\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[112\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[113\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
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+       (qux\[120\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[121\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
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+       (qux\[124\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
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+       (qux\[126\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (qux\[127\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_b\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_c\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       )
+      )
+     )
+     (INSTANCE the_structs[0]
+      (NET
+       (foo (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
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+       (bar[3]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
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+       (bar[3]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
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+       (bar[3]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[3]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
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+       (bar[2]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
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+       (qux\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[32\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[33\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[34\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[35\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[36\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[37\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[38\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[39\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[40\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[41\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[42\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[43\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[44\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[45\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[46\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[47\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[48\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[49\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[50\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[51\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[52\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[53\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[54\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[55\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[56\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[57\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[58\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[59\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[60\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[61\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[62\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[63\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[64\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[65\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[66\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[67\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[68\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[69\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[70\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[71\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[72\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[73\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[74\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[75\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[76\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[77\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[78\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[79\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[80\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[81\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[82\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[83\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[84\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[85\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[86\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[87\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[88\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[89\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[90\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[91\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[92\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[93\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[94\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[95\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[96\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[97\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[98\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[99\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[100\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[101\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[102\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[103\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[104\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[105\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[106\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[107\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[108\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[109\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[110\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[111\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[112\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[113\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[114\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[115\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[116\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[117\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[118\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[119\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[120\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[121\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[122\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[123\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[124\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[125\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[126\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (qux\[127\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_b\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_c\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       )
+      )
+     )
+     (INSTANCE the_packed_structs[2]
+      (NET
+       (foo (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[32\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[84\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[87\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[88\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[90\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[91\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[92\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[93\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[94\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[95\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[96\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[99\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[100\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[101\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[102\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[103\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[104\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[105\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[106\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[107\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_packed_structs[1]
+      (NET
+       (foo (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[93\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[94\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[95\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[96\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[97\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[98\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[99\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[100\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[101\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[102\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[103\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[104\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[105\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[106\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[107\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_packed_structs[0]
+      (NET
+       (foo (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[1]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[1]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[0]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[0]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[0]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (baz\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (baz\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[32\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[33\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[34\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[35\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[36\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[37\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[38\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[39\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[40\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[41\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[42\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[43\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[44\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[45\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[46\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[47\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[48\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[49\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[50\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[51\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[52\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[53\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[54\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[55\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[56\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[57\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[58\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[59\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[60\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[61\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[62\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[63\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[64\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[65\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[66\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[67\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[68\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[69\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[70\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[71\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[72\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[73\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[74\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[75\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[76\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[77\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[78\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[79\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[80\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[81\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[82\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[83\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[84\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[85\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[86\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[87\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[88\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[89\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[90\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[91\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[92\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[93\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[94\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[95\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[96\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[98\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[99\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[100\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[101\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[102\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[103\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[104\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[105\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[106\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[107\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_packed_structs[2]
+      (NET
+       (foo (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[32\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[46\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[84\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[87\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[88\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[90\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[91\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[92\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[93\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[94\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[95\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[96\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[99\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[100\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[101\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[102\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[103\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[104\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[105\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[106\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[107\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_packed_structs[1]
+      (NET
+       (foo (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[96\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[97\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[98\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[99\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[100\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[101\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[102\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[103\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[104\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[105\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[106\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[107\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_packed_structs[0]
+      (NET
+       (foo (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[1]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[1]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[0]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (baz\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (baz\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (baz\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (baz\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[32\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[33\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[34\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[35\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[36\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[37\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[38\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[39\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[40\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[41\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[42\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[43\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[44\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[45\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[46\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[47\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[48\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[49\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[50\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[51\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[52\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[53\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[54\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[55\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[56\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[57\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[58\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[59\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[60\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[61\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[62\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[63\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[64\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[65\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[66\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[67\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[68\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[69\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[70\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[71\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[72\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[73\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[74\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[75\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[76\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[77\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[78\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[79\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[80\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[81\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[82\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[83\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[84\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[85\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[86\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[87\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[88\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[89\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[90\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[91\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[92\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[93\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[94\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[95\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[96\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[97\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[98\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[99\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[100\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[101\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[102\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[103\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[104\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[105\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[106\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[107\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_local_struct
+      (NET
+       (abc (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (def (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (xyz (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+      )
+     )
+     (INSTANCE the_local_struct
+      (NET
+       (abc (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (def (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (xyz (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+      )
+     )
+     (INSTANCE const_struct
+      (NET
+       (abc (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (def (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (xyz (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+      )
+     )
+     (INSTANCE const_struct
+      (NET
+       (abc (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (def (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (xyz (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+      )
+     )
+     (INSTANCE the_typedefed_struct
+      (NET
+       (abc (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (def (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (xyz (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+      )
+     )
+     (INSTANCE the_typedefed_struct
+      (NET
+       (abc (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (def (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+       (xyz (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+      )
+     )
+     (INSTANCE the_local_unpacked_struct
+      (NET
+       (field_a (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (field_b (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (field_c (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+      )
+     )
+     (INSTANCE the_local_unpacked_struct
+      (NET
+       (field_a (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (field_b (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (field_c (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+      )
+     )
+     (INSTANCE the_local_union
+      (INSTANCE union_a
+       (NET
+        (field_0\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_0\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_0\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_0\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_0\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_0\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_0\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_0\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+      (INSTANCE union_b
+       (NET
+        (field_1\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_1\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_1\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_1\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_2\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_2\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_2\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_2\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+       )
+      )
+      (INSTANCE union_c
+       (NET
+        (field_3\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_3\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_4\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+        (field_4\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+        (field_4\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+        (field_4\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_4\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_4\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+    )
+   )
+   (INSTANCE gen_loop[3]
+    (NET
+     (loop_cyc\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 11))
+     (loop_cyc\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+     (loop_cyc\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (loop_cyc\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (loop_cyc\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (loop_cyc\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    )
+    (INSTANCE the_sub
+     (NET
+      (a (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (b (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (x (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+      (out_2d_unpacked[0][0] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      (out_2d_unpacked[0][1] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+      (out_2d_unpacked[0][2] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 7))
+      (out_2d_unpacked[0][3] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 9))
+      (out_2d_unpacked[1][0] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+      (out_2d_unpacked[1][1] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+     )
+     (INSTANCE data
+      (NET
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+       (bar[0]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (baz\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (baz\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[32\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_b\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_c\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE data
+      (NET
+       (foo (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_b\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_c\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_struct
+      (NET
+       (foo (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[1]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[3\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[53\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[54\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[55\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[56\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[57\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[58\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[59\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[60\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[61\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[62\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[63\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[64\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[65\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[66\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[67\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[68\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[69\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[70\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[71\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[72\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[73\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[74\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[75\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[76\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[77\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[78\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[79\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[80\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[81\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[82\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[83\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[84\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[85\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[86\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[87\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[88\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[89\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[90\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[91\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[92\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[93\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[94\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[95\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[96\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[97\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[98\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[99\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[100\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[101\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[102\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[103\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[104\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[105\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[106\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[107\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_b\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_c\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_struct
+      (NET
+       (foo (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[2]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 4))
+       (bar[2]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[1]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[1]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[3\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 9))
+       (bar[0]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+       (bar[0]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[3\] (T0 30) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (baz\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (baz\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[32\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[33\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[34\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[35\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[36\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[37\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[38\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[39\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[40\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[41\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[42\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[43\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[44\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[45\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[46\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[47\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[48\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[49\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[50\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[51\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[52\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[53\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[54\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[55\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[56\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[57\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[58\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[59\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[60\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[61\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[62\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[63\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[64\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[65\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[66\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[67\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[68\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[69\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[70\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[71\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[72\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[73\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[74\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[75\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[76\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[77\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[78\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[79\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[80\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[81\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[82\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[83\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[84\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[85\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[86\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[87\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[88\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[89\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[90\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[91\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[92\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[93\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[94\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[95\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[96\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[97\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[98\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[99\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[100\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[101\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[102\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[103\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[104\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[105\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[106\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[107\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_b\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_c\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_structs[3]
+      (NET
+       (foo (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
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+       (qux\[127\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       )
+      )
+     )
+     (INSTANCE the_structs[2]
+      (NET
+       (foo (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
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+       (bar[0]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
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+       (bar[0]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
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+       (baz\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
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+       (qux\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
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+       (qux\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
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+       (qux\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
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+       (qux\[56\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[57\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[58\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[59\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[60\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[61\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[62\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[63\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[64\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[65\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[66\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[67\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[68\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[69\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[70\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
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+       (qux\[72\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[73\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[74\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[75\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[76\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[77\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[78\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[79\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[80\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[81\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
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+       (qux\[83\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
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+       (qux\[92\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
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+       (qux\[100\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
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+       (qux\[102\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[103\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
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+       (qux\[105\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[106\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[107\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[108\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[109\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[110\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[111\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[112\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[113\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[114\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[115\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[116\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[117\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[118\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[119\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[120\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[121\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[122\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[123\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[124\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[125\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[126\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[127\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_b\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_b\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_b\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_b\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_b\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_c\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_c\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_c\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_c\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_c\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_c\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_c\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_c\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_c\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       )
+      )
+     )
+     (INSTANCE the_structs[1]
+      (NET
+       (foo (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[10\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[11\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[12\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[13\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[14\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[15\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[16\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[17\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[18\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[19\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[20\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[21\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[22\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[23\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[24\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[25\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[26\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[27\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[28\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[29\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[30\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[31\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[10\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[11\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[12\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[13\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[14\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[15\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[16\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[17\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[18\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[19\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[20\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[21\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[22\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
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+       (bar[2]\[24\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
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+       (bar[2]\[26\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[27\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[28\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
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+       (bar[2]\[31\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
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+       (bar[1]\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[1]\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[1]\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[1]\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[1]\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[1]\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
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+       (bar[0]\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[0]\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[0]\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[0]\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[0]\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[0]\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[0]\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
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+       (bar[0]\[13\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
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+       (bar[0]\[18\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[0]\[19\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
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+       (bar[0]\[29\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[0]\[30\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[0]\[31\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (baz\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (baz\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (baz\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (baz\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (baz\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (baz\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (baz\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (baz\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (baz\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (baz\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (baz\[10\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (baz\[11\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (baz\[12\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (baz\[13\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (baz\[14\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (baz\[15\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
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+       (qux\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
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+       (qux\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[10\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[11\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
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+       (qux\[13\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
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+       (qux\[17\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[18\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[19\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[20\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[21\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[22\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[23\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
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+       (qux\[25\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
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+       (qux\[27\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
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+       (qux\[31\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[32\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
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+       (qux\[112\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[113\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[114\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[115\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[116\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[117\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[118\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[119\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[120\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[121\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[122\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[123\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[124\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[125\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[126\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (qux\[127\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_b\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_b\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_b\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_b\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_b\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_b\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_c\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_c\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_c\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_c\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_c\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_c\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_c\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_c\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_c\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_c\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       )
+      )
+     )
+     (INSTANCE the_structs[0]
+      (NET
+       (foo (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[10\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[11\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[12\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[13\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[14\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[15\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[16\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[17\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[18\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[19\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[20\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[21\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[22\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[23\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[24\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[25\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[26\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[27\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[28\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[29\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[30\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[3]\[31\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[10\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[11\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[12\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[13\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[14\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[15\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[16\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[17\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[18\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[19\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[20\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[21\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (bar[2]\[22\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
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+       (qux\[127\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+      )
+      (INSTANCE sub_struct
+       (NET
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+        (field_b\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
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+        (field_b\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       )
+      )
+     )
+     (INSTANCE the_structs[3]
+      (NET
+       (foo (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[3]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[2]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[1]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
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+       (bar[0]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (bar[0]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
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+       (bar[0]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (baz\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
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+       (baz\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
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+       (baz\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
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+       (qux\[59\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[60\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[61\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[62\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[63\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[64\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[65\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[66\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[67\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[68\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[69\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[70\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[71\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[72\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[73\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[74\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[75\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[76\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[77\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[78\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[79\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[80\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[81\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[82\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[83\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[84\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[85\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[86\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[87\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[88\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[89\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[90\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[91\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[92\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[93\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[94\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[95\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[96\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[97\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[98\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[99\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[100\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[101\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[102\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[103\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[104\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[105\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[106\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[107\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[108\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[109\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[110\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[111\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[112\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[113\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[114\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[115\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[116\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[117\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[118\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[119\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[120\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[121\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[122\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[123\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[124\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[125\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[126\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (qux\[127\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_b\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_c\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       )
+      )
+     )
+     (INSTANCE the_structs[2]
+      (NET
+       (foo (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[3]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[2]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[1]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (bar[0]\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (baz\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[12\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[13\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[14\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[15\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[16\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[18\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[19\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[20\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[21\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[22\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[23\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[24\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[26\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[27\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[28\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[29\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[30\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[31\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[32\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[33\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[34\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[35\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[36\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[37\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[38\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[39\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[40\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[41\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[42\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[43\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[44\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[45\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[46\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[47\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[48\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[49\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[50\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[51\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[52\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[53\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[54\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[55\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[56\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[57\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[58\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[59\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[60\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[61\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[62\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[63\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[64\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
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+       (qux\[67\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[68\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
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+       (qux\[74\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
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+       (qux\[76\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
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+       (qux\[105\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[106\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[107\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[108\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[109\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[110\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[111\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[112\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[113\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[114\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[115\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[116\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[117\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[118\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[119\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[120\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[121\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[122\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[123\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[124\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[125\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[126\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (qux\[127\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_b\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_b\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_b\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_b\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_b\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_b\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_c\[0\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_c\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_c\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_c\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_c\[4\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_c\[5\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_c\[6\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_c\[7\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_c\[8\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_c\[9\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       )
+      )
+     )
+     (INSTANCE the_structs[1]
+      (NET
+       (foo (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[10\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[11\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[12\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[13\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[14\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[15\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[16\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[17\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[18\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[19\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[20\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[21\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[22\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[23\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[24\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[25\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[26\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[27\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[28\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[29\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[30\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[3]\[31\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[10\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[11\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[12\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[13\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[14\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[15\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[16\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[17\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[18\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[19\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[20\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[21\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[22\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[23\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[24\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[25\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (bar[2]\[26\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
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+       (qux\[127\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+      )
+      (INSTANCE sub_struct
+       (NET
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+        (field_c\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
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+        (field_c\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_c\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_c\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_c\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_c\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_c\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_c\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       )
+      )
+     )
+     (INSTANCE the_structs[0]
+      (NET
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+       (qux\[65\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[66\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[67\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[68\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[69\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[70\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[71\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[72\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[73\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[74\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[75\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[76\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[77\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[78\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[79\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[80\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[81\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[82\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[83\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[84\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[85\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[86\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[87\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[88\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[89\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[90\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[91\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[92\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[93\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[94\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[95\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[96\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[97\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[98\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[99\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[100\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[101\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[102\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[103\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[104\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[105\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[106\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[107\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[108\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[109\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[110\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[111\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[112\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[113\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[114\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[115\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[116\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[117\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[118\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[119\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[120\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[121\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[122\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[123\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[124\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[125\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[126\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (qux\[127\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_b\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[4\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[5\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[6\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[7\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_c\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       )
+      )
+     )
+     (INSTANCE the_packed_structs[2]
+      (NET
+       (foo (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[32\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[33\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[34\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[35\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[36\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[37\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[38\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[39\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[40\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[41\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[42\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[43\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[44\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[45\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[46\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[47\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[48\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[49\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[50\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[51\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[52\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[53\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[54\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[55\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[56\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[57\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[58\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[59\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[60\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[61\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[62\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[63\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[64\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[65\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[66\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[67\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[68\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[69\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[70\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[71\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[72\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[73\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[74\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[75\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[76\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[77\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[78\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[79\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[80\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[81\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[82\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[83\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[84\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[85\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[86\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[87\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[88\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[89\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[90\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[91\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[92\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[93\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[94\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[95\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[96\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[97\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[98\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[99\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[100\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[101\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[102\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[103\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[104\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[105\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[106\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[107\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_packed_structs[1]
+      (NET
+       (foo (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_packed_structs[0]
+      (NET
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+       (qux\[69\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[70\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[71\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[72\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[73\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[74\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[75\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[76\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[77\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[78\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[79\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[80\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[81\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[82\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[83\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[84\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[85\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[86\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[87\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[88\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[89\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[90\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[91\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[92\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[93\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[94\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[95\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[96\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[97\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[98\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[99\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[100\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[101\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[102\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[103\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[104\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[105\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[106\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[107\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_packed_structs[2]
+      (NET
+       (foo (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[32\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[33\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[34\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[35\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[36\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[37\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[38\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[39\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[40\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[41\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[42\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[43\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[44\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[45\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[46\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[47\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[48\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[49\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[50\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[51\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[52\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[53\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[54\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[55\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[56\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[57\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[58\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[59\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[60\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[61\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[62\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[63\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[64\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[65\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[66\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[67\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[68\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[69\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[70\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[71\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[72\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[73\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[74\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[75\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[76\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[77\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[78\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[79\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[80\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[81\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[82\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[83\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[84\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[85\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[86\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[87\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[88\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[89\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[90\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[91\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[92\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[93\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[94\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[95\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[96\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[97\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[98\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[99\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[100\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[101\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[102\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[103\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[104\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[105\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[106\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[107\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_packed_structs[1]
+      (NET
+       (foo (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[3]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[10\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[11\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[24\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[27\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[2]\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[1]\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[1]\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[0]\[16\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[17\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[18\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[19\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (bar[0]\[25\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (bar[0]\[26\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (baz\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (baz\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (baz\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
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+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_packed_structs[0]
+      (NET
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+       (qux\[75\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[76\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[77\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[78\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[79\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[80\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[81\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[82\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[83\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[84\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[85\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[86\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[87\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[88\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[89\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[90\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[91\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[92\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[93\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[94\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[95\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[96\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[97\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[98\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[99\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[100\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[101\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[102\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[103\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[104\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[105\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[106\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[107\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[108\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[109\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[110\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[111\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[112\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[113\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[114\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[115\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[116\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[117\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[118\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[119\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[120\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[121\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[122\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[123\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[124\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[125\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[126\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (qux\[127\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+      )
+      (INSTANCE sub_struct
+       (NET
+        (field_a (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_b\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[8\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_c\[9\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+     (INSTANCE the_local_struct
+      (NET
+       (abc (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (def (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (xyz (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+      )
+     )
+     (INSTANCE the_local_struct
+      (NET
+       (abc (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (def (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (xyz (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+      )
+     )
+     (INSTANCE const_struct
+      (NET
+       (abc (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (def (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (xyz (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+      )
+     )
+     (INSTANCE const_struct
+      (NET
+       (abc (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (def (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       (xyz (T0 0) (T1 100) (TZ 0) (TX 0) (TB 0) (TC 1))
+      )
+     )
+     (INSTANCE the_typedefed_struct
+      (NET
+       (abc (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (def (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (xyz (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+      )
+     )
+     (INSTANCE the_typedefed_struct
+      (NET
+       (abc (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       (def (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+       (xyz (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+      )
+     )
+     (INSTANCE the_local_unpacked_struct
+      (NET
+       (field_a (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (field_b (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (field_c (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+      )
+     )
+     (INSTANCE the_local_unpacked_struct
+      (NET
+       (field_a (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+       (field_b (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+       (field_c (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+      )
+     )
+     (INSTANCE the_local_union
+      (INSTANCE union_a
+       (NET
+        (field_0\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_0\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_0\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_0\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_0\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_0\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_0\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_0\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+      (INSTANCE union_b
+       (NET
+        (field_1\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_1\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_1\[2\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_1\[3\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_2\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_2\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_2\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_2\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+       )
+      )
+      (INSTANCE union_c
+       (NET
+        (field_3\[0\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_3\[1\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_4\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+        (field_4\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+        (field_4\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+        (field_4\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+        (field_4\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+        (field_4\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+       )
+      )
+     )
+    )
+   )
+   (INSTANCE the_intf_a
+    (NET
+     (clk (T0 55) (T1 45) (TZ 0) (TX 0) (TB 0) (TC 19))
+     (data[3]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+     (data[3]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (data[3]\[2\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (data[3]\[3\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data[2]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 11))
+     (data[2]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+     (data[2]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (data[2]\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data[2]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data[2]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data[2]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data[2]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data[1]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+     (data[1]\[1\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
+     (data[1]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (data[1]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data[1]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data[1]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data[1]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data[1]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data[0]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 11))
+     (data[0]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (data[0]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (data[0]\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data[0]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data[0]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data[0]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data[0]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 11))
+     (data_typed\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (data_typed\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 2))
+     (data_typed\[3\] (T0 70) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data_typed\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+     (data_typed\[9\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
+     (data_typed\[10\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (data_typed\[11\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data_typed\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[16\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 11))
+     (data_typed\[17\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+     (data_typed\[18\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (data_typed\[19\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data_typed\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[24\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+     (data_typed\[25\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (data_typed\[26\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (data_typed\[27\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data_typed\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    )
+   )
+   (INSTANCE the_intf_b
+    (NET
+     (clk (T0 55) (T1 45) (TZ 0) (TX 0) (TB 0) (TC 19))
+     (data[3]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 11))
+     (data[3]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (data[3]\[2\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (data[3]\[3\] (T0 30) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data[3]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data[3]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data[3]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data[3]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data[2]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+     (data[2]\[1\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (data[2]\[2\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (data[2]\[3\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data[2]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data[2]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data[2]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data[2]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data[1]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 11))
+     (data[1]\[1\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+     (data[1]\[2\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (data[1]\[3\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data[1]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data[1]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data[1]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data[1]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data[0]\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+     (data[0]\[1\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
+     (data[0]\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (data[0]\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data[0]\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data[0]\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data[0]\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data[0]\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[0\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+     (data_typed\[1\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 6))
+     (data_typed\[2\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (data_typed\[3\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data_typed\[4\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[5\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[6\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[7\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[8\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 11))
+     (data_typed\[9\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 6))
+     (data_typed\[10\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (data_typed\[11\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data_typed\[12\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[13\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[14\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[15\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[16\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 10))
+     (data_typed\[17\] (T0 60) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (data_typed\[18\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (data_typed\[19\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data_typed\[20\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[21\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[22\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[23\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[24\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 11))
+     (data_typed\[25\] (T0 50) (T1 50) (TZ 0) (TX 0) (TB 0) (TC 5))
+     (data_typed\[26\] (T0 40) (T1 60) (TZ 0) (TX 0) (TB 0) (TC 3))
+     (data_typed\[27\] (T0 30) (T1 70) (TZ 0) (TX 0) (TB 0) (TC 1))
+     (data_typed\[28\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[29\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[30\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+     (data_typed\[31\] (T0 100) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    )
+   )
+  )
+ )
+)
diff --git a/test_regress/t/t_trace_type_dupes_structs_saif.py b/test_regress/t/t_trace_type_dupes_structs_saif.py
new file mode 100755
index 000000000..e2f71b23f
--- /dev/null
+++ b/test_regress/t/t_trace_type_dupes_structs_saif.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_type_dupes_common
+
+test.scenarios('vlt_all')
+
+trace_type_dupes_common.run(test)
diff --git a/test_regress/t/t_trace_type_dupes_structs_vcd.out b/test_regress/t/t_trace_type_dupes_structs_vcd.out
new file mode 100644
index 000000000..a3a075bd3
--- /dev/null
+++ b/test_regress/t/t_trace_type_dupes_structs_vcd.out
@@ -0,0 +1,3711 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module top $end
+  $var wire 1 $% clk $end
+  $scope module pkg $end
+   $scope module SUB_ONES $end
+    $var wire 1 L% field_a $end
+    $var wire 6 o& field_b [5:0] $end
+    $var wire 10 p& field_c [9:0] $end
+   $upscope $end
+   $scope module SUB_ZEROS $end
+    $var wire 1 M% field_a $end
+    $var wire 6 q& field_b [5:0] $end
+    $var wire 10 r& field_c [9:0] $end
+   $upscope $end
+  $upscope $end
+  $scope module t $end
+   $var wire 1 $% clk $end
+   $var wire 32 " cyc [31:0] $end
+   $var wire 4 # x [3:0] $end
+   $scope module gen_loop[0] $end
+    $var wire 32 " loop_cyc [31:0] $end
+    $scope module the_sub $end
+     $var wire 1 $ a $end
+     $var wire 1 % b $end
+     $var wire 1 & x $end
+     $var wire 1 ' out_2d_unpacked[0][0] $end
+     $var wire 1 ( out_2d_unpacked[0][1] $end
+     $var wire 1 ) out_2d_unpacked[0][2] $end
+     $var wire 1 * out_2d_unpacked[0][3] $end
+     $var wire 1 + out_2d_unpacked[1][0] $end
+     $var wire 1 , out_2d_unpacked[1][1] $end
+     $var wire 1 - out_2d_unpacked[1][2] $end
+     $var wire 1 . out_2d_unpacked[1][3] $end
+     $var wire 1 / out_2d_unpacked[2][0] $end
+     $var wire 1 0 out_2d_unpacked[2][1] $end
+     $var wire 1 1 out_2d_unpacked[2][2] $end
+     $var wire 1 2 out_2d_unpacked[2][3] $end
+     $scope module data $end
+      $var wire 1 3 foo $end
+      $var wire 32 4 bar[0] [31:0] $end
+      $var wire 32 5 bar[1] [31:0] $end
+      $var wire 32 6 bar[2] [31:0] $end
+      $var wire 32 7 bar[3] [31:0] $end
+      $var wire 16 8 baz [15:0] $end
+      $var wire 128 9 qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 = field_a $end
+       $var wire 6 > field_b [5:0] $end
+       $var wire 10 ? field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $var wire 32 " cyc [31:0] $end
+     $var wire 1 $% clk $end
+     $scope module the_struct $end
+      $var wire 1 3 foo $end
+      $var wire 32 4 bar[0] [31:0] $end
+      $var wire 32 5 bar[1] [31:0] $end
+      $var wire 32 6 bar[2] [31:0] $end
+      $var wire 32 7 bar[3] [31:0] $end
+      $var wire 16 8 baz [15:0] $end
+      $var wire 128 9 qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 = field_a $end
+       $var wire 6 > field_b [5:0] $end
+       $var wire 10 ? field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_structs[0] $end
+      $var wire 1 @ foo $end
+      $var wire 32 A bar[0] [31:0] $end
+      $var wire 32 B bar[1] [31:0] $end
+      $var wire 32 C bar[2] [31:0] $end
+      $var wire 32 D bar[3] [31:0] $end
+      $var wire 16 E baz [15:0] $end
+      $var wire 128 F qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 J field_a $end
+       $var wire 6 K field_b [5:0] $end
+       $var wire 10 L field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_structs[1] $end
+      $var wire 1 M foo $end
+      $var wire 32 N bar[0] [31:0] $end
+      $var wire 32 O bar[1] [31:0] $end
+      $var wire 32 P bar[2] [31:0] $end
+      $var wire 32 Q bar[3] [31:0] $end
+      $var wire 16 R baz [15:0] $end
+      $var wire 128 S qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 W field_a $end
+       $var wire 6 X field_b [5:0] $end
+       $var wire 10 Y field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_structs[2] $end
+      $var wire 1 Z foo $end
+      $var wire 32 [ bar[0] [31:0] $end
+      $var wire 32 \ bar[1] [31:0] $end
+      $var wire 32 ] bar[2] [31:0] $end
+      $var wire 32 ^ bar[3] [31:0] $end
+      $var wire 16 _ baz [15:0] $end
+      $var wire 128 ` qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 d field_a $end
+       $var wire 6 e field_b [5:0] $end
+       $var wire 10 f field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_structs[3] $end
+      $var wire 1 g foo $end
+      $var wire 32 h bar[0] [31:0] $end
+      $var wire 32 i bar[1] [31:0] $end
+      $var wire 32 j bar[2] [31:0] $end
+      $var wire 32 k bar[3] [31:0] $end
+      $var wire 16 l baz [15:0] $end
+      $var wire 128 m qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 q field_a $end
+       $var wire 6 r field_b [5:0] $end
+       $var wire 10 s field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_packed_structs[0] $end
+      $var wire 1 %% foo $end
+      $var wire 32 &% bar[0] [31:0] $end
+      $var wire 32 '% bar[1] [31:0] $end
+      $var wire 32 (% bar[2] [31:0] $end
+      $var wire 32 )% bar[3] [31:0] $end
+      $var wire 16 *% baz [15:0] $end
+      $var wire 128 +% qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 /% field_a $end
+       $var wire 6 0% field_b [5:0] $end
+       $var wire 10 1% field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_packed_structs[1] $end
+      $var wire 1 2% foo $end
+      $var wire 32 3% bar[0] [31:0] $end
+      $var wire 32 4% bar[1] [31:0] $end
+      $var wire 32 5% bar[2] [31:0] $end
+      $var wire 32 6% bar[3] [31:0] $end
+      $var wire 16 7% baz [15:0] $end
+      $var wire 128 8% qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 <% field_a $end
+       $var wire 6 =% field_b [5:0] $end
+       $var wire 10 >% field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_packed_structs[2] $end
+      $var wire 1 ?% foo $end
+      $var wire 32 @% bar[0] [31:0] $end
+      $var wire 32 A% bar[1] [31:0] $end
+      $var wire 32 B% bar[2] [31:0] $end
+      $var wire 32 C% bar[3] [31:0] $end
+      $var wire 16 D% baz [15:0] $end
+      $var wire 128 E% qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 I% field_a $end
+       $var wire 6 J% field_b [5:0] $end
+       $var wire 10 K% field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_local_struct $end
+      $var wire 1 t abc $end
+      $var wire 1 u def $end
+      $var wire 1 v xyz $end
+     $upscope $end
+     $scope module const_struct $end
+      $var wire 1 L% abc $end
+      $var wire 1 M% def $end
+      $var wire 1 L% xyz $end
+     $upscope $end
+     $scope module the_typedefed_struct $end
+      $var wire 1 w abc $end
+      $var wire 1 x def $end
+      $var wire 1 y xyz $end
+     $upscope $end
+     $scope module the_local_unpacked_struct $end
+      $var wire 1 z field_a $end
+      $var wire 1 { field_b $end
+      $var wire 1 | field_c $end
+     $upscope $end
+     $scope module the_local_union $end
+      $scope module union_a $end
+       $var wire 8 } field_0 [7:0] $end
+      $upscope $end
+      $scope module union_b $end
+       $var wire 4 ~ field_1 [3:0] $end
+       $var wire 4 !! field_2 [3:0] $end
+      $upscope $end
+      $scope module union_c $end
+       $var wire 2 "! field_3 [1:0] $end
+       $var wire 6 #! field_4 [5:0] $end
+      $upscope $end
+     $upscope $end
+     $var wire 32 $! the_logic_array[0] [31:0] $end
+     $var wire 32 %! the_logic_array[1] [31:0] $end
+     $var wire 32 &! the_other_logic_array[0] [31:0] $end
+     $var wire 32 '! the_other_logic_array[1] [31:0] $end
+     $var wire 16 (! the_unpacked_array[0] [15:0] $end
+     $var wire 16 )! the_unpacked_array[1] [15:0] $end
+     $var wire 16 *! the_unpacked_array[2] [15:0] $end
+     $var wire 16 +! the_unpacked_array[3] [15:0] $end
+     $var wire 16 ,! the_unpacked_array[4] [15:0] $end
+     $var wire 1 -! the_2d_unpacked[0][0] $end
+     $var wire 1 .! the_2d_unpacked[0][1] $end
+     $var wire 1 /! the_2d_unpacked[0][2] $end
+     $var wire 1 0! the_2d_unpacked[0][3] $end
+     $var wire 1 1! the_2d_unpacked[1][0] $end
+     $var wire 1 2! the_2d_unpacked[1][1] $end
+     $var wire 1 3! the_2d_unpacked[1][2] $end
+     $var wire 1 4! the_2d_unpacked[1][3] $end
+     $var wire 1 5! the_2d_unpacked[2][0] $end
+     $var wire 1 6! the_2d_unpacked[2][1] $end
+     $var wire 1 7! the_2d_unpacked[2][2] $end
+     $var wire 1 8! the_2d_unpacked[2][3] $end
+     $var wire 4 N% two_fours[0] [3:0] $end
+     $var wire 4 O% two_fours[1] [3:0] $end
+     $var wire 4 P% two_fours_var[0] [3:0] $end
+     $var wire 4 Q% two_fours_var[1] [3:0] $end
+    $upscope $end
+   $upscope $end
+   $scope module gen_loop[1] $end
+    $var wire 32 9! loop_cyc [31:0] $end
+    $scope module the_sub $end
+     $var wire 1 :! a $end
+     $var wire 1 ;! b $end
+     $var wire 1 <! x $end
+     $var wire 1 =! out_2d_unpacked[0][0] $end
+     $var wire 1 >! out_2d_unpacked[0][1] $end
+     $var wire 1 ?! out_2d_unpacked[0][2] $end
+     $var wire 1 @! out_2d_unpacked[0][3] $end
+     $var wire 1 A! out_2d_unpacked[1][0] $end
+     $var wire 1 B! out_2d_unpacked[1][1] $end
+     $var wire 1 C! out_2d_unpacked[1][2] $end
+     $var wire 1 D! out_2d_unpacked[1][3] $end
+     $var wire 1 E! out_2d_unpacked[2][0] $end
+     $var wire 1 F! out_2d_unpacked[2][1] $end
+     $var wire 1 G! out_2d_unpacked[2][2] $end
+     $var wire 1 H! out_2d_unpacked[2][3] $end
+     $scope module data $end
+      $var wire 1 I! foo $end
+      $var wire 32 J! bar[0] [31:0] $end
+      $var wire 32 K! bar[1] [31:0] $end
+      $var wire 32 L! bar[2] [31:0] $end
+      $var wire 32 M! bar[3] [31:0] $end
+      $var wire 16 N! baz [15:0] $end
+      $var wire 128 O! qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 S! field_a $end
+       $var wire 6 T! field_b [5:0] $end
+       $var wire 10 U! field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $var wire 32 9! cyc [31:0] $end
+     $var wire 1 $% clk $end
+     $scope module the_struct $end
+      $var wire 1 I! foo $end
+      $var wire 32 J! bar[0] [31:0] $end
+      $var wire 32 K! bar[1] [31:0] $end
+      $var wire 32 L! bar[2] [31:0] $end
+      $var wire 32 M! bar[3] [31:0] $end
+      $var wire 16 N! baz [15:0] $end
+      $var wire 128 O! qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 S! field_a $end
+       $var wire 6 T! field_b [5:0] $end
+       $var wire 10 U! field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_structs[0] $end
+      $var wire 1 V! foo $end
+      $var wire 32 W! bar[0] [31:0] $end
+      $var wire 32 X! bar[1] [31:0] $end
+      $var wire 32 Y! bar[2] [31:0] $end
+      $var wire 32 Z! bar[3] [31:0] $end
+      $var wire 16 [! baz [15:0] $end
+      $var wire 128 \! qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 `! field_a $end
+       $var wire 6 a! field_b [5:0] $end
+       $var wire 10 b! field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_structs[1] $end
+      $var wire 1 c! foo $end
+      $var wire 32 d! bar[0] [31:0] $end
+      $var wire 32 e! bar[1] [31:0] $end
+      $var wire 32 f! bar[2] [31:0] $end
+      $var wire 32 g! bar[3] [31:0] $end
+      $var wire 16 h! baz [15:0] $end
+      $var wire 128 i! qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 m! field_a $end
+       $var wire 6 n! field_b [5:0] $end
+       $var wire 10 o! field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_structs[2] $end
+      $var wire 1 p! foo $end
+      $var wire 32 q! bar[0] [31:0] $end
+      $var wire 32 r! bar[1] [31:0] $end
+      $var wire 32 s! bar[2] [31:0] $end
+      $var wire 32 t! bar[3] [31:0] $end
+      $var wire 16 u! baz [15:0] $end
+      $var wire 128 v! qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 z! field_a $end
+       $var wire 6 {! field_b [5:0] $end
+       $var wire 10 |! field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_structs[3] $end
+      $var wire 1 }! foo $end
+      $var wire 32 ~! bar[0] [31:0] $end
+      $var wire 32 !" bar[1] [31:0] $end
+      $var wire 32 "" bar[2] [31:0] $end
+      $var wire 32 #" bar[3] [31:0] $end
+      $var wire 16 $" baz [15:0] $end
+      $var wire 128 %" qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 )" field_a $end
+       $var wire 6 *" field_b [5:0] $end
+       $var wire 10 +" field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_packed_structs[0] $end
+      $var wire 1 R% foo $end
+      $var wire 32 S% bar[0] [31:0] $end
+      $var wire 32 T% bar[1] [31:0] $end
+      $var wire 32 U% bar[2] [31:0] $end
+      $var wire 32 V% bar[3] [31:0] $end
+      $var wire 16 W% baz [15:0] $end
+      $var wire 128 X% qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 \% field_a $end
+       $var wire 6 ]% field_b [5:0] $end
+       $var wire 10 ^% field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_packed_structs[1] $end
+      $var wire 1 _% foo $end
+      $var wire 32 `% bar[0] [31:0] $end
+      $var wire 32 a% bar[1] [31:0] $end
+      $var wire 32 b% bar[2] [31:0] $end
+      $var wire 32 c% bar[3] [31:0] $end
+      $var wire 16 d% baz [15:0] $end
+      $var wire 128 e% qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 i% field_a $end
+       $var wire 6 j% field_b [5:0] $end
+       $var wire 10 k% field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_packed_structs[2] $end
+      $var wire 1 l% foo $end
+      $var wire 32 m% bar[0] [31:0] $end
+      $var wire 32 n% bar[1] [31:0] $end
+      $var wire 32 o% bar[2] [31:0] $end
+      $var wire 32 p% bar[3] [31:0] $end
+      $var wire 16 q% baz [15:0] $end
+      $var wire 128 r% qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 v% field_a $end
+       $var wire 6 w% field_b [5:0] $end
+       $var wire 10 x% field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_local_struct $end
+      $var wire 1 ," abc $end
+      $var wire 1 -" def $end
+      $var wire 1 ." xyz $end
+     $upscope $end
+     $scope module const_struct $end
+      $var wire 1 L% abc $end
+      $var wire 1 M% def $end
+      $var wire 1 L% xyz $end
+     $upscope $end
+     $scope module the_typedefed_struct $end
+      $var wire 1 /" abc $end
+      $var wire 1 0" def $end
+      $var wire 1 1" xyz $end
+     $upscope $end
+     $scope module the_local_unpacked_struct $end
+      $var wire 1 2" field_a $end
+      $var wire 1 3" field_b $end
+      $var wire 1 4" field_c $end
+     $upscope $end
+     $scope module the_local_union $end
+      $scope module union_a $end
+       $var wire 8 5" field_0 [7:0] $end
+      $upscope $end
+      $scope module union_b $end
+       $var wire 4 6" field_1 [3:0] $end
+       $var wire 4 7" field_2 [3:0] $end
+      $upscope $end
+      $scope module union_c $end
+       $var wire 2 8" field_3 [1:0] $end
+       $var wire 6 9" field_4 [5:0] $end
+      $upscope $end
+     $upscope $end
+     $var wire 32 :" the_logic_array[0] [31:0] $end
+     $var wire 32 ;" the_logic_array[1] [31:0] $end
+     $var wire 32 <" the_other_logic_array[0] [31:0] $end
+     $var wire 32 =" the_other_logic_array[1] [31:0] $end
+     $var wire 16 >" the_unpacked_array[0] [15:0] $end
+     $var wire 16 ?" the_unpacked_array[1] [15:0] $end
+     $var wire 16 @" the_unpacked_array[2] [15:0] $end
+     $var wire 16 A" the_unpacked_array[3] [15:0] $end
+     $var wire 16 B" the_unpacked_array[4] [15:0] $end
+     $var wire 1 C" the_2d_unpacked[0][0] $end
+     $var wire 1 D" the_2d_unpacked[0][1] $end
+     $var wire 1 E" the_2d_unpacked[0][2] $end
+     $var wire 1 F" the_2d_unpacked[0][3] $end
+     $var wire 1 G" the_2d_unpacked[1][0] $end
+     $var wire 1 H" the_2d_unpacked[1][1] $end
+     $var wire 1 I" the_2d_unpacked[1][2] $end
+     $var wire 1 J" the_2d_unpacked[1][3] $end
+     $var wire 1 K" the_2d_unpacked[2][0] $end
+     $var wire 1 L" the_2d_unpacked[2][1] $end
+     $var wire 1 M" the_2d_unpacked[2][2] $end
+     $var wire 1 N" the_2d_unpacked[2][3] $end
+     $var wire 4 N% two_fours[0] [3:0] $end
+     $var wire 4 O% two_fours[1] [3:0] $end
+     $var wire 4 y% two_fours_var[0] [3:0] $end
+     $var wire 4 z% two_fours_var[1] [3:0] $end
+    $upscope $end
+   $upscope $end
+   $scope module gen_loop[2] $end
+    $var wire 32 O" loop_cyc [31:0] $end
+    $scope module the_sub $end
+     $var wire 1 P" a $end
+     $var wire 1 Q" b $end
+     $var wire 1 R" x $end
+     $var wire 1 S" out_2d_unpacked[0][0] $end
+     $var wire 1 T" out_2d_unpacked[0][1] $end
+     $var wire 1 U" out_2d_unpacked[0][2] $end
+     $var wire 1 V" out_2d_unpacked[0][3] $end
+     $var wire 1 W" out_2d_unpacked[1][0] $end
+     $var wire 1 X" out_2d_unpacked[1][1] $end
+     $var wire 1 Y" out_2d_unpacked[1][2] $end
+     $var wire 1 Z" out_2d_unpacked[1][3] $end
+     $var wire 1 [" out_2d_unpacked[2][0] $end
+     $var wire 1 \" out_2d_unpacked[2][1] $end
+     $var wire 1 ]" out_2d_unpacked[2][2] $end
+     $var wire 1 ^" out_2d_unpacked[2][3] $end
+     $scope module data $end
+      $var wire 1 _" foo $end
+      $var wire 32 `" bar[0] [31:0] $end
+      $var wire 32 a" bar[1] [31:0] $end
+      $var wire 32 b" bar[2] [31:0] $end
+      $var wire 32 c" bar[3] [31:0] $end
+      $var wire 16 d" baz [15:0] $end
+      $var wire 128 e" qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 i" field_a $end
+       $var wire 6 j" field_b [5:0] $end
+       $var wire 10 k" field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $var wire 32 O" cyc [31:0] $end
+     $var wire 1 $% clk $end
+     $scope module the_struct $end
+      $var wire 1 _" foo $end
+      $var wire 32 `" bar[0] [31:0] $end
+      $var wire 32 a" bar[1] [31:0] $end
+      $var wire 32 b" bar[2] [31:0] $end
+      $var wire 32 c" bar[3] [31:0] $end
+      $var wire 16 d" baz [15:0] $end
+      $var wire 128 e" qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 i" field_a $end
+       $var wire 6 j" field_b [5:0] $end
+       $var wire 10 k" field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_structs[0] $end
+      $var wire 1 l" foo $end
+      $var wire 32 m" bar[0] [31:0] $end
+      $var wire 32 n" bar[1] [31:0] $end
+      $var wire 32 o" bar[2] [31:0] $end
+      $var wire 32 p" bar[3] [31:0] $end
+      $var wire 16 q" baz [15:0] $end
+      $var wire 128 r" qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 v" field_a $end
+       $var wire 6 w" field_b [5:0] $end
+       $var wire 10 x" field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_structs[1] $end
+      $var wire 1 y" foo $end
+      $var wire 32 z" bar[0] [31:0] $end
+      $var wire 32 {" bar[1] [31:0] $end
+      $var wire 32 |" bar[2] [31:0] $end
+      $var wire 32 }" bar[3] [31:0] $end
+      $var wire 16 ~" baz [15:0] $end
+      $var wire 128 !# qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 %# field_a $end
+       $var wire 6 &# field_b [5:0] $end
+       $var wire 10 '# field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_structs[2] $end
+      $var wire 1 (# foo $end
+      $var wire 32 )# bar[0] [31:0] $end
+      $var wire 32 *# bar[1] [31:0] $end
+      $var wire 32 +# bar[2] [31:0] $end
+      $var wire 32 ,# bar[3] [31:0] $end
+      $var wire 16 -# baz [15:0] $end
+      $var wire 128 .# qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 2# field_a $end
+       $var wire 6 3# field_b [5:0] $end
+       $var wire 10 4# field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_structs[3] $end
+      $var wire 1 5# foo $end
+      $var wire 32 6# bar[0] [31:0] $end
+      $var wire 32 7# bar[1] [31:0] $end
+      $var wire 32 8# bar[2] [31:0] $end
+      $var wire 32 9# bar[3] [31:0] $end
+      $var wire 16 :# baz [15:0] $end
+      $var wire 128 ;# qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 ?# field_a $end
+       $var wire 6 @# field_b [5:0] $end
+       $var wire 10 A# field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_packed_structs[0] $end
+      $var wire 1 {% foo $end
+      $var wire 32 |% bar[0] [31:0] $end
+      $var wire 32 }% bar[1] [31:0] $end
+      $var wire 32 ~% bar[2] [31:0] $end
+      $var wire 32 !& bar[3] [31:0] $end
+      $var wire 16 "& baz [15:0] $end
+      $var wire 128 #& qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 '& field_a $end
+       $var wire 6 (& field_b [5:0] $end
+       $var wire 10 )& field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_packed_structs[1] $end
+      $var wire 1 *& foo $end
+      $var wire 32 +& bar[0] [31:0] $end
+      $var wire 32 ,& bar[1] [31:0] $end
+      $var wire 32 -& bar[2] [31:0] $end
+      $var wire 32 .& bar[3] [31:0] $end
+      $var wire 16 /& baz [15:0] $end
+      $var wire 128 0& qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 4& field_a $end
+       $var wire 6 5& field_b [5:0] $end
+       $var wire 10 6& field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_packed_structs[2] $end
+      $var wire 1 7& foo $end
+      $var wire 32 8& bar[0] [31:0] $end
+      $var wire 32 9& bar[1] [31:0] $end
+      $var wire 32 :& bar[2] [31:0] $end
+      $var wire 32 ;& bar[3] [31:0] $end
+      $var wire 16 <& baz [15:0] $end
+      $var wire 128 =& qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 A& field_a $end
+       $var wire 6 B& field_b [5:0] $end
+       $var wire 10 C& field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_local_struct $end
+      $var wire 1 B# abc $end
+      $var wire 1 C# def $end
+      $var wire 1 D# xyz $end
+     $upscope $end
+     $scope module const_struct $end
+      $var wire 1 L% abc $end
+      $var wire 1 M% def $end
+      $var wire 1 L% xyz $end
+     $upscope $end
+     $scope module the_typedefed_struct $end
+      $var wire 1 E# abc $end
+      $var wire 1 F# def $end
+      $var wire 1 G# xyz $end
+     $upscope $end
+     $scope module the_local_unpacked_struct $end
+      $var wire 1 H# field_a $end
+      $var wire 1 I# field_b $end
+      $var wire 1 J# field_c $end
+     $upscope $end
+     $scope module the_local_union $end
+      $scope module union_a $end
+       $var wire 8 K# field_0 [7:0] $end
+      $upscope $end
+      $scope module union_b $end
+       $var wire 4 L# field_1 [3:0] $end
+       $var wire 4 M# field_2 [3:0] $end
+      $upscope $end
+      $scope module union_c $end
+       $var wire 2 N# field_3 [1:0] $end
+       $var wire 6 O# field_4 [5:0] $end
+      $upscope $end
+     $upscope $end
+     $var wire 32 P# the_logic_array[0] [31:0] $end
+     $var wire 32 Q# the_logic_array[1] [31:0] $end
+     $var wire 32 R# the_other_logic_array[0] [31:0] $end
+     $var wire 32 S# the_other_logic_array[1] [31:0] $end
+     $var wire 16 T# the_unpacked_array[0] [15:0] $end
+     $var wire 16 U# the_unpacked_array[1] [15:0] $end
+     $var wire 16 V# the_unpacked_array[2] [15:0] $end
+     $var wire 16 W# the_unpacked_array[3] [15:0] $end
+     $var wire 16 X# the_unpacked_array[4] [15:0] $end
+     $var wire 1 Y# the_2d_unpacked[0][0] $end
+     $var wire 1 Z# the_2d_unpacked[0][1] $end
+     $var wire 1 [# the_2d_unpacked[0][2] $end
+     $var wire 1 \# the_2d_unpacked[0][3] $end
+     $var wire 1 ]# the_2d_unpacked[1][0] $end
+     $var wire 1 ^# the_2d_unpacked[1][1] $end
+     $var wire 1 _# the_2d_unpacked[1][2] $end
+     $var wire 1 `# the_2d_unpacked[1][3] $end
+     $var wire 1 a# the_2d_unpacked[2][0] $end
+     $var wire 1 b# the_2d_unpacked[2][1] $end
+     $var wire 1 c# the_2d_unpacked[2][2] $end
+     $var wire 1 d# the_2d_unpacked[2][3] $end
+     $var wire 4 N% two_fours[0] [3:0] $end
+     $var wire 4 O% two_fours[1] [3:0] $end
+     $var wire 4 D& two_fours_var[0] [3:0] $end
+     $var wire 4 E& two_fours_var[1] [3:0] $end
+    $upscope $end
+   $upscope $end
+   $scope module gen_loop[3] $end
+    $var wire 32 e# loop_cyc [31:0] $end
+    $scope module the_sub $end
+     $var wire 1 f# a $end
+     $var wire 1 g# b $end
+     $var wire 1 h# x $end
+     $var wire 1 i# out_2d_unpacked[0][0] $end
+     $var wire 1 j# out_2d_unpacked[0][1] $end
+     $var wire 1 k# out_2d_unpacked[0][2] $end
+     $var wire 1 l# out_2d_unpacked[0][3] $end
+     $var wire 1 m# out_2d_unpacked[1][0] $end
+     $var wire 1 n# out_2d_unpacked[1][1] $end
+     $var wire 1 o# out_2d_unpacked[1][2] $end
+     $var wire 1 p# out_2d_unpacked[1][3] $end
+     $var wire 1 q# out_2d_unpacked[2][0] $end
+     $var wire 1 r# out_2d_unpacked[2][1] $end
+     $var wire 1 s# out_2d_unpacked[2][2] $end
+     $var wire 1 t# out_2d_unpacked[2][3] $end
+     $scope module data $end
+      $var wire 1 u# foo $end
+      $var wire 32 v# bar[0] [31:0] $end
+      $var wire 32 w# bar[1] [31:0] $end
+      $var wire 32 x# bar[2] [31:0] $end
+      $var wire 32 y# bar[3] [31:0] $end
+      $var wire 16 z# baz [15:0] $end
+      $var wire 128 {# qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 !$ field_a $end
+       $var wire 6 "$ field_b [5:0] $end
+       $var wire 10 #$ field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $var wire 32 e# cyc [31:0] $end
+     $var wire 1 $% clk $end
+     $scope module the_struct $end
+      $var wire 1 u# foo $end
+      $var wire 32 v# bar[0] [31:0] $end
+      $var wire 32 w# bar[1] [31:0] $end
+      $var wire 32 x# bar[2] [31:0] $end
+      $var wire 32 y# bar[3] [31:0] $end
+      $var wire 16 z# baz [15:0] $end
+      $var wire 128 {# qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 !$ field_a $end
+       $var wire 6 "$ field_b [5:0] $end
+       $var wire 10 #$ field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_structs[0] $end
+      $var wire 1 $$ foo $end
+      $var wire 32 %$ bar[0] [31:0] $end
+      $var wire 32 &$ bar[1] [31:0] $end
+      $var wire 32 '$ bar[2] [31:0] $end
+      $var wire 32 ($ bar[3] [31:0] $end
+      $var wire 16 )$ baz [15:0] $end
+      $var wire 128 *$ qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 .$ field_a $end
+       $var wire 6 /$ field_b [5:0] $end
+       $var wire 10 0$ field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_structs[1] $end
+      $var wire 1 1$ foo $end
+      $var wire 32 2$ bar[0] [31:0] $end
+      $var wire 32 3$ bar[1] [31:0] $end
+      $var wire 32 4$ bar[2] [31:0] $end
+      $var wire 32 5$ bar[3] [31:0] $end
+      $var wire 16 6$ baz [15:0] $end
+      $var wire 128 7$ qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 ;$ field_a $end
+       $var wire 6 <$ field_b [5:0] $end
+       $var wire 10 =$ field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_structs[2] $end
+      $var wire 1 >$ foo $end
+      $var wire 32 ?$ bar[0] [31:0] $end
+      $var wire 32 @$ bar[1] [31:0] $end
+      $var wire 32 A$ bar[2] [31:0] $end
+      $var wire 32 B$ bar[3] [31:0] $end
+      $var wire 16 C$ baz [15:0] $end
+      $var wire 128 D$ qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 H$ field_a $end
+       $var wire 6 I$ field_b [5:0] $end
+       $var wire 10 J$ field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_structs[3] $end
+      $var wire 1 K$ foo $end
+      $var wire 32 L$ bar[0] [31:0] $end
+      $var wire 32 M$ bar[1] [31:0] $end
+      $var wire 32 N$ bar[2] [31:0] $end
+      $var wire 32 O$ bar[3] [31:0] $end
+      $var wire 16 P$ baz [15:0] $end
+      $var wire 128 Q$ qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 U$ field_a $end
+       $var wire 6 V$ field_b [5:0] $end
+       $var wire 10 W$ field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_packed_structs[0] $end
+      $var wire 1 F& foo $end
+      $var wire 32 G& bar[0] [31:0] $end
+      $var wire 32 H& bar[1] [31:0] $end
+      $var wire 32 I& bar[2] [31:0] $end
+      $var wire 32 J& bar[3] [31:0] $end
+      $var wire 16 K& baz [15:0] $end
+      $var wire 128 L& qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 P& field_a $end
+       $var wire 6 Q& field_b [5:0] $end
+       $var wire 10 R& field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_packed_structs[1] $end
+      $var wire 1 S& foo $end
+      $var wire 32 T& bar[0] [31:0] $end
+      $var wire 32 U& bar[1] [31:0] $end
+      $var wire 32 V& bar[2] [31:0] $end
+      $var wire 32 W& bar[3] [31:0] $end
+      $var wire 16 X& baz [15:0] $end
+      $var wire 128 Y& qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 ]& field_a $end
+       $var wire 6 ^& field_b [5:0] $end
+       $var wire 10 _& field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_packed_structs[2] $end
+      $var wire 1 `& foo $end
+      $var wire 32 a& bar[0] [31:0] $end
+      $var wire 32 b& bar[1] [31:0] $end
+      $var wire 32 c& bar[2] [31:0] $end
+      $var wire 32 d& bar[3] [31:0] $end
+      $var wire 16 e& baz [15:0] $end
+      $var wire 128 f& qux [127:0] $end
+      $scope module sub_struct $end
+       $var wire 1 j& field_a $end
+       $var wire 6 k& field_b [5:0] $end
+       $var wire 10 l& field_c [9:0] $end
+      $upscope $end
+     $upscope $end
+     $scope module the_local_struct $end
+      $var wire 1 X$ abc $end
+      $var wire 1 Y$ def $end
+      $var wire 1 Z$ xyz $end
+     $upscope $end
+     $scope module const_struct $end
+      $var wire 1 L% abc $end
+      $var wire 1 M% def $end
+      $var wire 1 L% xyz $end
+     $upscope $end
+     $scope module the_typedefed_struct $end
+      $var wire 1 [$ abc $end
+      $var wire 1 \$ def $end
+      $var wire 1 ]$ xyz $end
+     $upscope $end
+     $scope module the_local_unpacked_struct $end
+      $var wire 1 ^$ field_a $end
+      $var wire 1 _$ field_b $end
+      $var wire 1 `$ field_c $end
+     $upscope $end
+     $scope module the_local_union $end
+      $scope module union_a $end
+       $var wire 8 a$ field_0 [7:0] $end
+      $upscope $end
+      $scope module union_b $end
+       $var wire 4 b$ field_1 [3:0] $end
+       $var wire 4 c$ field_2 [3:0] $end
+      $upscope $end
+      $scope module union_c $end
+       $var wire 2 d$ field_3 [1:0] $end
+       $var wire 6 e$ field_4 [5:0] $end
+      $upscope $end
+     $upscope $end
+     $var wire 32 f$ the_logic_array[0] [31:0] $end
+     $var wire 32 g$ the_logic_array[1] [31:0] $end
+     $var wire 32 h$ the_other_logic_array[0] [31:0] $end
+     $var wire 32 i$ the_other_logic_array[1] [31:0] $end
+     $var wire 16 j$ the_unpacked_array[0] [15:0] $end
+     $var wire 16 k$ the_unpacked_array[1] [15:0] $end
+     $var wire 16 l$ the_unpacked_array[2] [15:0] $end
+     $var wire 16 m$ the_unpacked_array[3] [15:0] $end
+     $var wire 16 n$ the_unpacked_array[4] [15:0] $end
+     $var wire 1 o$ the_2d_unpacked[0][0] $end
+     $var wire 1 p$ the_2d_unpacked[0][1] $end
+     $var wire 1 q$ the_2d_unpacked[0][2] $end
+     $var wire 1 r$ the_2d_unpacked[0][3] $end
+     $var wire 1 s$ the_2d_unpacked[1][0] $end
+     $var wire 1 t$ the_2d_unpacked[1][1] $end
+     $var wire 1 u$ the_2d_unpacked[1][2] $end
+     $var wire 1 v$ the_2d_unpacked[1][3] $end
+     $var wire 1 w$ the_2d_unpacked[2][0] $end
+     $var wire 1 x$ the_2d_unpacked[2][1] $end
+     $var wire 1 y$ the_2d_unpacked[2][2] $end
+     $var wire 1 z$ the_2d_unpacked[2][3] $end
+     $var wire 4 N% two_fours[0] [3:0] $end
+     $var wire 4 O% two_fours[1] [3:0] $end
+     $var wire 4 m& two_fours_var[0] [3:0] $end
+     $var wire 4 n& two_fours_var[1] [3:0] $end
+    $upscope $end
+   $upscope $end
+   $scope module the_intf_a $end
+    $var wire 1 $% clk $end
+    $var wire 8 {$ data[0] [7:0] $end
+    $var wire 8 |$ data[1] [7:0] $end
+    $var wire 8 }$ data[2] [7:0] $end
+    $var wire 8 ~$ data[3] [7:0] $end
+    $var wire 32 !% data_typed [31:0] $end
+   $upscope $end
+   $scope module the_intf_b $end
+    $var wire 1 $% clk $end
+    $var wire 8 |$ data[0] [7:0] $end
+    $var wire 8 }$ data[1] [7:0] $end
+    $var wire 8 ~$ data[2] [7:0] $end
+    $var wire 8 "% data[3] [7:0] $end
+    $var wire 32 #% data_typed [31:0] $end
+   $upscope $end
+  $upscope $end
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diff --git a/test_regress/t/t_trace_type_dupes_structs_vcd.py b/test_regress/t/t_trace_type_dupes_structs_vcd.py
new file mode 100755
index 000000000..e2f71b23f
--- /dev/null
+++ b/test_regress/t/t_trace_type_dupes_structs_vcd.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_type_dupes_common
+
+test.scenarios('vlt_all')
+
+trace_type_dupes_common.run(test)
diff --git a/test_regress/t/t_trace_ub_misaligned_address.out b/test_regress/t/t_trace_ub_misaligned_address.out
index 1fe9f3feb..e69de29bb 100644
--- a/test_regress/t/t_trace_ub_misaligned_address.out
+++ b/test_regress/t/t_trace_ub_misaligned_address.out
@@ -1 +0,0 @@
-*-* All Finished *-*
diff --git a/test_regress/t/t_trace_var_kind.v b/test_regress/t/t_trace_var_kind.v
new file mode 100644
index 000000000..4e2e679b7
--- /dev/null
+++ b/test_regress/t/t_trace_var_kind.v
@@ -0,0 +1,32 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Wilson Snyder
+// SPDX-License-Identifier: CC0-1.0
+
+module t (
+    input clk
+);
+
+  int cnt;
+
+  typedef struct packed {
+    logic foo;
+    logic bar;
+  } struct_t;
+
+  wire struct_t struct_wire;
+  var struct_t struct_logic;
+
+  assign struct_wire = '{foo: cnt[0], bar: cnt[1]};
+  always @(posedge clk) struct_logic <= '{foo: ~cnt[0], bar: ~cnt[1]};
+
+  initial cnt = 0;
+  always @(posedge clk) begin
+    cnt <= cnt + 1;
+    if (cnt == 3) begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+    end
+  end
+endmodule
diff --git a/test_regress/t/t_trace_var_kind_cc_fst.out b/test_regress/t/t_trace_var_kind_cc_fst.out
new file mode 100644
index 000000000..7d1482e9a
--- /dev/null
+++ b/test_regress/t/t_trace_var_kind_cc_fst.out
@@ -0,0 +1,67 @@
+$date
+Fri Apr 10 14:01:23 2026
+
+$end
+$version
+Generated by VerilatedFst
+$end
+$timescale
+1ps
+$end
+ $scope module top $end
+  $var wire 1 ! clk $end
+  $scope module t $end
+   $var wire 1 ! clk $end
+   $var int 32 " cnt [31:0] $end
+   $attrbegin pack packed members 2 $end
+   $scope struct struct_wire $end
+    $var wire 1 # foo $end
+    $var wire 1 $ bar $end
+   $upscope $end
+   $attrbegin pack packed members 2 $end
+   $scope struct struct_logic $end
+    $var logic 1 % foo $end
+    $var logic 1 & bar $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+0&
+0%
+0$
+0#
+b00000000000000000000000000000000 "
+0!
+$end
+#10
+1!
+b00000000000000000000000000000001 "
+1#
+1%
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+0!
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+1!
+0%
+0#
+b00000000000000000000000000000100 "
+0$
diff --git a/test_regress/t/t_trace_var_kind_cc_fst.py b/test_regress/t/t_trace_var_kind_cc_fst.py
new file mode 100755
index 000000000..47ead2293
--- /dev/null
+++ b/test_regress/t/t_trace_var_kind_cc_fst.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_var_kind_common
+
+test.scenarios('vlt_all')
+
+trace_var_kind_common.run(test)
diff --git a/test_regress/t/t_trace_var_kind_cc_saif.out b/test_regress/t/t_trace_var_kind_cc_saif.out
new file mode 100644
index 000000000..14ce57aca
--- /dev/null
+++ b/test_regress/t/t_trace_var_kind_cc_saif.out
@@ -0,0 +1,63 @@
+// Generated by verilated_saif
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(PROGRAM_NAME "Verilator")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 40)
+ (INSTANCE top
+  (NET
+   (clk (T0 25) (T1 15) (TZ 0) (TX 0) (TB 0) (TC 7))
+  )
+  (INSTANCE t
+   (NET
+    (clk (T0 25) (T1 15) (TZ 0) (TX 0) (TB 0) (TC 7))
+    (cnt\[0\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+    (cnt\[1\] (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
+    (cnt\[2\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (cnt\[3\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[4\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[5\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[6\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[7\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[8\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[9\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[10\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[11\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[12\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[13\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[14\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[15\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[16\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[17\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[18\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[19\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[20\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[21\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[22\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[23\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[24\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[25\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[26\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[27\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[28\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[29\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[30\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cnt\[31\] (T0 40) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   )
+   (INSTANCE struct_wire
+    (NET
+     (foo (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+     (bar (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
+    )
+   )
+   (INSTANCE struct_logic
+    (NET
+     (foo (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 4))
+     (bar (T0 20) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 2))
+    )
+   )
+  )
+ )
+)
diff --git a/test_regress/t/t_trace_var_kind_cc_saif.py b/test_regress/t/t_trace_var_kind_cc_saif.py
new file mode 100755
index 000000000..47ead2293
--- /dev/null
+++ b/test_regress/t/t_trace_var_kind_cc_saif.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_var_kind_common
+
+test.scenarios('vlt_all')
+
+trace_var_kind_common.run(test)
diff --git a/test_regress/t/t_trace_var_kind_cc_vcd.out b/test_regress/t/t_trace_var_kind_cc_vcd.out
new file mode 100644
index 000000000..fe80a0834
--- /dev/null
+++ b/test_regress/t/t_trace_var_kind_cc_vcd.out
@@ -0,0 +1,57 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module top $end
+  $var wire 1 ' clk $end
+  $scope module t $end
+   $var wire 1 ' clk $end
+   $var wire 32 " cnt [31:0] $end
+   $scope module struct_wire $end
+    $var wire 1 # foo $end
+    $var wire 1 $ bar $end
+   $upscope $end
+   $scope module struct_logic $end
+    $var wire 1 % foo $end
+    $var wire 1 & bar $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 "
+0#
+0$
+0%
+0&
+0'
+#10
+b00000000000000000000000000000001 "
+1#
+1%
+1&
+1'
+#15
+0'
+#20
+b00000000000000000000000000000010 "
+0#
+1$
+0%
+1'
+#25
+0'
+#30
+b00000000000000000000000000000011 "
+1#
+1%
+0&
+1'
+#35
+0'
+#40
+b00000000000000000000000000000100 "
+0#
+0$
+0%
+1'
diff --git a/test_regress/t/t_trace_var_kind_cc_vcd.py b/test_regress/t/t_trace_var_kind_cc_vcd.py
new file mode 100755
index 000000000..47ead2293
--- /dev/null
+++ b/test_regress/t/t_trace_var_kind_cc_vcd.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_var_kind_common
+
+test.scenarios('vlt_all')
+
+trace_var_kind_common.run(test)
diff --git a/test_regress/t/t_trace_var_kind_sc_fst.out b/test_regress/t/t_trace_var_kind_sc_fst.out
new file mode 100644
index 000000000..b1d445258
--- /dev/null
+++ b/test_regress/t/t_trace_var_kind_sc_fst.out
@@ -0,0 +1,67 @@
+$date
+Mon Apr 13 08:56:28 2026
+
+$end
+$version
+Generated by VerilatedFst
+$end
+$timescale
+1ps
+$end
+ $scope module top $end
+  $scope module t $end
+   $var wire 1 ! clk $end
+   $var int 32 " cnt [31:0] $end
+   $attrbegin pack packed members 2 $end
+   $scope struct struct_wire $end
+    $var wire 1 # foo $end
+    $var wire 1 $ bar $end
+   $upscope $end
+   $attrbegin pack packed members 2 $end
+   $scope struct struct_logic $end
+    $var logic 1 % foo $end
+    $var logic 1 & bar $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+0&
+0%
+0$
+0#
+b00000000000000000000000000000000 "
+0!
+$end
+#10
+1!
+b00000000000000000000000000000001 "
+1#
+1%
+1&
+#15
+0!
+#20
+1!
+0%
+0#
+b00000000000000000000000000000010 "
+1$
+#25
+0!
+#30
+1!
+b00000000000000000000000000000011 "
+1#
+1%
+0&
+#35
+0!
+#40
+1!
+0%
+0#
+b00000000000000000000000000000100 "
+0$
+#44
diff --git a/test_regress/t/t_trace_var_kind_sc_fst.py b/test_regress/t/t_trace_var_kind_sc_fst.py
new file mode 100755
index 000000000..47ead2293
--- /dev/null
+++ b/test_regress/t/t_trace_var_kind_sc_fst.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_var_kind_common
+
+test.scenarios('vlt_all')
+
+trace_var_kind_common.run(test)
diff --git a/test_regress/t/t_trace_var_kind_sc_vcd.out b/test_regress/t/t_trace_var_kind_sc_vcd.out
new file mode 100644
index 000000000..db53c8a29
--- /dev/null
+++ b/test_regress/t/t_trace_var_kind_sc_vcd.out
@@ -0,0 +1,57 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module top $end
+  $scope module t $end
+   $var wire 1 ' clk $end
+   $var wire 32 " cnt [31:0] $end
+   $scope module struct_wire $end
+    $var wire 1 # foo $end
+    $var wire 1 $ bar $end
+   $upscope $end
+   $scope module struct_logic $end
+    $var wire 1 % foo $end
+    $var wire 1 & bar $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 "
+0#
+0$
+0%
+0&
+0'
+#10
+b00000000000000000000000000000001 "
+1#
+1%
+1&
+1'
+#15
+0'
+#20
+b00000000000000000000000000000010 "
+0#
+1$
+0%
+1'
+#25
+0'
+#30
+b00000000000000000000000000000011 "
+1#
+1%
+0&
+1'
+#35
+0'
+#40
+b00000000000000000000000000000100 "
+0#
+0$
+0%
+1'
+#44
diff --git a/test_regress/t/t_trace_var_kind_sc_vcd.py b/test_regress/t/t_trace_var_kind_sc_vcd.py
new file mode 100755
index 000000000..47ead2293
--- /dev/null
+++ b/test_regress/t/t_trace_var_kind_sc_vcd.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_var_kind_common
+
+test.scenarios('vlt_all')
+
+trace_var_kind_common.run(test)
diff --git a/test_regress/t/trace_complex_common.py b/test_regress/t/trace_complex_common.py
index 388ae333e..f7764819f 100644
--- a/test_regress/t/trace_complex_common.py
+++ b/test_regress/t/trace_complex_common.py
@@ -34,6 +34,10 @@ def run(test, *, verilator_flags2=()):
     # Run test
     test.compile(verilator_flags2=flags)
 
+    if variant == "structs":
+        trace_cpp = test.obj_dir + "/" + test.vm_prefix + "__Trace__0.cpp"
+        test.file_grep(trace_cpp, r"^ *Vt_.*trace_chg_dtype.*v_strp2")
+
     test.execute()
 
     test.trace_identical(test.trace_filename, test.golden_filename)
diff --git a/test_regress/t/trace_split_struct_common.py b/test_regress/t/trace_split_struct_common.py
new file mode 100644
index 000000000..8599faeea
--- /dev/null
+++ b/test_regress/t/trace_split_struct_common.py
@@ -0,0 +1,29 @@
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+
+def run(test):
+    (fmt, ) = test.parse_name(r"t_trace_split_struct_([a-z]+)")
+
+    test.top_filename = "t/t_trace_split_struct.v"
+    test.golden_filename = test.py_filename.rpartition(fmt)[0] + fmt + ".out"
+
+    flags = ["--cc", f"--trace-{fmt}", "--trace-structs", "--no-trace-params"]
+
+    test.compile(verilator_flags2=flags)
+
+    # When struct fields are driven from different clocks, the dtype
+    # optimization cannot be applied -- no trace_chg_dtype functions should exist
+    trace_cpp = test.obj_dir + "/" + test.vm_prefix + "__Trace__0.cpp"
+    test.file_grep_count(trace_cpp, r"^ *Vt_.*trace_chg_dtype", 0)
+
+    test.execute()
+
+    test.trace_identical(test.trace_filename, test.golden_filename)
+
+    test.passes()
diff --git a/test_regress/t/trace_struct_alias_common.py b/test_regress/t/trace_struct_alias_common.py
new file mode 100644
index 000000000..e5e418f68
--- /dev/null
+++ b/test_regress/t/trace_struct_alias_common.py
@@ -0,0 +1,36 @@
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+
+def run(test):
+    (fmt, ) = test.parse_name(r"t_trace_struct_alias_([a-z]+)")
+
+    test.top_filename = "t/t_trace_struct_alias.v"
+    test.golden_filename = test.py_filename.rpartition(fmt)[0] + fmt + ".out"
+
+    flags = ["--cc", f"--trace-{fmt}", "--trace-structs"]
+
+    test.compile(verilator_flags2=flags)
+
+    test.execute()
+
+    if fmt == "vcd":
+        codes = test.vcd_extract_codes(test.trace_filename)
+
+        test.vcd_check_not_aliased(codes, "top.t.s1.a", "top.t.s2.a")
+
+        test.vcd_check_aliased(codes, "top.t.s3.a", "top.t.alias_of_s3a")
+
+        test.vcd_check_aliased(codes, "top.t.s4.a", "top.t.s5.a")
+        test.vcd_check_aliased(codes, "top.t.s4.b", "top.t.s5.b")
+
+        test.vcd_check_aliased(codes, "top.t.s6.a", "top.t.source_val")
+
+    test.trace_identical(test.trace_filename, test.golden_filename)
+
+    test.passes()
diff --git a/test_regress/t/trace_struct_array_multi_inst_common.py b/test_regress/t/trace_struct_array_multi_inst_common.py
new file mode 100644
index 000000000..e22d1f83c
--- /dev/null
+++ b/test_regress/t/trace_struct_array_multi_inst_common.py
@@ -0,0 +1,84 @@
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import re
+
+
+def _check_empty_scopes_vcd(test, vcd_filename):
+    with open(vcd_filename, "r", encoding="utf-8") as f:
+        lines = f.readlines()
+
+    scope_stack = []
+    for line in lines:
+        line = line.strip()
+        if "$scope" in line:
+            scope_stack.append({"name": line, "has_var": False})
+        elif "$var" in line:
+            for scope in scope_stack:
+                scope["has_var"] = True
+        elif "$upscope" in line:
+            if scope_stack:
+                scope = scope_stack.pop()
+                if not scope["has_var"]:
+                    test.error("Empty scope hierarchy: " + scope["name"] +
+                               " (no variables in scope or any child scopes)")
+        elif "$enddefinitions" in line:
+            break
+
+
+def _check_empty_scopes_saif(test, saif_filename):
+    with open(saif_filename, "r", encoding="utf-8") as f:
+        content = f.read()
+
+    instance_stack = []
+    for line in content.splitlines():
+        stripped = line.strip()
+        m = re.match(r"\(INSTANCE\s+(\S+)", stripped)
+        if m:
+            instance_stack.append({"name": m.group(1), "has_net": False})
+        elif stripped.startswith("(NET"):
+            for inst in instance_stack:
+                inst["has_net"] = True
+        elif stripped == ")" and instance_stack:
+            inst = instance_stack.pop()
+            if not inst["has_net"]:
+                test.error("Empty INSTANCE in SAIF: " + inst["name"] +
+                           " (no NET in instance or any child instances)")
+
+
+def run(test):
+    mode, fmt = test.parse_name(r"t_trace_struct_array_multi_inst_(cc|sc)_([a-z]+)")
+
+    if mode == "sc" and not test.have_sc:
+        test.skip("No SystemC installed")
+
+    test.top_filename = "t/t_trace_struct_array_multi_inst.v"
+    test.golden_filename = test.py_filename.rpartition(fmt)[0] + fmt + ".out"
+
+    flags = [
+        f"--{mode}",
+        f"--trace-{fmt}",
+        "--trace-structs",
+        "--output-split-ctrace",
+        "10",
+    ]
+
+    test.compile(verilator_flags2=flags)
+
+    test.execute()
+
+    test.trace_identical(test.trace_filename, test.golden_filename)
+
+    if fmt == "fst":
+        _check_empty_scopes_vcd(test, test.trace_filename + ".vcd")
+    elif fmt == "vcd":
+        _check_empty_scopes_vcd(test, test.trace_filename)
+    elif fmt == "saif":
+        _check_empty_scopes_saif(test, test.trace_filename)
+
+    test.passes()
diff --git a/test_regress/t/trace_type_dupes_common.py b/test_regress/t/trace_type_dupes_common.py
new file mode 100644
index 000000000..300391b27
--- /dev/null
+++ b/test_regress/t/trace_type_dupes_common.py
@@ -0,0 +1,31 @@
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+
+def run(test):
+    variant, fmt = test.parse_name(r"t_trace_type_dupes_([a-z]+)_([a-z]+)")
+
+    test.top_filename = "t/t_trace_type_dupes.v"
+    test.golden_filename = test.py_filename.rpartition(fmt)[0] + fmt + ".out"
+
+    flags = ["--cc", f"--trace-{fmt}"]
+    match variant:
+        case "default":
+            pass
+        case "structs":
+            flags.extend(["--trace-structs", "--output-split-ctrace 10"])
+        case _:
+            test.error(f"Unhandled test variant '{variant}'")
+
+    test.compile(verilator_flags2=flags)
+
+    test.execute()
+
+    test.trace_identical(test.trace_filename, test.golden_filename)
+
+    test.passes()
diff --git a/test_regress/t/trace_var_kind_common.py b/test_regress/t/trace_var_kind_common.py
new file mode 100644
index 000000000..bb4208f51
--- /dev/null
+++ b/test_regress/t/trace_var_kind_common.py
@@ -0,0 +1,27 @@
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+
+def run(test):
+    mode, fmt = test.parse_name(r"t_trace_var_kind_(cc|sc)_([a-z]+)")
+
+    if mode == "sc" and not test.have_sc:
+        test.skip("No SystemC installed")
+
+    test.top_filename = "t/t_trace_var_kind.v"
+    test.golden_filename = test.py_filename.rpartition(fmt)[0] + fmt + ".out"
+
+    flags = [f"--{mode}", f"--trace-{fmt}", "--trace-structs"]
+
+    test.compile(verilator_flags2=flags)
+
+    test.execute()
+
+    test.trace_identical(test.trace_filename, test.golden_filename)
+
+    test.passes()