From 7ef37d6e1752e10c9d17700c3c2a9d48828e72d7 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 30 Oct 2012 03:02:35 -0400 Subject: [PATCH] Fix missing var access functions when no DPI, bug572. --- Changes | 2 ++ src/V3EmitCSyms.cpp | 5 +++-- src/verilog.y | 14 +++++++------- test_regress/t/t_vpi_var.v | 15 +++++++++++++++ 4 files changed, 27 insertions(+), 9 deletions(-) diff --git a/Changes b/Changes index 0144a2f79..66f62a348 100644 --- a/Changes +++ b/Changes @@ -11,6 +11,8 @@ indicates the contributor was also the author of the fix; Thanks! **** Fix $display mangling on GCC 4.7, msg927. [R Diez] +**** Fix missing var access functions when no DPI, bug572. [Amir Gonnen] + * Verilator 3.841 2012/09/03 diff --git a/src/V3EmitCSyms.cpp b/src/V3EmitCSyms.cpp index 0f189a26a..92c02000f 100644 --- a/src/V3EmitCSyms.cpp +++ b/src/V3EmitCSyms.cpp @@ -115,8 +115,8 @@ class EmitCSyms : EmitCBaseVisitor { AstScope* scopep = it->first; AstNodeModule* smodp = it->second; for (vector::iterator it = m_modVars.begin(); it != m_modVars.end(); ++it) { AstNodeModule* modp = it->first; + AstVar* varp = it->second; if (modp == smodp) { - AstVar* varp = it->second; // Need to split the module + var name into the original-ish full scope and variable name under that scope. // The module instance name is included later, when we know the scopes this module is under string whole = scopep->name()+"__DOT__"+varp->name(); @@ -204,7 +204,8 @@ class EmitCSyms : EmitCBaseVisitor { } virtual void visit(AstVar* nodep, AstNUser*) { nodep->iterateChildren(*this); - if (nodep->isSigUserRdPublic()) { + if (nodep->isSigUserRdPublic() + && !nodep->isParam()) { // The VPI functions require a pointer to allow modification, but parameters are constants m_modVars.push_back(make_pair(m_modp, nodep)); } } diff --git a/src/verilog.y b/src/verilog.y index 2e88ad2d9..8bbc8380e 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -1488,7 +1488,7 @@ non_port_module_item: // ==IEEE: non_port_module_item | yaSCDTOR { $$ = new AstScDtor($1,*$1); } | yVL_INLINE_MODULE { $$ = new AstPragma($1,AstPragmaType::INLINE_MODULE); } | yVL_NO_INLINE_MODULE { $$ = new AstPragma($1,AstPragmaType::NO_INLINE_MODULE); } - | yVL_PUBLIC_MODULE { $$ = new AstPragma($1,AstPragmaType::PUBLIC_MODULE); } + | yVL_PUBLIC_MODULE { $$ = new AstPragma($1,AstPragmaType::PUBLIC_MODULE); v3Global.dpi(true); } ; module_or_generate_item: // ==IEEE: module_or_generate_item @@ -1745,11 +1745,11 @@ sigAttrList: sigAttr: yVL_CLOCK { $$ = new AstAttrOf($1,AstAttrType::VAR_CLOCK); } | yVL_CLOCK_ENABLE { $$ = new AstAttrOf($1,AstAttrType::VAR_CLOCK_ENABLE); } - | yVL_PUBLIC { $$ = new AstAttrOf($1,AstAttrType::VAR_PUBLIC); } - | yVL_PUBLIC_FLAT { $$ = new AstAttrOf($1,AstAttrType::VAR_PUBLIC_FLAT); } - | yVL_PUBLIC_FLAT_RD { $$ = new AstAttrOf($1,AstAttrType::VAR_PUBLIC_FLAT_RD); } - | yVL_PUBLIC_FLAT_RW { $$ = new AstAttrOf($1,AstAttrType::VAR_PUBLIC_FLAT_RW); } - | yVL_PUBLIC_FLAT_RW attr_event_control { $$ = new AstAttrOf($1,AstAttrType::VAR_PUBLIC_FLAT_RW); + | yVL_PUBLIC { $$ = new AstAttrOf($1,AstAttrType::VAR_PUBLIC); v3Global.dpi(true); } + | yVL_PUBLIC_FLAT { $$ = new AstAttrOf($1,AstAttrType::VAR_PUBLIC_FLAT); v3Global.dpi(true); } + | yVL_PUBLIC_FLAT_RD { $$ = new AstAttrOf($1,AstAttrType::VAR_PUBLIC_FLAT_RD); v3Global.dpi(true); } + | yVL_PUBLIC_FLAT_RW { $$ = new AstAttrOf($1,AstAttrType::VAR_PUBLIC_FLAT_RW); v3Global.dpi(true); } + | yVL_PUBLIC_FLAT_RW attr_event_control { $$ = new AstAttrOf($1,AstAttrType::VAR_PUBLIC_FLAT_RW); v3Global.dpi(true); $$ = $$->addNext(new AstAlwaysPublic($1,$2,NULL)); } | yVL_ISOLATE_ASSIGNMENTS { $$ = new AstAttrOf($1,AstAttrType::VAR_ISOLATE_ASSIGNMENTS); } | yVL_SC_BV { $$ = new AstAttrOf($1,AstAttrType::VAR_SC_BV); } @@ -2540,7 +2540,7 @@ tf_item_declaration: // ==IEEE: tf_item_declaration ; tf_item_declarationVerilator: // Verilator extensions - yVL_PUBLIC { $$ = new AstPragma($1,AstPragmaType::PUBLIC_TASK); } + yVL_PUBLIC { $$ = new AstPragma($1,AstPragmaType::PUBLIC_TASK); v3Global.dpi(true); } | yVL_NO_INLINE_TASK { $$ = new AstPragma($1,AstPragmaType::NO_INLINE_TASK); } ; diff --git a/test_regress/t/t_vpi_var.v b/test_regress/t/t_vpi_var.v index 8d1aaf00b..2a789b85b 100644 --- a/test_regress/t/t_vpi_var.v +++ b/test_regress/t/t_vpi_var.v @@ -5,12 +5,23 @@ // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +`ifdef VERILATOR +//We call it via $c so we can verify DPI isn't required - see bug572 +`else import "DPI-C" context function integer mon_check(); +`endif module t (/*AUTOARG*/ // Inputs clk ); + +`ifdef VERILATOR +`systemc_header +extern "C" int mon_check(); +`verilog +`endif + input clk; reg onebit /*verilator public_flat_rw @(posedge clk) */; @@ -29,7 +40,11 @@ module t (/*AUTOARG*/ // Test loop initial begin onebit = 1'b0; +`ifdef VERILATOR + status = $c32("mon_check()"); +`else status = mon_check(); +`endif if (status!=0) begin $write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status); $stop;