From 7e3346c84e8afd54209a9038bb1fced83fadee73 Mon Sep 17 00:00:00 2001
From: Mateusz Gancarz <mgancarz@antmicro.com>
Date: Mon, 17 Feb 2025 09:45:58 +0100
Subject: [PATCH] [#72179] add t_trace_array_saif_portable test

---
 test_regress/t/t_trace_array_saif_portable.py | 22 +++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100755 test_regress/t/t_trace_array_saif_portable.py

diff --git a/test_regress/t/t_trace_array_saif_portable.py b/test_regress/t/t_trace_array_saif_portable.py
new file mode 100755
index 000000000..9d49d4549
--- /dev/null
+++ b/test_regress/t/t_trace_array_saif_portable.py
@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+test.top_filename = "t/t_trace_array.v"
+test.golden_filename = "t/t_trace_array_saif.out"
+
+test.compile(verilator_flags2=['--cc --trace-saif --trace-structs', '-CFLAGS -DVL_PORTABLE_ONLY'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()