From 79682e6072571486d028416ad905dd6aa32f08d3 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Thu, 20 Oct 2022 22:04:50 -0400
Subject: [PATCH] Support empty generate_regions (#3695). [mpb27]

---
 Changes                   | 1 +
 src/verilog.y             | 4 ++++
 test_regress/t/t_gen_if.v | 6 ++++++
 3 files changed, 11 insertions(+)

diff --git a/Changes b/Changes
index 822275bef..c24211e13 100644
--- a/Changes
+++ b/Changes
@@ -34,6 +34,7 @@ Verilator 5.001 devel
 * Support standalone 'this' in classes (#2594) (#3248) (#3675). [Arkadiusz Kozdra, Antmicro Ltd]
 * Support tristate select/extend (#3604). [Ryszard Rozak, Antmicro Ltd>
 * Support linting for top module interfaces (#3635). [Kanad Kanhere]
+* Support empty generate_regions (#3695). [mpb27]
 * Add --dump-tree-dot to enable dumping Ast Tree .dot files (#3636). [Marcel Chang]
 * Add --get-supported to determine what features are in Verilator.
 * Add error on real edge event control.
diff --git a/src/verilog.y b/src/verilog.y
index 256c530db..c73dad6e4 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -1645,6 +1645,8 @@ program_generate_item<nodep>:           // ==IEEE: program_generate_item
                 loop_generate_construct                 { $$ = $1; }
         |       conditional_generate_construct          { $$ = $1; }
         |       generate_region                         { $$ = $1; }
+                                // not in IEEE, but presumed so can do yBEGIN ... yEND
+        |       genItemBegin                            { $$ = $1; }
         |       elaboration_system_task                 { $$ = $1; }
         ;
 
@@ -2424,6 +2426,8 @@ module_item<nodep>:             // ==IEEE: module_item
 
 non_port_module_item<nodep>:    // ==IEEE: non_port_module_item
                 generate_region                         { $$ = $1; }
+                                // not in IEEE, but presumed so can do yBEGIN ... yEND
+        |       genItemBegin                            { $$ = $1; }
         |       module_or_generate_item                 { $$ = $1; }
         |       specify_block                           { $$ = $1; }
         |       specparam_declaration                   { $$ = $1; }
diff --git a/test_regress/t/t_gen_if.v b/test_regress/t/t_gen_if.v
index 3a3f8dc0c..acbd2eb12 100644
--- a/test_regress/t/t_gen_if.v
+++ b/test_regress/t/t_gen_if.v
@@ -14,6 +14,12 @@ module t(data_i, data_o, single);
    output [31:0] data_o;
    input single;
 
+   // Bare begin/end extension of IEEE allowed by most all tools
+   begin
+   end
+   begin : named
+   end : named
+
    //simplistic example, should choose 1st conditional generate and assign straight through
    //the tool also compiles the special case and determines an error (replication value is 0
    generate