diff --git a/test_regress/t/t_trace_array_saif.out b/test_regress/t/t_trace_array_saif.out
new file mode 100644
index 000000000..fb5e7213f
--- /dev/null
+++ b/test_regress/t/t_trace_array_saif.out
@@ -0,0 +1,20 @@
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(DESIGN "foo")
+(PROGRAM_NAME "Verilator")
+(VERSION "5.032")
+(DIVIDER .)
+(TIMESCALE 1ps)
+(DURATION 60)
+(INSTANCE foo (NET
+(d[1] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 1))
+(d[2] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+(d[3] (T0 50) (T1 10) (TZ 0) (TX 0) (TB 0) (TC 1))
+(d[4] (T0 60) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+(d[32] (T0 20) (T1 40) (TZ 0) (TX 0) (TB 0) (TC 1))
+(cyc[0] (T0 30) (T1 30) (TZ 0) (TX 0) (TB 0) (TC 6))
+(cyc[1] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 3))
+(cyc[2] (T0 40) (T1 20) (TZ 0) (TX 0) (TB 0) (TC 1))
+(clk (T0 35) (T1 25) (TZ 0) (TX 0) (TB 0) (TC 11))
+)))
diff --git a/test_regress/t/t_trace_array_saif.py b/test_regress/t/t_trace_array_saif.py
new file mode 100755
index 000000000..bba805c29
--- /dev/null
+++ b/test_regress/t/t_trace_array_saif.py
@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+test.top_filename = "t/t_trace_array.v"
+
+test.compile(verilator_flags2=['--cc --trace --trace-structs'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()