From f32a4223302769aa55e35e871e67823a99fb90b2 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Mon, 2 Apr 2012 19:38:42 -0400
Subject: [PATCH 1/2] Tests: New test

---
 test_regress/t/t_package_ddecl.pl | 20 ++++++++++++++++++++
 test_regress/t/t_package_ddecl.v  | 30 ++++++++++++++++++++++++++++++
 2 files changed, 50 insertions(+)
 create mode 100755 test_regress/t/t_package_ddecl.pl
 create mode 100644 test_regress/t/t_package_ddecl.v

diff --git a/test_regress/t/t_package_ddecl.pl b/test_regress/t/t_package_ddecl.pl
new file mode 100755
index 000000000..eb1f82e1f
--- /dev/null
+++ b/test_regress/t/t_package_ddecl.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} and $Self->unsupported("Verilator unsupported, bug474");
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_package_ddecl.v b/test_regress/t/t_package_ddecl.v
new file mode 100644
index 000000000..af51139d8
--- /dev/null
+++ b/test_regress/t/t_package_ddecl.v
@@ -0,0 +1,30 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012 by Wilson Snyder.
+
+// see bug 474
+package functions;
+   localparam LP_PACK = 512;
+   localparam LP_PACK_AND_MOD = 19;
+   task check_param;
+      $display("In %m\n");  // "In functions::check_param"
+      if (LP_PACK_AND_MOD != 19) $stop;
+   endtask
+endpackage
+
+module t ();
+   // synthesis translate off
+   import functions::*;
+   // synthesis translate on
+   localparam LP_PACK_AND_MOD = 20;
+   initial begin
+      #10;
+      if (LP_PACK_AND_MOD != 20) $stop;
+      check_param();
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule
+
+						
\ No newline at end of file

From d45d58b6bfbcafbca44bdaaf6f46c154a8819ec0 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Mon, 2 Apr 2012 21:58:40 -0400
Subject: [PATCH 2/2] Fix real constant parameter functions, bug475.

---
 Changes                             |  2 ++
 src/V3Number.cpp                    |  3 ++-
 src/V3Number.h                      |  1 +
 src/V3Simulate.h                    |  1 +
 test_regress/t/t_func_real_param.pl | 18 ++++++++++++++++++
 test_regress/t/t_func_real_param.v  | 27 +++++++++++++++++++++++++++
 6 files changed, 51 insertions(+), 1 deletion(-)
 create mode 100755 test_regress/t/t_func_real_param.pl
 create mode 100644 test_regress/t/t_func_real_param.v

diff --git a/Changes b/Changes
index 784364ed6..9092bf991 100644
--- a/Changes
+++ b/Changes
@@ -14,6 +14,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Fix genvar and begin under generate, bug461.  [Alex Solomatnikov]
 
+****  Fix real constant parameter functions, bug475.  [Alex Solomatnikov]
+
 ****  Fix and document --gdb option, bug454. [Jeremy Bennett]
 
 ****  Fix OpenSolaris compile error. [Sanjay Singh]
diff --git a/src/V3Number.cpp b/src/V3Number.cpp
index 70fb13d0a..463399ffd 100644
--- a/src/V3Number.cpp
+++ b/src/V3Number.cpp
@@ -339,7 +339,8 @@ string V3Number::ascii(bool prefixed, bool cleanVerilog) const {
 
     if (isDouble()) {
 	out.precision(17);
-	out<<toDouble();
+	if (width()!=64) out<<"%E-bad-width-double";
+	else out<<toDouble();
 	return out.str();
     }
     if (prefixed) {
diff --git a/src/V3Number.h b/src/V3Number.h
index a74f0ea8b..20fd5e02b 100644
--- a/src/V3Number.h
+++ b/src/V3Number.h
@@ -156,6 +156,7 @@ public:
     bool isFromString() const { return m_fromString; }
     bool isSigned() const { return m_signed; }	// Only correct for parsing of numbers from strings, otherwise not used (use AstConst::isSigned())
     bool isDouble() const { return m_double; }	// Only correct for parsing of numbers from strings, otherwise not used (use AstConst::isSigned())
+    void isDouble(bool flag)  { m_double=flag; } // Only if have 64 bit value loaded, and want to indicate it's real
     bool isNegative() const { return bitIs1(width()-1); }
     bool isFourState() const { for (int i=0;i<words();i++) {if (m_valueX[i]) return true;} return false; }
     bool hasZ() const { for(int i=0;i<words();i++) {if((~m_value[i]) & m_valueX[i]) return true;} return false;}
diff --git a/src/V3Simulate.h b/src/V3Simulate.h
index 0954523dd..d9a7c20bc 100644
--- a/src/V3Simulate.h
+++ b/src/V3Simulate.h
@@ -144,6 +144,7 @@ private:
 	    nump = new V3Number (nodep->fileline(), nodep->width(), value);
 	    m_numAllps.push_back(nump);
 	}
+	nump->isDouble(nodep->isDouble());
 	return nump;
     }
 public:
diff --git a/test_regress/t/t_func_real_param.pl b/test_regress/t/t_func_real_param.pl
new file mode 100755
index 000000000..7058e622f
--- /dev/null
+++ b/test_regress/t/t_func_real_param.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_func_real_param.v b/test_regress/t/t_func_real_param.v
new file mode 100644
index 000000000..62c8a1830
--- /dev/null
+++ b/test_regress/t/t_func_real_param.v
@@ -0,0 +1,27 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012 by Wilson Snyder.
+
+// bug475
+
+module t();
+
+   function real get_real_one;
+      input 	      ignored;
+      get_real_one = 1.1;
+   endfunction
+
+   localparam R_PARAM = get_real_one(1'b0);
+   localparam R_PARAM_2 = (R_PARAM > 0);
+
+   generate
+      initial begin
+	 if (R_PARAM != 1.1) $stop;
+	 if (R_PARAM_2 != 1'b1) $stop;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   endgenerate
+
+endmodule