diff --git a/Changes b/Changes
index aac6d50ff..8254e2147 100644
--- a/Changes
+++ b/Changes
@@ -14,6 +14,7 @@ Verilator 5.033 devel
 **Minor:**
 
 * Support generated classes (#5665). [Shou-Li Hsu]
+* Support `+incdir` with multiple directories.
 * Fix error message when call task as a function (#3089). [Matthew Ballance]
 * Fix V3Simulate constant reuse (#5709). [Geza Lore]
 * Fix man pages what-is section (#5710). [Ahmed El-Mahmoudy]
diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst
index 7afdb5df6..1f653d652 100644
--- a/docs/guide/exe_verilator.rst
+++ b/docs/guide/exe_verilator.rst
@@ -751,7 +751,10 @@ Summary:
 
 .. option:: +incdir+<dir>
 
-   See :vlopt:`-y`.
+   See :vlopt:`-y`.  Unlike with :vlopt:`-y`, multiple directories may be
+   specified separated with a `+` symbol; this is for Verilog-XL
+   compatibility and is not recommended usage as this is not supported by
+   some third-party tools.
 
 .. option:: --inline-mult <value>
 
diff --git a/src/V3Options.cpp b/src/V3Options.cpp
index 7a7714b1e..5e78fd40e 100644
--- a/src/V3Options.cpp
+++ b/src/V3Options.cpp
@@ -1127,8 +1127,15 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc,
     // Plus options
     DECL_OPTION("+define+", CbPartialMatch,
                 [this](const char* optp) VL_MT_DISABLED { addDefine(optp, true); });
-    DECL_OPTION("+incdir+", CbPartialMatch,
-                [this, &optdir](const char* optp) { addIncDirUser(parseFileArg(optdir, optp)); });
+    DECL_OPTION("+incdir+", CbPartialMatch, [this, &optdir](const char* optp) {
+        string dirs = optp;
+        string::size_type pos;
+        while ((pos = dirs.find('+')) != string::npos) {
+            addIncDirUser(parseFileArg(optdir, dirs.substr(0, pos)));
+            dirs = dirs.substr(pos + 1);
+        }
+        addIncDirUser(parseFileArg(optdir, dirs));
+    });
     DECL_OPTION("+libext+", CbPartialMatch, [this](const char* optp) {
         string exts = optp;
         string::size_type pos;
diff --git a/test_regress/t/t_flag_incdir.py b/test_regress/t/t_flag_incdir.py
new file mode 100755
index 000000000..a4f25aabb
--- /dev/null
+++ b/test_regress/t/t_flag_incdir.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.lint(verilator_flags2=['+incdir+ignore1+t/tsub+ignore2'])
+
+test.passes()
diff --git a/test_regress/t/t_flag_incdir.v b/test_regress/t/t_flag_incdir.v
new file mode 100644
index 000000000..7fbf7d202
--- /dev/null
+++ b/test_regress/t/t_flag_incdir.v
@@ -0,0 +1,14 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`include "t_flag_f_tsub_inc.v"
+
+`ifndef GOT_DEF5
+`error "No GOT_DEF5"
+`endif
+
+module t (/*AUTOARG*/);
+endmodule