diff --git a/test_regress/driver.py b/test_regress/driver.py
index 828fe5ac5..ec61e0534 100755
--- a/test_regress/driver.py
+++ b/test_regress/driver.py
@@ -2368,6 +2368,10 @@ class VlTest:
         self.fst2vcd(fn1, tmp)
         self.vcd_identical(tmp, fn2)
 
+    def saif_identical(self, fn1: str, fn2: str) -> None:
+        """Test if two SAIF files have logically-identical contents"""
+        #TODO: implement checking if two SAIF file are logically-identical
+
     def _vcd_read(self, filename: str) -> str:
         data = {}
         with open(filename, 'r', encoding='latin-1') as fh:
diff --git a/test_regress/t/t_hier_block_sc_trace_saif.py b/test_regress/t/t_hier_block_sc_trace_saif.py
new file mode 100755
index 000000000..8380974c7
--- /dev/null
+++ b/test_regress/t/t_hier_block_sc_trace_saif.py
@@ -0,0 +1,39 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+test.top_filename = "t/t_hier_block.v"
+
+# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist.
+test.clean_objs()
+
+# CI environment offers 2 VCPUs, 2 thread setting causes the following warning.
+# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads.
+# So use 6 threads here though it's not optimal in performance, but ok.
+
+test.compile(v_flags2=['t/t_hier_block.cpp'],
+             verilator_flags2=[
+                 '--sc', '--stats', '--hierarchical', '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"',
+                 "--CFLAGS", '"-O0 -ggdb"', "--trace-saif"
+             ],
+             threads=(6 if test.vltmt else 1))
+
+test.execute()
+
+test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0")
+test.file_grep(test.obj_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1")
+test.file_grep(test.obj_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2")
+test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14)
+test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus")
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_hier_block_trace_saif.py b/test_regress/t/t_hier_block_trace_saif.py
new file mode 100755
index 000000000..254156804
--- /dev/null
+++ b/test_regress/t/t_hier_block_trace_saif.py
@@ -0,0 +1,33 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+test.top_filename = "t/t_hier_block.v"
+
+# CI environment offers 2 VCPUs, 2 thread setting causes the following warning.
+# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads.
+# So use 6 threads here though it's not optimal in performance, but ok.
+
+test.compile(
+    v_flags2=['t/t_hier_block.cpp'],
+    verilator_flags2=[
+        '--hierarchical',
+        '--Wno-TIMESCALEMOD',
+        '--trace-saif',
+        '--no-trace-underscore',  # To avoid handle mismatches
+    ],
+    threads=(6 if test.vltmt else 1))
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_interface_ref_trace_saif.py b/test_regress/t/t_interface_ref_trace_saif.py
new file mode 100755
index 000000000..3ebe41194
--- /dev/null
+++ b/test_regress/t/t_interface_ref_trace_saif.py
@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_interface_ref_trace.v"
+
+test.compile(verilator_flags2=['--trace-structs --trace-saif'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_interface_ref_trace_saif_sc.py b/test_regress/t/t_interface_ref_trace_saif_sc.py
new file mode 100755
index 000000000..9015b11dd
--- /dev/null
+++ b/test_regress/t/t_interface_ref_trace_saif_sc.py
@@ -0,0 +1,23 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_interface_ref_trace.v"
+
+if not test.have_sc:
+    test.skip("No SystemC installed")
+
+test.compile(verilator_flags2=['--trace-structs --trace-saif --sc'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+test.passes()
diff --git a/test_regress/t/t_timing_trace_saif.py b/test_regress/t/t_timing_trace_saif.py
new file mode 100755
index 000000000..b5bd921eb
--- /dev/null
+++ b/test_regress/t/t_timing_trace_saif.py
@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_timing_trace.v"
+
+test.compile(verilator_flags2=["--exe --main --timing --trace-saif -Wno-MINTYPMAXDLY"])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_abort_saif.py b/test_regress/t/t_trace_abort_saif.py
new file mode 100755
index 000000000..2053a1bcd
--- /dev/null
+++ b/test_regress/t/t_trace_abort_saif.py
@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+test.top_filename = "t/t_trace_abort.v"
+
+test.compile(verilator_flags2=['--cc --trace-saif'])
+
+test.execute(fails=True)
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_abort_saif_sc.py b/test_regress/t/t_trace_abort_saif_sc.py
new file mode 100755
index 000000000..3bdffa73d
--- /dev/null
+++ b/test_regress/t/t_trace_abort_saif_sc.py
@@ -0,0 +1,24 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+test.top_filename = "t/t_trace_abort.v"
+
+if not test.have_sc:
+    test.skip("No SystemC installed")
+
+test.compile(verilator_flags2=['--sc --trace-saif'])
+
+test.execute(fails=True)
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_array_saif.py b/test_regress/t/t_trace_array_saif.py
index 9a271de06..e9a4c8abc 100755
--- a/test_regress/t/t_trace_array_saif.py
+++ b/test_regress/t/t_trace_array_saif.py
@@ -1,8 +1,8 @@
 #!/usr/bin/env python3
-# DESCRIPTION: Verilator: Verilog Test module
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2025 by Antmicro. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
@@ -12,11 +12,10 @@ import vltest_bootstrap
 test.scenarios('vlt')
 test.top_filename = "t/t_trace_array.v"
 
-test.compile(verilator_flags2=['--trace-saif --trace-structs'])
+test.compile(verilator_flags2=['--cc --trace-saif --trace-structs'])
 
 test.execute()
 
-#TODO: add checking if two SAIF files are identical
-#test.saif_identical(test.trace_filename, test.golden_filename)
+test.saif_identical(test.trace_filename, test.golden_filename)
 
 test.passes()
diff --git a/test_regress/t/t_trace_array_saif_portable.py b/test_regress/t/t_trace_array_saif_portable.py
new file mode 100755
index 000000000..73fa92133
--- /dev/null
+++ b/test_regress/t/t_trace_array_saif_portable.py
@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+test.top_filename = "t/t_trace_array.v"
+test.golden_filename = "t/t_trace_array_fst.out"
+
+test.compile(verilator_flags2=['--cc --trace-saif --trace-structs', '-CFLAGS -DVL_PORTABLE_ONLY'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_array_saif_portable_sc.py b/test_regress/t/t_trace_array_saif_portable_sc.py
new file mode 100755
index 000000000..6dfeee2ab
--- /dev/null
+++ b/test_regress/t/t_trace_array_saif_portable_sc.py
@@ -0,0 +1,25 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+test.top_filename = "t/t_trace_array.v"
+test.golden_filename = "t/t_trace_array_fst_sc.out"
+
+if not test.have_sc:
+    test.skip("No SystemC installed")
+
+test.compile(verilator_flags2=['--sc --trace-saif --trace-structs', '-CFLAGS -DVL_PORTABLE_ONLY'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_array_saif_sc.py b/test_regress/t/t_trace_array_saif_sc.py
new file mode 100755
index 000000000..0b6db4657
--- /dev/null
+++ b/test_regress/t/t_trace_array_saif_sc.py
@@ -0,0 +1,24 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+test.top_filename = "t/t_trace_array.v"
+
+if not test.have_sc:
+    test.skip("No SystemC installed")
+
+test.compile(verilator_flags2=['--sc --trace-saif --trace-structs'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_array_saif_threads_1.py b/test_regress/t/t_trace_array_saif_threads_1.py
new file mode 100755
index 000000000..71b7fd55d
--- /dev/null
+++ b/test_regress/t/t_trace_array_saif_threads_1.py
@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+test.top_filename = "t/t_trace_array.v"
+test.golden_filename = "t/t_trace_array_fst.out"
+
+test.compile(verilator_flags2=['--cc --trace-saif --trace-threads 1 --trace-structs'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_array_saif_threads_1_sc.py b/test_regress/t/t_trace_array_saif_threads_1_sc.py
new file mode 100755
index 000000000..b30a0e210
--- /dev/null
+++ b/test_regress/t/t_trace_array_saif_threads_1_sc.py
@@ -0,0 +1,25 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+test.top_filename = "t/t_trace_array.v"
+test.golden_filename = "t/t_trace_array_fst_sc.out"
+
+if not test.have_sc:
+    test.skip("No SystemC installed")
+
+test.compile(verilator_flags2=['--sc --trace-saif --trace-threads 1 --trace-structs'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_array_saif_threads_2.py b/test_regress/t/t_trace_array_saif_threads_2.py
new file mode 100755
index 000000000..569f92e48
--- /dev/null
+++ b/test_regress/t/t_trace_array_saif_threads_2.py
@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+test.top_filename = "t/t_trace_array.v"
+test.golden_filename = "t/t_trace_array_fst.out"
+
+test.compile(verilator_flags2=['--cc --trace-saif --trace-threads 2 --trace-structs'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_array_saif_threads_2_sc.py b/test_regress/t/t_trace_array_saif_threads_2_sc.py
new file mode 100755
index 000000000..c7f999671
--- /dev/null
+++ b/test_regress/t/t_trace_array_saif_threads_2_sc.py
@@ -0,0 +1,25 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+test.top_filename = "t/t_trace_array.v"
+test.golden_filename = "t/t_trace_array_fst_sc.out"
+
+if not test.have_sc:
+    test.skip("No SystemC installed")
+
+test.compile(verilator_flags2=['--sc --trace-saif --trace-threads 2 --trace-structs'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_ascendingrange_saif.py b/test_regress/t/t_trace_ascendingrange_saif.py
new file mode 100755
index 000000000..10e5f248e
--- /dev/null
+++ b/test_regress/t/t_trace_ascendingrange_saif.py
@@ -0,0 +1,25 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_trace_ascendingrange.v"
+
+# CI environment offers 2 VCPUs, 2 thread setting causes the following warning.
+# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads.
+# Strangely, asking for more threads makes it go away.
+test.compile(verilator_flags2=['--cc --trace-saif --trace-params -Wno-ASCRANGE'],
+             threads=(6 if test.vltmt else 1))
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_ascendingrange_saif_sc.py b/test_regress/t/t_trace_ascendingrange_saif_sc.py
new file mode 100755
index 000000000..7d97731da
--- /dev/null
+++ b/test_regress/t/t_trace_ascendingrange_saif_sc.py
@@ -0,0 +1,28 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_trace_ascendingrange.v"
+
+if not test.have_sc:
+    test.skip("No SystemC installed")
+
+# CI environment offers 2 VCPUs, 2 thread setting causes the following warning.
+# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads.
+# Strangely, asking for more threads makes it go away.
+test.compile(verilator_flags2=['--sc --trace-saif --trace-params -Wno-ASCRANGE'],
+             threads=(6 if test.vltmt else 1))
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_cat_saif.py b/test_regress/t/t_trace_cat_saif.py
new file mode 100755
index 000000000..1ae10e187
--- /dev/null
+++ b/test_regress/t/t_trace_cat_saif.py
@@ -0,0 +1,23 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+
+test.compile(make_top_shell=False,
+             make_main=False,
+             v_flags2=["--trace-saif --exe", test.pli_filename])
+
+test.execute()
+
+test.saif_identical(test.obj_dir + "/simpart_0000.fst", "t/" + test.name + "_0000.out")
+test.saif_identical(test.obj_dir + "/simpart_0100.fst", "t/" + test.name + "_0100.out")
+
+test.passes()
diff --git a/test_regress/t/t_trace_complex_params_saif.py b/test_regress/t/t_trace_complex_params_saif.py
new file mode 100755
index 000000000..f31d18818
--- /dev/null
+++ b/test_regress/t/t_trace_complex_params_saif.py
@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_trace_complex.v"
+
+test.compile(verilator_flags2=['--cc --trace-saif --no-trace-structs --trace-params'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_complex_params_saif_sc.py b/test_regress/t/t_trace_complex_params_saif_sc.py
new file mode 100755
index 000000000..0510d838f
--- /dev/null
+++ b/test_regress/t/t_trace_complex_params_saif_sc.py
@@ -0,0 +1,24 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_trace_complex.v"
+
+if not test.have_sc:
+    test.skip("No SystemC installed")
+
+test.compile(verilator_flags2=['--sc --trace-saif --no-trace-structs --trace-params'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_complex_saif.py b/test_regress/t/t_trace_complex_saif.py
new file mode 100755
index 000000000..c3bc9d4c2
--- /dev/null
+++ b/test_regress/t/t_trace_complex_saif.py
@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_trace_complex.v"
+
+test.compile(verilator_flags2=['--cc --trace-saif'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_complex_saif_sc.py b/test_regress/t/t_trace_complex_saif_sc.py
new file mode 100755
index 000000000..268690520
--- /dev/null
+++ b/test_regress/t/t_trace_complex_saif_sc.py
@@ -0,0 +1,24 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_trace_complex.v"
+
+if not test.have_sc:
+    test.skip("No SystemC installed")
+
+test.compile(verilator_flags2=['--sc --trace-saif'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_complex_saif_threads_1.py b/test_regress/t/t_trace_complex_saif_threads_1.py
new file mode 100755
index 000000000..2d0d7fd70
--- /dev/null
+++ b/test_regress/t/t_trace_complex_saif_threads_1.py
@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_trace_complex.v"
+test.golden_filename = "t/t_trace_complex_fst.out"
+
+test.compile(verilator_flags2=['--cc --trace-saif --trace-threads 1'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_complex_saif_threads_1_sc.py b/test_regress/t/t_trace_complex_saif_threads_1_sc.py
new file mode 100755
index 000000000..ad7343ed0
--- /dev/null
+++ b/test_regress/t/t_trace_complex_saif_threads_1_sc.py
@@ -0,0 +1,25 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_trace_complex.v"
+test.golden_filename = "t/t_trace_complex_fst_sc.out"
+
+if not test.have_sc:
+    test.skip("No SystemC installed")
+
+test.compile(verilator_flags2=['--sc --trace-saif --trace-threads 1'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_complex_saif_threads_2.py b/test_regress/t/t_trace_complex_saif_threads_2.py
new file mode 100755
index 000000000..1eb64d6d8
--- /dev/null
+++ b/test_regress/t/t_trace_complex_saif_threads_2.py
@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_trace_complex.v"
+test.golden_filename = "t/t_trace_complex_fst.out"
+
+test.compile(verilator_flags2=['--cc --trace-saif --trace-threads 2'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_complex_saif_threads_2_sc.py b/test_regress/t/t_trace_complex_saif_threads_2_sc.py
new file mode 100755
index 000000000..5ede01f0a
--- /dev/null
+++ b/test_regress/t/t_trace_complex_saif_threads_2_sc.py
@@ -0,0 +1,25 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_trace_complex.v"
+test.golden_filename = "t/t_trace_complex_fst_sc.out"
+
+if not test.have_sc:
+    test.skip("No SystemC installed")
+
+test.compile(verilator_flags2=['--sc --trace-saif --trace-threads 2'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_complex_structs_saif.py b/test_regress/t/t_trace_complex_structs_saif.py
new file mode 100755
index 000000000..2a2b74369
--- /dev/null
+++ b/test_regress/t/t_trace_complex_structs_saif.py
@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_trace_complex.v"
+
+test.compile(verilator_flags2=['--cc --trace-saif --trace-structs --no-trace-params'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_complex_structs_saif_sc.py b/test_regress/t/t_trace_complex_structs_saif_sc.py
new file mode 100755
index 000000000..c51d5ba80
--- /dev/null
+++ b/test_regress/t/t_trace_complex_structs_saif_sc.py
@@ -0,0 +1,24 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_trace_complex.v"
+
+if not test.have_sc:
+    test.skip("No SystemC installed")
+
+test.compile(verilator_flags2=['--sc --trace-saif --trace-structs --no-trace-params'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_dumpvars_dyn_saif_0.py b/test_regress/t/t_trace_dumpvars_dyn_saif_0.py
new file mode 100755
index 000000000..44835a822
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_dyn_saif_0.py
@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+test.pli_filename = "t/t_trace_dumpvars_dyn.cpp"
+test.top_filename = "t/t_trace_dumpvars_dyn.v"
+
+test.compile(make_main=False, verilator_flags2=["--trace-saif --exe", test.pli_filename])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_dumpvars_dyn_saif_1.py b/test_regress/t/t_trace_dumpvars_dyn_saif_1.py
new file mode 100755
index 000000000..44835a822
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_dyn_saif_1.py
@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+test.pli_filename = "t/t_trace_dumpvars_dyn.cpp"
+test.top_filename = "t/t_trace_dumpvars_dyn.v"
+
+test.compile(make_main=False, verilator_flags2=["--trace-saif --exe", test.pli_filename])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_enum_saif.py b/test_regress/t/t_trace_enum_saif.py
new file mode 100755
index 000000000..7f689fbdb
--- /dev/null
+++ b/test_regress/t/t_trace_enum_saif.py
@@ -0,0 +1,29 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_trace_enum.v"
+
+test.compile(verilator_flags2=['--cc --trace-saif --output-split-ctrace 1'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+# Five $attrbegin expected:
+# - state_t declaration
+# - t.v_enumed
+# - t.sink.state
+# - other_state_t declaration
+# - t.v_other_enumed
+test.file_grep_count(test.golden_filename, r'attrbegin', 5)
+
+test.passes()
diff --git a/test_regress/t/t_trace_event_saif.py b/test_regress/t/t_trace_event_saif.py
new file mode 100755
index 000000000..4544eb517
--- /dev/null
+++ b/test_regress/t/t_trace_event_saif.py
@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+test.top_filename = "t/t_trace_event.v"
+
+test.compile(verilator_flags2=['--trace-saif --binary'])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_no_top_name2_saif.py b/test_regress/t/t_trace_no_top_name2_saif.py
new file mode 100755
index 000000000..5035c849b
--- /dev/null
+++ b/test_regress/t/t_trace_no_top_name2_saif.py
@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+test.pli_filename = "t/t_trace_no_top_name2.cpp"
+test.top_filename = "t/t_trace_no_top_name2.v"
+
+test.compile(make_main=False, verilator_flags2=["--trace-saif --exe", test.pli_filename])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_packed_struct_saif.py b/test_regress/t/t_trace_packed_struct_saif.py
new file mode 100755
index 000000000..60986d596
--- /dev/null
+++ b/test_regress/t/t_trace_packed_struct_saif.py
@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_trace_packed_struct.v"
+
+test.compile(v_flags2=["--trace-saif"])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_packed_struct_saif_sc.py b/test_regress/t/t_trace_packed_struct_saif_sc.py
new file mode 100755
index 000000000..d7c819ef6
--- /dev/null
+++ b/test_regress/t/t_trace_packed_struct_saif_sc.py
@@ -0,0 +1,24 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_trace_packed_struct.v"
+
+if not test.have_sc:
+    test.skip("No SystemC installed")
+
+test.compile(v_flags2=["--sc --trace-saif"])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_param_saif.py b/test_regress/t/t_trace_param_saif.py
new file mode 100755
index 000000000..981062c76
--- /dev/null
+++ b/test_regress/t/t_trace_param_saif.py
@@ -0,0 +1,19 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+test.top_filename = "t/t_trace_param.v"
+
+test.compile(v_flags2=["--trace-saif"])
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_trace_primitive_saif.py b/test_regress/t/t_trace_primitive_saif.py
new file mode 100755
index 000000000..65acc5dd6
--- /dev/null
+++ b/test_regress/t/t_trace_primitive_saif.py
@@ -0,0 +1,19 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_trace_primitive.v"
+
+test.compile(v_flags2=["--trace-saif"])
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_trace_primitive_saif_sc.py b/test_regress/t/t_trace_primitive_saif_sc.py
new file mode 100755
index 000000000..04e646311
--- /dev/null
+++ b/test_regress/t/t_trace_primitive_saif_sc.py
@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_trace_primitive.v"
+
+if not test.have_sc:
+    test.skip("No SystemC installed")
+
+test.compile(v_flags2=["--sc --trace-saif"])
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_trace_saif.py b/test_regress/t/t_trace_saif.py
index 015f47c74..ec0b35e75 100755
--- a/test_regress/t/t_trace_saif.py
+++ b/test_regress/t/t_trace_saif.py
@@ -1,8 +1,8 @@
 #!/usr/bin/env python3
-# DESCRIPTION: Verilator: Verilog Test module
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2025 by Antmicro. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
@@ -15,7 +15,6 @@ test.compile(v_flags2=["--trace-saif"])
 
 test.execute()
 
-#TODO: add checking if two SAIF files are identical
-#test.saif_identical(test.trace_filename, test.golden_filename)
+test.saif_identical(test.trace_filename, test.golden_filename)
 
 test.passes()
diff --git a/test_regress/t/t_trace_saif_cmake.py b/test_regress/t/t_trace_saif_cmake.py
new file mode 100755
index 000000000..70ab07067
--- /dev/null
+++ b/test_regress/t/t_trace_saif_cmake.py
@@ -0,0 +1,20 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+
+test.compile(v_flags2=["--trace-saif"], verilator_make_gmake=False, verilator_make_cmake=1)
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_saif_sc.py b/test_regress/t/t_trace_saif_sc.py
new file mode 100755
index 000000000..d8ff6413a
--- /dev/null
+++ b/test_regress/t/t_trace_saif_sc.py
@@ -0,0 +1,23 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+
+if not test.have_sc:
+    test.skip("No SystemC installed")
+
+test.compile(verilator_flags2=["--trace-saif --sc"])
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_saif_sc_cmake.py b/test_regress/t/t_trace_saif_sc_cmake.py
new file mode 100755
index 000000000..50d89cb33
--- /dev/null
+++ b/test_regress/t/t_trace_saif_sc_cmake.py
@@ -0,0 +1,25 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+
+if not test.have_sc:
+    test.skip("No SystemC installed")
+
+test.compile(verilator_flags2=["--trace-saif --sc"],
+             verilator_make_gmake=False,
+             verilator_make_cmake=1)
+
+test.execute()
+
+test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_string_saif.py b/test_regress/t/t_trace_string_saif.py
new file mode 100755
index 000000000..cf926f0d2
--- /dev/null
+++ b/test_regress/t/t_trace_string_saif.py
@@ -0,0 +1,19 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_trace_string.v"
+
+test.compile(verilator_flags2=['--cc --trace'])
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_trace_string_saif_sc.py b/test_regress/t/t_trace_string_saif_sc.py
new file mode 100755
index 000000000..dc56e4069
--- /dev/null
+++ b/test_regress/t/t_trace_string_saif_sc.py
@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_trace_string.v"
+
+if not test.have_sc:
+    test.skip("No SystemC installed")
+
+test.compile(verilator_flags2=['--sc --trace'])
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_trace_two_dumpsaif_cc.py b/test_regress/t/t_trace_two_dumpsaif_cc.py
new file mode 100755
index 000000000..68017d6c0
--- /dev/null
+++ b/test_regress/t/t_trace_two_dumpsaif_cc.py
@@ -0,0 +1,38 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+# Test tracing with two models instanced
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+test.top_filename = "t_trace_two_a.v"
+
+test.compile(make_main=False,
+             verilator_make_gmake=False,
+             top_filename='t_trace_two_b.v',
+             vm_prefix='Vt_trace_two_b',
+             verilator_flags2=['--trace-saif --trace-threads 1 -DTEST_FST'])
+
+test.run(logfile=test.obj_dir + "/make_first_ALL.log",
+         cmd=["make", "-C", test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"])
+
+test.compile(make_main=False,
+             top_filename='t_trace_two_a.v',
+             verilator_flags2=[
+                 '-exe', '--trace-saif --trace-threads 1', '-DTEST_FST',
+                 test.t_dir + "/t_trace_two_cc.cpp"
+             ],
+             v_flags2=['+define+TEST_DUMP'])
+
+test.execute()
+
+if test.vlt_all:
+    test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_two_hdrsaif_cc.py b/test_regress/t/t_trace_two_hdrsaif_cc.py
new file mode 100755
index 000000000..d2ea9a876
--- /dev/null
+++ b/test_regress/t/t_trace_two_hdrsaif_cc.py
@@ -0,0 +1,39 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+# Test tracing with two models instanced
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+test.top_filename = "t_trace_two_a.v"
+
+test.compile(make_main=False,
+             verilator_make_gmake=False,
+             top_filename='t_trace_two_b.v',
+             vm_prefix='Vt_trace_two_b',
+             verilator_flags2=['--trace-saif --trace-threads 1'])
+
+test.run(
+    logfile=test.obj_dir + "/make_first_ALL.log",
+    cmd=["make", "-C", "" + test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"])
+
+test.compile(make_main=False,
+             top_filename='t_trace_two_a.v',
+             make_flags=['CPPFLAGS_ADD="-DTEST_HDR_TRACE=1 -DTEST_FST=1"'],
+             verilator_flags2=[
+                 '-exe', '--trace-saif --trace-threads 1', '-DTEST_FST',
+                 test.t_dir + "/t_trace_two_cc.cpp"
+             ])
+
+test.execute()
+
+if test.vlt_all:
+    test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_trace_two_portsaif_cc.py b/test_regress/t/t_trace_two_portsaif_cc.py
new file mode 100755
index 000000000..13645c013
--- /dev/null
+++ b/test_regress/t/t_trace_two_portsaif_cc.py
@@ -0,0 +1,39 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+# Test tracing with two models instanced
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+test.top_filename = "t_trace_two_a.v"
+
+test.compile(make_main=False,
+             verilator_make_gmake=False,
+             top_filename='t_trace_two_b.v',
+             vm_prefix='Vt_trace_two_b',
+             verilator_flags2=['--trace-saif --trace-threads 1'])
+
+test.run(
+    logfile=test.obj_dir + "/make_first_ALL.log",
+    cmd=["make", "-C", "" + test.obj_dir, "-f", "Vt_trace_two_b.mk", "Vt_trace_two_b__ALL.cpp"])
+
+test.compile(make_main=False,
+             top_filename='t_trace_two_a.v',
+             verilator_flags2=[
+                 '-exe', '--trace-saif --trace-threads 1', '-DTEST_FST',
+                 test.t_dir + "/t_trace_two_cc.cpp"
+             ],
+             v_flags2=['+define+TEST_DUMPPORTS'])
+
+test.execute()
+
+if test.vlt_all:
+    test.saif_identical(test.trace_filename, test.golden_filename)
+
+test.passes()