From 7628a540af0db3adf7bddf5e8e27fe6b1ca03674 Mon Sep 17 00:00:00 2001
From: Pawel Klopotek <pklopotek@internships.antmicro.com>
Date: Wed, 19 Aug 2026 08:29:29 +0200
Subject: [PATCH] Fix invalid C++ on cast (#8113)

Signed-off-by: Pawel Klopotek <pklopotek@internships.antmicro.com>
---
 src/V3Task.cpp                       |  5 ++++
 test_regress/t/t_func_real_output.py | 18 ++++++++++++++
 test_regress/t/t_func_real_output.v  | 37 ++++++++++++++++++++++++++++
 3 files changed, 60 insertions(+)
 create mode 100755 test_regress/t/t_func_real_output.py
 create mode 100644 test_regress/t/t_func_real_output.v

diff --git a/src/V3Task.cpp b/src/V3Task.cpp
index 028f53e1b..19329eb4c 100644
--- a/src/V3Task.cpp
+++ b/src/V3Task.cpp
@@ -534,6 +534,11 @@ class TaskVisitor final : public VNVisitor {
             }
             postRhsp->dtypeFrom(outPinp);
         }
+        if (VN_IS(outPinp, IToRD) || VN_IS(outPinp, ISToRD)) {
+            outPinp = VN_AS(outPinp, NodeUniop)->lhsp();
+            postRhsp = new AstRToIRoundS{pinp->fileline(), postRhsp};
+            postRhsp->dtypeFrom(outPinp);
+        }
         // Put output assignment AFTER function call
         AstNodeExpr* const outPinClonep
             = pureCheck ? outPinp->cloneTreePure(true) : outPinp->cloneTree(true);
diff --git a/test_regress/t/t_func_real_output.py b/test_regress/t/t_func_real_output.py
new file mode 100755
index 000000000..8a938befd
--- /dev/null
+++ b/test_regress/t/t_func_real_output.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_func_real_output.v b/test_regress/t/t_func_real_output.v
new file mode 100644
index 000000000..41f05a3a0
--- /dev/null
+++ b/test_regress/t/t_func_real_output.v
@@ -0,0 +1,37 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Antmicro
+// SPDX-License-Identifier: CC0-1.0
+
+// verilog_format: off
+`define stop $stop
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
+
+module t;
+  bit unsigned [3:0] dst_u2s;
+  bit signed [3:0] dst_s2s;
+  bit unsigned [11:0] dst_u2l;
+  bit signed [11:0] dst_s2l;
+
+  real src_r;
+
+  task cp_r(output real dst, input real src);
+    dst = src;
+  endtask
+
+  initial begin
+    src_r = -7.0;
+    cp_r(dst_u2s, src_r);
+    `checkh(dst_u2s, 4'h9);
+    cp_r(dst_s2s, src_r);
+    `checkh(dst_s2s, -7);
+    cp_r(dst_u2l, src_r);
+    `checkh(dst_u2l, 12'hff9);
+    cp_r(dst_s2l, src_r);
+    `checkh(dst_s2l, -7);
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule