From 74d7c55f1b8d2c95746ccedd2e78d15934f76c1c Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 3 Oct 2006 13:02:21 +0000 Subject: [PATCH] Fix dotted variables in always sensitivity lists. git-svn-id: file://localhost/svn/verilator/trunk/verilator@803 77ca24e4-aefa-0310-84f0-b9a241c72d87 --- Changes | 2 + src/V3AstNodes.h | 4 +- src/V3Case.cpp | 2 +- src/V3Const.cpp | 2 +- src/verilog.y | 6 +- test_regress/t/t_case_nest.pl | 18 ++++++ test_regress/t/t_case_nest.v | 109 ++++++++++++++++++++++++++++++++++ test_regress/t/t_var_dotted.v | 3 +- 8 files changed, 137 insertions(+), 9 deletions(-) create mode 100755 test_regress/t/t_case_nest.pl create mode 100644 test_regress/t/t_case_nest.v diff --git a/Changes b/Changes index 0d7218c5e..a70b0a54e 100644 --- a/Changes +++ b/Changes @@ -18,6 +18,8 @@ indicates the contributor was also the author of the fix; Thanks! **** Fix coredump when dotted cross-ref inside task call. [Eugene Weber] +**** Fix dotted variables in always sensitivity lists. [Allan Cochrane] + * Verilator 3.610 09/20/2006 *** Verilator now works under DJGPP (Pentium GCC). [John Stroebel] diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h index 5df207817..9df92c688 100644 --- a/src/V3AstNodes.h +++ b/src/V3AstNodes.h @@ -809,7 +809,7 @@ public: class Initial {}; // for creator type-overload selection class Settle {}; // for creator type-overload selection class Never {}; // for creator type-overload selection - AstSenItem(FileLine* fl, AstEdgeType edgeType, AstVarRef* varrefp) + AstSenItem(FileLine* fl, AstEdgeType edgeType, AstNodeVarRef* varrefp) : AstNode(fl) { m_edgeType = edgeType; setOp1p(varrefp); @@ -842,7 +842,7 @@ public: AstEdgeType edgeType() const { return m_edgeType; } // * = Posedge/negedge void edgeType(AstEdgeType type) { m_edgeType=type; editCountInc(); }// * = Posedge/negedge AstNode* sensp() const { return op1p(); } // op1 = Signal sensitized - AstVarRef* varrefp() const { return op1p()->castVarRef(); } // op1 = Signal sensitized + AstNodeVarRef* varrefp() const { return op1p()->castNodeVarRef(); } // op1 = Signal sensitized // bool isClocked() const { return edgeType().clockedStmt(); } bool isCombo() const { return edgeType()==AstEdgeType::COMBO; } diff --git a/src/V3Case.cpp b/src/V3Case.cpp index 5663eae07..927f437ae 100644 --- a/src/V3Case.cpp +++ b/src/V3Case.cpp @@ -376,7 +376,7 @@ private: public: // CONSTUCTORS - CaseVisitor(AstNode* nodep) { + CaseVisitor(AstNetlist* nodep) { m_caseNoOverlapsAllCovered = false; nodep->accept(*this); } diff --git a/src/V3Const.cpp b/src/V3Const.cpp index 7c8af8ba5..8bfb59aff 100644 --- a/src/V3Const.cpp +++ b/src/V3Const.cpp @@ -815,7 +815,7 @@ private: } UINFO(8,"senItem(NOT...) "<edgeType( nodep->edgeType().invert() ); - AstVarRef* senvarp = lastSensp->unlinkFrBack()->castVarRef(); + AstNodeVarRef* senvarp = lastSensp->unlinkFrBack()->castNodeVarRef(); if (!senvarp) sensp->v3fatalSrc("Non-varref sensitivity variable"); sensp->replaceWith(senvarp); sensp->deleteTree(); sensp=NULL; diff --git a/src/verilog.y b/src/verilog.y index e2f6e8de3..b19c6463f 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -627,11 +627,11 @@ senList: senitem { $$ = $1; } ; senitem: senitemEdge { $$ = $1; } - | idVarRef ignoreRangeE { $$ = new AstSenItem(CRELINE(),AstEdgeType::ANYEDGE,$1); } + | idVarXRef ignoreRangeE { $$ = new AstSenItem(CRELINE(),AstEdgeType::ANYEDGE,$1); } ; -senitemEdge: yPOSEDGE idVarRef ignoreRangeE { $$ = new AstSenItem($1,AstEdgeType::POSEDGE,$2); } - | yNEGEDGE idVarRef ignoreRangeE { $$ = new AstSenItem($1,AstEdgeType::NEGEDGE,$2); } +senitemEdge: yPOSEDGE idVarXRef ignoreRangeE { $$ = new AstSenItem($1,AstEdgeType::POSEDGE,$2); } + | yNEGEDGE idVarXRef ignoreRangeE { $$ = new AstSenItem($1,AstEdgeType::NEGEDGE,$2); } ; ignoreRangeE: /* empty */ { $$ = NULL; } /* ignored */ diff --git a/test_regress/t/t_case_nest.pl b/test_regress/t/t_case_nest.pl new file mode 100755 index 000000000..7bfdbe852 --- /dev/null +++ b/test_regress/t/t_case_nest.pl @@ -0,0 +1,18 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } +# $Id$ +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# General Public License or the Perl Artistic License. + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_case_nest.v b/test_regress/t/t_case_nest.v new file mode 100644 index 000000000..f224ebe5b --- /dev/null +++ b/test_regress/t/t_case_nest.v @@ -0,0 +1,109 @@ +// $Id$ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2006 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + integer cyc; initial cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + reg out1; + sub sub (.in(crc[23:0]), .out1(out1)); + + always @ (posedge clk) begin + $write("[%0t] cyc==%0d crc=%x sum=%x out=%x\n",$time, cyc, crc, sum, out1); + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {63'h0,out1}; + if (cyc==1) begin + // Setup + crc <= 64'h00000000_00000097; + sum <= 64'h0; + end + else if (cyc==90) begin + if (sum != 64'h2e5cb972eb02b8a0) $stop; + end + else if (cyc==91) begin + end + else if (cyc==92) begin + end + else if (cyc==93) begin + end + else if (cyc==94) begin + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module sub (/*AUTOARG*/ + // Outputs + out1, + // Inputs + in + ); + + input [23:0] in; + output reg [0:0] out1; + + parameter [1023:0] RANDOM = 1024'b101011010100011011100111101001000000101000001111111111100110000110011011010110011101000100110000110101111101000111100100010111001001110001010101000111000100010000010011100001100011110110110000101100011111000110111110010110011000011111111010101110001101010010001111110111100000110111101100110101110001110110000010000110101110111001111001100001101110001011100111001001110101001010000110101010100101111000010000010110100101110100110000110110101000100011101111100011000110011001100010010011001101100100101110010100110101001110011111110010000111001111000010001101100101101110111110001000010110010011100101001011111110011010110111110000110010011110001110110011010011010110011011111001110100010110100011100001011000101111000010011111010111001110110011101110101011111001100011000101000001000100111110010100111011101010101011001101000100000101111110010011010011010001111010001110000110010100011110110011001010000011001010010110111101010010011111111010001000101100010100100010011001100110000111111000001000000001001111101110000100101; + + always @* begin + casez (in[17:16]) + 2'b00: casez (in[2:0]) + 3'h0: out1[0] = in[0]^RANDOM[0]; + 3'h1: out1[0] = in[0]^RANDOM[1]; + 3'h2: out1[0] = in[0]^RANDOM[2]; + 3'h3: out1[0] = in[0]^RANDOM[3]; + 3'h4: out1[0] = in[0]^RANDOM[4]; + 3'h5: out1[0] = in[0]^RANDOM[5]; + 3'h6: out1[0] = in[0]^RANDOM[6]; + 3'h7: out1[0] = in[0]^RANDOM[7]; + endcase + 2'b01: casez (in[2:0]) + 3'h0: out1[0] = RANDOM[10]; + 3'h1: out1[0] = RANDOM[11]; + 3'h2: out1[0] = RANDOM[12]; + 3'h3: out1[0] = RANDOM[13]; + 3'h4: out1[0] = RANDOM[14]; + 3'h5: out1[0] = RANDOM[15]; + 3'h6: out1[0] = RANDOM[16]; + 3'h7: out1[0] = RANDOM[17]; + endcase + 2'b1?: casez (in[4]) + 1'b1: casez (in[2:0]) + 3'h0: out1[0] = RANDOM[20]; + 3'h1: out1[0] = RANDOM[21]; + 3'h2: out1[0] = RANDOM[22]; + 3'h3: out1[0] = RANDOM[23]; + 3'h4: out1[0] = RANDOM[24]; + 3'h5: out1[0] = RANDOM[25]; + 3'h6: out1[0] = RANDOM[26]; + 3'h7: out1[0] = RANDOM[27]; + endcase + 1'b0: casez (in[2:0]) + 3'h0: out1[0] = RANDOM[30]; + 3'h1: out1[0] = RANDOM[31]; + 3'h2: out1[0] = RANDOM[32]; + 3'h3: out1[0] = RANDOM[33]; + 3'h4: out1[0] = RANDOM[34]; + 3'h5: out1[0] = RANDOM[35]; + 3'h6: out1[0] = RANDOM[36]; + 3'h7: out1[0] = RANDOM[37]; + endcase + endcase + endcase + end + +endmodule diff --git a/test_regress/t/t_var_dotted.v b/test_regress/t/t_var_dotted.v index 6213299d4..f08fb93eb 100644 --- a/test_regress/t/t_var_dotted.v +++ b/test_regress/t/t_var_dotted.v @@ -141,10 +141,9 @@ module mc (output reg [31:0] out); end // Can we look from the top module name down? - wire reach_up_clk = t.clk; wire [31:0] reach_up_cyc = t.cyc; - always @ (posedge reach_up_clk) begin + always @ (posedge t.clk) begin //$write("[%0t] %m: Got reachup, cyc=%0d\n", $time, reach_up_cyc); if (reach_up_cyc==2) begin if (global_cell.global != 32'hf00d) $stop;