From 74420550e6ab5e88924485800d09c5a84344efd0 Mon Sep 17 00:00:00 2001 From: Mike Popoloski Date: Thu, 14 Sep 2017 21:24:13 -0400 Subject: [PATCH] Fix .name connections on interfaces, bug1214. Signed-off-by: Wilson Snyder --- Changes | 2 ++ src/verilog.y | 8 ++++---- test_regress/t/t_interface_star.v | 2 ++ 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/Changes b/Changes index dbdc75759..e8a9db81c 100644 --- a/Changes +++ b/Changes @@ -20,6 +20,8 @@ The contributors that suggested a given feature are shown in []. Thanks! **** Fix non-colon array of interface modports, bug1212. [Mike Popoloski] +**** Fix .name connections on interfaces, bug1214. [Mike Popoloski] + * Verilator 3.910 2017-09-07 diff --git a/src/verilog.y b/src/verilog.y index b4bdb2f02..b339796f2 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -2102,8 +2102,8 @@ cellparamItemE: // IEEE: named_parameter_assignment + empty // Note empty can match either () or (,); V3LinkCells cleans up () /* empty: ',,' is legal */ { $$ = new AstPin(CRELINE(),PINNUMINC(),"",NULL); } | yP_DOTSTAR { $$ = new AstPin($1,PINNUMINC(),".*",NULL); } - | '.' idSVKwd { $$ = new AstPin($1,PINNUMINC(),*$2,new AstVarRef($1,*$2,false)); $$->svImplicit(true);} - | '.' idAny { $$ = new AstPin($1,PINNUMINC(),*$2,new AstVarRef($1,*$2,false)); $$->svImplicit(true);} + | '.' idSVKwd { $$ = new AstPin($1,PINNUMINC(),*$2,new AstParseRef($1,AstParseRefExp::PX_TEXT,*$2,NULL,NULL)); $$->svImplicit(true);} + | '.' idAny { $$ = new AstPin($1,PINNUMINC(),*$2,new AstParseRef($1,AstParseRefExp::PX_TEXT,*$2,NULL,NULL)); $$->svImplicit(true);} | '.' idAny '(' ')' { $$ = new AstPin($1,PINNUMINC(),*$2,NULL); } // // mintypmax is expanded here, as it might be a UDP or gate primitive | '.' idAny '(' expr ')' { $$ = new AstPin($1,PINNUMINC(),*$2,$4); } @@ -2123,8 +2123,8 @@ cellpinItemE: // IEEE: named_port_connection + empty // Note empty can match either () or (,); V3LinkCells cleans up () /* empty: ',,' is legal */ { $$ = new AstPin(CRELINE(),PINNUMINC(),"",NULL); } | yP_DOTSTAR { $$ = new AstPin($1,PINNUMINC(),".*",NULL); } - | '.' idSVKwd { $$ = new AstPin($1,PINNUMINC(),*$2,new AstVarRef($1,*$2,false)); $$->svImplicit(true);} - | '.' idAny { $$ = new AstPin($1,PINNUMINC(),*$2,new AstVarRef($1,*$2,false)); $$->svImplicit(true);} + | '.' idSVKwd { $$ = new AstPin($1,PINNUMINC(),*$2,new AstParseRef($1,AstParseRefExp::PX_TEXT,*$2,NULL,NULL)); $$->svImplicit(true);} + | '.' idAny { $$ = new AstPin($1,PINNUMINC(),*$2,new AstParseRef($1,AstParseRefExp::PX_TEXT,*$2,NULL,NULL)); $$->svImplicit(true);} | '.' idAny '(' ')' { $$ = new AstPin($1,PINNUMINC(),*$2,NULL); } // // mintypmax is expanded here, as it might be a UDP or gate primitive | '.' idAny '(' expr ')' { $$ = new AstPin($1,PINNUMINC(),*$2,$4); } diff --git a/test_regress/t/t_interface_star.v b/test_regress/t/t_interface_star.v index e51c06a01..e3e4b3b14 100644 --- a/test_regress/t/t_interface_star.v +++ b/test_regress/t/t_interface_star.v @@ -15,6 +15,8 @@ module t (/*AUTOARG*/ counter_ansi c1 (.clk, .*); + counter_ansi c2 (.clk, .c_data); + always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==20) begin