From 738d7fff53ab697b19d8a6a5493d6f5f2125b8e5 Mon Sep 17 00:00:00 2001 From: Mateusz Gancarz Date: Tue, 4 Mar 2025 12:44:57 +0100 Subject: [PATCH] [#73912] add support for CMake --- src/V3EmitCMake.cpp | 3 + src/V3EmitMk.cpp | 2 +- test_regress/t/t_trace_saif_cmake.out | 90 ++++++++++++++++++++++++ test_regress/t/t_trace_saif_cmake.py | 22 ++++++ test_regress/t/t_trace_saif_cmake.v | 99 +++++++++++++++++++++++++++ verilator-config.cmake.in | 18 +++++ 6 files changed, 233 insertions(+), 1 deletion(-) create mode 100644 test_regress/t/t_trace_saif_cmake.out create mode 100755 test_regress/t/t_trace_saif_cmake.py create mode 100644 test_regress/t/t_trace_saif_cmake.v diff --git a/src/V3EmitCMake.cpp b/src/V3EmitCMake.cpp index 6744098e8..182406281 100644 --- a/src/V3EmitCMake.cpp +++ b/src/V3EmitCMake.cpp @@ -116,6 +116,9 @@ class CMakeEmitter final { *of << "# FST Tracing output mode? 0/1 (from --trace-fst)\n"; cmake_set_raw(*of, name + "_TRACE_FST", (v3Global.opt.trace() && v3Global.opt.traceFormat().fst()) ? "1" : "0"); + *of << "# SAIF Tracing output mode? 0/1 (from --trace-saif)\n"; + cmake_set_raw(*of, name + "_TRACE_SAIF", + (v3Global.opt.trace() && v3Global.opt.traceFormat().saif()) ? "1" : "0"); *of << "\n### Sources...\n"; std::vector classes_fast; diff --git a/src/V3EmitMk.cpp b/src/V3EmitMk.cpp index 3f44a9069..e5ae98483 100644 --- a/src/V3EmitMk.cpp +++ b/src/V3EmitMk.cpp @@ -551,7 +551,7 @@ public: of.puts("VM_PARALLEL_BUILDS = "); of.puts(v3Global.useParallelBuild() ? "1" : "0"); of.puts("\n"); - of.puts("# Tracing output mode? 0/1 (from --trace/--trace-fst)\n"); + of.puts("# Tracing output mode? 0/1 (from --trace/--trace-fst/--trace-saif)\n"); of.puts("VM_TRACE = "); of.puts(v3Global.opt.trace() ? "1" : "0"); of.puts("\n"); diff --git a/test_regress/t/t_trace_saif_cmake.out b/test_regress/t/t_trace_saif_cmake.out new file mode 100644 index 000000000..cd7b980b6 --- /dev/null +++ b/test_regress/t/t_trace_saif_cmake.out @@ -0,0 +1,90 @@ +(SAIFILE +(SAIFVERSION "2.0") +(DIRECTION "backward") +(PROGRAM_NAME "Verilator") +(DIVIDER / ) +(TIMESCALE 1ps) +(DURATION 1000) + (INSTANCE top + (NET + (clk (T0 505) (T1 495) (TZ 0) (TX 0) (TB 0) (TC 199)) + (state\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46)) + (state\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) + (state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) + (state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44)) + (state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) + ) + (INSTANCE t + (NET + (clk (T0 505) (T1 495) (TZ 0) (TX 0) (TB 0) (TC 199)) + (cyc\[0\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 100)) + (cyc\[1\] (T0 500) (T1 500) (TZ 0) (TX 0) (TB 0) (TC 50)) + (cyc\[2\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 25)) + (cyc\[3\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 12)) + (cyc\[4\] (T0 520) (T1 480) (TZ 0) (TX 0) (TB 0) (TC 6)) + (cyc\[5\] (T0 640) (T1 360) (TZ 0) (TX 0) (TB 0) (TC 3)) + (cyc\[6\] (T0 640) (T1 360) (TZ 0) (TX 0) (TB 0) (TC 1)) + (rstn (T0 110) (T1 890) (TZ 0) (TX 0) (TB 0) (TC 1)) + (state\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46)) + (state\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) + (state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) + (state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44)) + (state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) + (fst_parameter\[0\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) + (fst_parameter\[1\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) + (fst_parameter\[3\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) + (fst_parameter\[4\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) + (fst_parameter\[5\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) + (fst_parameter\[6\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) + (fst_lparam\[3\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) + (fst_lparam\[6\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) + (fst_lparam\[7\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) + (fst_lparam\[8\] (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) + (fst_supply1 (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) + (fst_tri1 (T0 0) (T1 1000) (TZ 0) (TX 0) (TB 0) (TC 1)) + ) + (INSTANCE test + (NET + (clk (T0 505) (T1 495) (TZ 0) (TX 0) (TB 0) (TC 199)) + (rstn (T0 110) (T1 890) (TZ 0) (TX 0) (TB 0) (TC 1)) + (state\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46)) + (state\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) + (state\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) + (state\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44)) + (state\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) + (state_w\[0\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) + (state_w\[1\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) + (state_w\[2\] (T0 430) (T1 570) (TZ 0) (TX 0) (TB 0) (TC 46)) + (state_w\[3\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 47)) + (state_w\[4\] (T0 420) (T1 580) (TZ 0) (TX 0) (TB 0) (TC 48)) + (state_array[0]\[0\] (T0 410) (T1 590) (TZ 0) (TX 0) (TB 0) (TC 46)) + (state_array[0]\[1\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) + (state_array[0]\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) + (state_array[0]\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 44)) + (state_array[0]\[4\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) + (state_array[1]\[0\] (T0 420) (T1 580) (TZ 0) (TX 0) (TB 0) (TC 47)) + (state_array[1]\[1\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) + (state_array[1]\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) + (state_array[1]\[3\] (T0 540) (T1 460) (TZ 0) (TX 0) (TB 0) (TC 45)) + (state_array[1]\[4\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) + (state_array[2]\[0\] (T0 420) (T1 580) (TZ 0) (TX 0) (TB 0) (TC 48)) + (state_array[2]\[1\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) + (state_array[2]\[2\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) + (state_array[2]\[3\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 46)) + (state_array[2]\[4\] (T0 530) (T1 470) (TZ 0) (TX 0) (TB 0) (TC 47)) + ) + (INSTANCE unnamedblk1 + (NET + (i\[0\] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1)) + (i\[1\] (T0 10) (T1 990) (TZ 0) (TX 0) (TB 0) (TC 1)) + ) + ) + (INSTANCE unnamedblk2 + (NET + (i\[1\] (T0 120) (T1 880) (TZ 0) (TX 0) (TB 0) (TC 1)) + ) + ) + ) + ) + ) +) diff --git a/test_regress/t/t_trace_saif_cmake.py b/test_regress/t/t_trace_saif_cmake.py new file mode 100755 index 000000000..11d689389 --- /dev/null +++ b/test_regress/t/t_trace_saif_cmake.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.top_filename = "t/t_trace_fst_cmake.v" + +test.compile(v_flags2=["--trace-saif"], verilator_make_gmake=False, verilator_make_cmake=True) + +test.execute() + +test.saif_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_saif_cmake.v b/test_regress/t/t_trace_saif_cmake.v new file mode 100644 index 000000000..288ddadfc --- /dev/null +++ b/test_regress/t/t_trace_saif_cmake.v @@ -0,0 +1,99 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// Author: Yu-Sheng Lin johnjohnlys@media.ee.ntu.edu.tw +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Outputs + state, + // Inputs + clk + ); + + input clk; + + int cyc; + reg rstn; + output [4:0] state; + + parameter real fst_gparam_real = 1.23; + localparam real fst_lparam_real = 4.56; + real fst_real = 1.23; + integer fst_integer; + bit fst_bit; + logic fst_logic; + int fst_int; + shortint fst_shortint; + longint fst_longint; + byte fst_byte; + + parameter fst_parameter = 123; + localparam fst_lparam = 456; + supply0 fst_supply0; + supply1 fst_supply1; + tri0 fst_tri0; + tri1 fst_tri1; + tri fst_tri; + wire fst_wire; + + Test test (/*AUTOINST*/ + // Outputs + .state (state[4:0]), + // Inputs + .clk (clk), + .rstn (rstn)); + + // Test loop + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==0) begin + // Setup + rstn <= ~'1; + end + else if (cyc<10) begin + rstn <= ~'1; + end + else if (cyc<90) begin + rstn <= ~'0; + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + + +module Test ( + input clk, + input rstn, + output logic [4:0] state + ); + + logic [4:0] state_w; + logic [4:0] state_array [3]; + assign state = state_array[0]; + + always_comb begin + state_w[4] = state_array[2][0]; + state_w[3] = state_array[2][4]; + state_w[2] = state_array[2][3] ^ state_array[2][0]; + state_w[1] = state_array[2][2]; + state_w[0] = state_array[2][1]; + end + + always_ff @(posedge clk or negedge rstn) begin + if (!rstn) begin + for (int i = 0; i < 3; i++) + state_array[i] <= 'b1; + end + else begin + for (int i = 0; i < 2; i++) + state_array[i] <= state_array[i+1]; + state_array[2] <= state_w; + end + end + +endmodule diff --git a/verilator-config.cmake.in b/verilator-config.cmake.in index 33dcc4406..6b5f766ee 100644 --- a/verilator-config.cmake.in +++ b/verilator-config.cmake.in @@ -142,6 +142,13 @@ define_property( FULL_DOCS "Verilator FST trace enabled" ) +define_property( + TARGET + PROPERTY VERILATOR_TRACE_SAIF + BRIEF_DOCS "Verilator SAIF trace enabled" + FULL_DOCS "Verilator SAIF trace enabled" +) + define_property( TARGET PROPERTY VERILATOR_SYSTEMC @@ -206,6 +213,10 @@ function(verilate TARGET) list(APPEND VERILATOR_ARGS --trace-fst) endif() + if(VERILATE_TRACE_SAIF) + list(APPEND VERILATOR_ARGS --trace-saif) + endif() + if(VERILATE_SYSTEMC) list(APPEND VERILATOR_ARGS --sc) else() @@ -377,6 +388,12 @@ function(verilate TARGET) set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE_FST ON) endif() + if(${VERILATE_PREFIX}_TRACE_SAIF) + # If any verilate() call specifies TRACE_SAIF, define VM_TRACE_SAIF in the final build + set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE ON) + set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE_SAIF ON) + endif() + if(${VERILATE_PREFIX}_SC) # If any verilate() call specifies SYSTEMC, define VM_SC in the final build set_property(TARGET ${TARGET} PROPERTY VERILATOR_SYSTEMC ON) @@ -455,6 +472,7 @@ function(verilate TARGET) VM_TRACE=$> VM_TRACE_VCD=$> VM_TRACE_FST=$> + VM_TRACE_SAIF=$> ) target_link_libraries(${TARGET} PUBLIC ${${VERILATE_PREFIX}_USER_LDLIBS})