From 72a3c756ad7d7268a7f120da795e20313352f4c6 Mon Sep 17 00:00:00 2001 From: Larry Doolittle Date: Sun, 27 Feb 2022 02:01:44 -0800 Subject: [PATCH] Commentary: Minor spelling fixes in docs/guide/*.rst (#3327) --- docs/CONTRIBUTORS | 1 + docs/guide/deprecations.rst | 2 +- docs/guide/exe_verilator.rst | 4 ++-- docs/guide/exe_verilator_coverage.rst | 2 +- docs/guide/extensions.rst | 2 +- docs/guide/faq.rst | 4 ++-- docs/guide/languages.rst | 2 +- docs/guide/warnings.rst | 6 +++--- 8 files changed, 12 insertions(+), 11 deletions(-) diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS index d98c2c325..ff2ca8d6d 100644 --- a/docs/CONTRIBUTORS +++ b/docs/CONTRIBUTORS @@ -57,6 +57,7 @@ Keith Colbert Kevin Kiningham Krzysztof Bieganski Kuba Ober +Larry Doolittle Ludwig Rogiers Lukasz Dalek Maarten De Braekeleer diff --git a/docs/guide/deprecations.rst b/docs/guide/deprecations.rst index 71db142ee..87107cca1 100644 --- a/docs/guide/deprecations.rst +++ b/docs/guide/deprecations.rst @@ -18,4 +18,4 @@ Verilated_heavy.h Option `--cdc` The experimental `--cdc` option is believed to be generally unused and is - planned for removeal no sooner than January 2023. + planned for removal no sooner than January 2023. diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst index 09b13c2a0..55a356ee4 100644 --- a/docs/guide/exe_verilator.rst +++ b/docs/guide/exe_verilator.rst @@ -884,7 +884,7 @@ Summary: Using DPI imports/exports is allowed and generally relatively safe in terms of information disclosed, which is limited to the DPI function - prototyptes. Use of the VPI is not recommended as many design details + prototypes. Use of the VPI is not recommended as many design details may be exposed, and an INSECURE warning will be issued. .. option:: --protect-lib @@ -1514,7 +1514,7 @@ The grammar of configuration commands is as follows: .. option:: no_clocker -module "" [-function ""] -var "" Indicates that the signal is used as clock or not. This information is - used by Verilator to mark the signal and any derrived signals as + used by Verilator to mark the signal and any derived signals as clocker. See :vlopt:`--clk`. Same as :option:`/*verilator&32;clocker*/` metacomment. diff --git a/docs/guide/exe_verilator_coverage.rst b/docs/guide/exe_verilator_coverage.rst index 878969b08..2bd93e7c0 100644 --- a/docs/guide/exe_verilator_coverage.rst +++ b/docs/guide/exe_verilator_coverage.rst @@ -67,7 +67,7 @@ which have low coverage are written to the output directory. Specifies if the coverage point does not include the count number of coverage hits, then the coverage point will be considered above the -threashold, and the coverage report will put a "%" to indicate the coverage +threshold, and the coverage report will put a "%" to indicate the coverage is not sufficient. Defaults to 10. .. option:: --help diff --git a/docs/guide/extensions.rst b/docs/guide/extensions.rst index 65e8f829a..19951334b 100644 --- a/docs/guide/extensions.rst +++ b/docs/guide/extensions.rst @@ -185,7 +185,7 @@ or "`ifdef`"'s may break other tools. .. option:: /*verilator&32;no_clocker*/ Specifies that the signal is used as clock or not. This information is - used by Verilator to mark the signal and any derrived signals as + used by Verilator to mark the signal and any derived signals as clocker. See :vlopt:`--clk`. Same as :option:`clocker` and :option:`no_clocker` in configuration diff --git a/docs/guide/faq.rst b/docs/guide/faq.rst index 263e9d4a0..de8882a2b 100644 --- a/docs/guide/faq.rst +++ b/docs/guide/faq.rst @@ -37,8 +37,8 @@ Does Verilator run under Windows? Yes, ideally run Ubuntu under Windows Subsystem for Linux (WSL2). Alternatively use Cygwin, though this tends to be slower and is not -regurally tested. Verilated output also compiles under Microsoft Visual -C++, but this is also not regurally tested. +regularly tested. Verilated output also compiles under Microsoft Visual +C++, but this is also not regularly tested. Can you provide binaries? diff --git a/docs/guide/languages.rst b/docs/guide/languages.rst index 108e58212..0f6d21589 100644 --- a/docs/guide/languages.rst +++ b/docs/guide/languages.rst @@ -136,7 +136,7 @@ ___05F (5F is the hex code of an underscore.) Bind ---- -sVerilator only supports bind to a target module name, not to an +Verilator only supports bind to a target module name, not to an instance path. diff --git a/docs/guide/warnings.rst b/docs/guide/warnings.rst index 1460970b4..06c7c648b 100644 --- a/docs/guide/warnings.rst +++ b/docs/guide/warnings.rst @@ -518,7 +518,7 @@ List Of Warnings Another way DIDNOTCONVERGE may occur is if # delays are used to generate clocks. Verilator ignores the delays and gives an :option:`ASSIGNDLY` or :option:`STMTDLY` warning. If these were suppressed, due to the - absense of the delay, the code may now oscillate. + absence of the delay, the code may now oscillate. Finally, rare, more difficult cases can be debugged like a C++ program; either enter :command:`gdb` and use its tracing facilities, or edit the @@ -528,7 +528,7 @@ List Of Warnings .. option:: ENDCAPSULATED Warns that a class member is declared is local or protected, but is - being accessed from outside that class (if local) or a derrived class + being accessed from outside that class (if local) or a derived class (if protected). Ignoring this warning will only suppress the lint check, it will @@ -924,7 +924,7 @@ List Of Warnings simulate correctly. Other tools with similar warnings: Icarus Verilog's portbind, "warning: - Instantiating module ... with dangling impot port (...)". Slang's + Instantiating module ... with dangling input port (...)". Slang's unconnected-port, "port '...' has no connection".