From 713dab278c201b68db658087ff6cafde0671ee8d Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Tue, 26 Nov 2024 19:16:05 -0500
Subject: [PATCH] Fix mis-public interfaces, broke in
 f58aee2ff278d4595d6e90997c1c3d41e782d13c

---
 src/V3LinkParse.cpp                     | 13 ++++++-----
 test_regress/t/t_interface_notpublic.py | 18 +++++++++++++++
 test_regress/t/t_interface_notpublic.v  | 29 +++++++++++++++++++++++++
 3 files changed, 55 insertions(+), 5 deletions(-)
 create mode 100755 test_regress/t/t_interface_notpublic.py
 create mode 100644 test_regress/t/t_interface_notpublic.v

diff --git a/src/V3LinkParse.cpp b/src/V3LinkParse.cpp
index 1a8956a43..5c1ece2ae 100644
--- a/src/V3LinkParse.cpp
+++ b/src/V3LinkParse.cpp
@@ -430,20 +430,23 @@ class LinkParseVisitor final : public VNVisitor {
             VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
         } else if (nodep->attrType() == VAttrType::VAR_PUBLIC) {
             UASSERT_OBJ(m_varp, nodep, "Attribute not attached to variable");
-            m_varp->sigUserRWPublic(true);
-            m_varp->sigModPublic(true);
+            // Public ifacerefs aren't supported - be compatible with older parser that ignored it
+            if (!m_varp->isIfaceRef()) {
+                m_varp->sigUserRWPublic(true);
+                m_varp->sigModPublic(true);
+            }
             VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
         } else if (nodep->attrType() == VAttrType::VAR_PUBLIC_FLAT) {
             UASSERT_OBJ(m_varp, nodep, "Attribute not attached to variable");
-            m_varp->sigUserRWPublic(true);
+            if (!m_varp->isIfaceRef()) m_varp->sigUserRWPublic(true);
             VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
         } else if (nodep->attrType() == VAttrType::VAR_PUBLIC_FLAT_RD) {
             UASSERT_OBJ(m_varp, nodep, "Attribute not attached to variable");
-            m_varp->sigUserRdPublic(true);
+            if (!m_varp->isIfaceRef()) m_varp->sigUserRdPublic(true);
             VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
         } else if (nodep->attrType() == VAttrType::VAR_PUBLIC_FLAT_RW) {
             UASSERT_OBJ(m_varp, nodep, "Attribute not attached to variable");
-            m_varp->sigUserRWPublic(true);
+            if (!m_varp->isIfaceRef()) m_varp->sigUserRWPublic(true);
             VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
         } else if (nodep->attrType() == VAttrType::VAR_ISOLATE_ASSIGNMENTS) {
             UASSERT_OBJ(m_varp, nodep, "Attribute not attached to variable");
diff --git a/test_regress/t/t_interface_notpublic.py b/test_regress/t/t_interface_notpublic.py
new file mode 100755
index 000000000..d4f986441
--- /dev/null
+++ b/test_regress/t/t_interface_notpublic.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_interface_notpublic.v b/test_regress/t/t_interface_notpublic.v
new file mode 100644
index 000000000..7619519e8
--- /dev/null
+++ b/test_regress/t/t_interface_notpublic.v
@@ -0,0 +1,29 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012 by Iztok Jeras.
+// SPDX-License-Identifier: CC0-1.0
+
+interface intf
+  (input wire clk,
+   input wire rst);
+   modport intf_modp (input clk, rst);
+endinterface
+
+module sub
+  // verilator public_on
+  (intf.intf_modp intf_port);
+
+   always @ (posedge intf_port.clk) begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+   // verilator public_off
+endmodule
+
+module t(clk);
+   input clk   /*verilator public*/ ;
+   logic rst;
+   intf the_intf (.clk, .rst);
+   sub the_sub (.intf_port (the_intf));
+endmodule