diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index 30efc7884..e0926534a 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -2739,13 +2739,15 @@ private: ok = m_ds.m_dotPos == DP_SCOPE; } else if (const AstNodeFTask* const ftaskp = VN_CAST(foundp->nodep(), NodeFTask)) { if (!ftaskp->isFunction()) { - // The condition is true for tasks, properties and void functions. - // In these cases, the parentheses may be skipped. - AstFuncRef* const funcRefp - = new AstFuncRef{nodep->fileline(), nodep->name(), nullptr}; - nodep->replaceWith(funcRefp); - VL_DO_DANGLING(pushDeletep(nodep), nodep); ok = m_ds.m_dotPos == DP_NONE; + if (ok) { + // The condition is true for tasks, properties and void functions. + // In these cases, the parentheses may be skipped. + AstFuncRef* const funcRefp + = new AstFuncRef{nodep->fileline(), nodep->name(), nullptr}; + nodep->replaceWith(funcRefp); + VL_DO_DANGLING(pushDeletep(nodep), nodep); + } } } // diff --git a/test_regress/t/t_var_xref_bad.out b/test_regress/t/t_var_xref_bad.out new file mode 100644 index 000000000..7ae4ada15 --- /dev/null +++ b/test_regress/t/t_var_xref_bad.out @@ -0,0 +1,4 @@ +%Error: t/t_var_xref_bad.v:11:12: Found definition of 'tsk' as a TASK but expected a scope/variable + 11 | initial tsk.bad_missing_ref = 0; + | ^~~ +%Error: Exiting due to diff --git a/test_regress/t/t_var_xref_bad.pl b/test_regress/t/t_var_xref_bad.pl new file mode 100755 index 000000000..59ba0d6c6 --- /dev/null +++ b/test_regress/t/t_var_xref_bad.pl @@ -0,0 +1,19 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(linter => 1); + +lint( + fails => $Self->{vlt_all}, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_var_xref_bad.v b/test_regress/t/t_var_xref_bad.v new file mode 100644 index 000000000..ec7be7c09 --- /dev/null +++ b/test_regress/t/t_var_xref_bad.v @@ -0,0 +1,12 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + task tsk; + endtask + + initial tsk.bad_missing_ref = 0; +endmodule