diff --git a/docs/guide/warnings.rst b/docs/guide/warnings.rst
index f0ef61804..53c2958ab 100644
--- a/docs/guide/warnings.rst
+++ b/docs/guide/warnings.rst
@@ -1524,7 +1524,12 @@ List Of Warnings
    ANSI-style `#(...)` declarations. IEEE 1800-2023 6.20.1 requires this
    error, but some simulators accept this syntax.
 
-   Faulty example:
+   Also issued with ANSI format where a parameter without default is
+   present in the top-level module, and as such Verilator cannot know how
+   to process that module. For such cases suggest adding a default so the
+   module can lint cleanly.
+
+   Faulty non-ANSI example:
 
    .. include:: ../../docs/gen/ex_PARAMNODEFAULT_faulty.rst
 
@@ -1534,8 +1539,8 @@ List Of Warnings
 
    To fix the issue, move to an ANSI-style declaration.
 
-   Suppressing this error will only suppress the IEEE-required check; it
-   will simulate correctly.
+   For the non-ANSI case, suppressing this error will only suppress the
+   IEEE-required check; it will simulate correctly.
 
 
 .. option:: PINCONNECTEMPTY
diff --git a/test_regress/t/t_lint_paramnodefault_top_bad.out b/test_regress/t/t_lint_paramnodefault_top_bad.out
new file mode 100644
index 000000000..18cbd6d92
--- /dev/null
+++ b/test_regress/t/t_lint_paramnodefault_top_bad.out
@@ -0,0 +1,6 @@
+%Error: t/t_lint_paramnodefault_top_bad.v:8:13: Parameter without default value is never given value (IEEE 1800-2023 6.20.1): 'NODEF'
+                                              : ... note: In instance 't'
+    8 |   parameter NODEF);   
+      |             ^~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: Exiting due to
diff --git a/test_regress/t/t_lint_paramnodefault_top_bad.py b/test_regress/t/t_lint_paramnodefault_top_bad.py
new file mode 100755
index 000000000..c7d9b21a5
--- /dev/null
+++ b/test_regress/t/t_lint_paramnodefault_top_bad.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2024 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+
+test.lint(fails=True, expect_filename=test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_lint_paramnodefault_top_bad.v b/test_regress/t/t_lint_paramnodefault_top_bad.v
new file mode 100644
index 000000000..cab2da429
--- /dev/null
+++ b/test_regress/t/t_lint_paramnodefault_top_bad.v
@@ -0,0 +1,9 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2025 Wilson Snyder
+// SPDX-License-Identifier: CC0-1.0
+
+module t #(
+  parameter NODEF);  //<--- Warning
+endmodule