From 70045433c97161b9cd13b27dfdc428a4b07a525c Mon Sep 17 00:00:00 2001
From: Pawel Kojma <pkojma@internships.antmicro.com>
Date: Thu, 28 May 2026 16:04:14 +0200
Subject: [PATCH] Fix reserved keywords reaching emitter (#7666)

---
 src/V3Name.cpp                               |  1 +
 test_regress/t/t_module_reserved_keyword.out |  7 ++++++
 test_regress/t/t_module_reserved_keyword.py  | 23 ++++++++++++++++++++
 test_regress/t/t_module_reserved_keyword.v   | 11 ++++++++++
 4 files changed, 42 insertions(+)
 create mode 100644 test_regress/t/t_module_reserved_keyword.out
 create mode 100755 test_regress/t/t_module_reserved_keyword.py
 create mode 100644 test_regress/t/t_module_reserved_keyword.v

diff --git a/src/V3Name.cpp b/src/V3Name.cpp
index bcc9efe11..4220c2028 100644
--- a/src/V3Name.cpp
+++ b/src/V3Name.cpp
@@ -83,6 +83,7 @@ class NameVisitor final : public VNVisitorConst {
         VL_RESTORER(m_modp);
         m_modp = nodep;
         iterateChildrenConst(nodep);
+        rename(nodep, false);
     }
     // Add __PVT__ to names of local signals
     void visit(AstVar* nodep) override {
diff --git a/test_regress/t/t_module_reserved_keyword.out b/test_regress/t/t_module_reserved_keyword.out
new file mode 100644
index 000000000..fc6ebe31f
--- /dev/null
+++ b/test_regress/t/t_module_reserved_keyword.out
@@ -0,0 +1,7 @@
+%Warning-SYMRSVDWORD: t/t_module_reserved_keyword.v:7:8: Symbol matches C++ common word: 'interrupt'
+                                                       : ... note: In instance 'interrupt'
+    7 | module interrupt (
+      |        ^~~~~~~~~
+                      ... For warning description see https://verilator.org/warn/SYMRSVDWORD?v=latest
+                      ... Use "/* verilator lint_off SYMRSVDWORD */" and lint_on around source to disable this message.
+%Error: Exiting due to
diff --git a/test_regress/t/t_module_reserved_keyword.py b/test_regress/t/t_module_reserved_keyword.py
new file mode 100755
index 000000000..73bf16577
--- /dev/null
+++ b/test_regress/t/t_module_reserved_keyword.py
@@ -0,0 +1,23 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2024 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios("simulator")
+
+test.compile(
+    verilator_flags2=[
+        "-fno-inline",
+        "--coverage",
+    ],
+    fails=True,
+    expect_filename=test.golden_filename,
+)
+
+test.passes()
diff --git a/test_regress/t/t_module_reserved_keyword.v b/test_regress/t/t_module_reserved_keyword.v
new file mode 100644
index 000000000..133ddff44
--- /dev/null
+++ b/test_regress/t/t_module_reserved_keyword.v
@@ -0,0 +1,11 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Antmicro
+// SPDX-License-Identifier: CC0-1.0
+
+module interrupt (
+    input  logic clk_i = 1,
+    input  logic rst_ni = 1
+);
+endmodule