From 6f7bc38088a1b5a7fd152f6272f042b9693b5542 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Wed, 5 Jul 2023 14:11:55 -0400
Subject: [PATCH] Tests: Improve specparam verilog.y coverage

---
 test_regress/t/t_gate_basic.v | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/test_regress/t/t_gate_basic.v b/test_regress/t/t_gate_basic.v
index 326a23347..8ac9c0dab 100644
--- a/test_regress/t/t_gate_basic.v
+++ b/test_regress/t/t_gate_basic.v
@@ -40,12 +40,17 @@ module t (/*AUTOARG*/
    buf BARRAY [BITS-1:0] (ba, a);
 
 `ifdef verilator
+   specparam RAW_SP = 1;
+
+   specify
+   endspecify
+
    specify
       specparam CDS_LIBNAME  = "foobar";
       (nt0 *> nt0) = (0, 0);
    endspecify
 
-  specify
+   specify
     // delay parameters
     specparam
       a$A1$Y = 1.0,