From 6f28d2120761c78803b58efc5d503a2a9b81a752 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Wed, 21 Dec 2016 17:43:19 -0500 Subject: [PATCH] With --bbox-unsup, suppress desassign and mixed edges, bug1120. --- Changes | 2 ++ bin/verilator | 7 ++++--- src/V3Active.cpp | 4 +++- src/verilog.l | 2 +- src/verilog.y | 4 +++- test_regress/t/t_lint_unsup_deassign.pl | 18 ++++++++++++++++++ test_regress/t/t_lint_unsup_deassign.v | 19 +++++++++++++++++++ test_regress/t/t_lint_unsup_mixed.pl | 18 ++++++++++++++++++ test_regress/t/t_lint_unsup_mixed.v | 22 ++++++++++++++++++++++ 9 files changed, 90 insertions(+), 6 deletions(-) create mode 100755 test_regress/t/t_lint_unsup_deassign.pl create mode 100644 test_regress/t/t_lint_unsup_deassign.v create mode 100755 test_regress/t/t_lint_unsup_mixed.pl create mode 100644 test_regress/t/t_lint_unsup_mixed.v diff --git a/Changes b/Changes index d64edbe9a..0a624315c 100644 --- a/Changes +++ b/Changes @@ -5,6 +5,8 @@ The contributors that suggested a given feature are shown in []. Thanks! * Verilator 3.891 devel +**** With --bbox-unsup, suppress desassign and mixed edges, bug1120. [Galen Seitz] + **** Fix internal error on double-for loop unrolling, bug1044. [Jan Egil Ruud] **** Fix internal error on unique casez with --assert, bug1117. [Enzo Chi] diff --git a/bin/verilator b/bin/verilator index f3d6e1055..ff71a59d9 100755 --- a/bin/verilator +++ b/bin/verilator @@ -444,9 +444,10 @@ calls. =item --bbox-unsup -Black box some unsupported language features, currently UDP tables and the -cmos and tran gate primitives. This may enable linting the rest of the -design even when unsupported constructs are present. +Black box some unsupported language features, currently UDP tables, the +cmos and tran gate primitives, deassign statements, and mixed edge errors. +This may enable linting the rest of the design even when unsupported +constructs are present. =item --bin I diff --git a/src/V3Active.cpp b/src/V3Active.cpp index 1c499aecd..e7fe209f5 100644 --- a/src/V3Active.cpp +++ b/src/V3Active.cpp @@ -329,7 +329,9 @@ private: if (!combo && !sequent) combo=true; // If no list, Verilog 2000: always @ (*) if (combo && sequent) { - nodep->v3error("Unsupported: Mixed edge (pos/negedge) and activity (no edge) sensitive activity list"); + if (!v3Global.opt.bboxUnsup()) { + nodep->v3error("Unsupported: Mixed edge (pos/negedge) and activity (no edge) sensitive activity list"); + } sequent = false; } diff --git a/src/verilog.l b/src/verilog.l index aa9d8aa1e..691c153b1 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -247,6 +247,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "casex" { FL; return yCASEX; } "casez" { FL; return yCASEZ; } "cmos" { FL; return yCMOS; } + "deassign" { FL; return yDEASSIGN; } "default" { FL; return yDEFAULT; } "defparam" { FL; return yDEFPARAM; } "disable" { FL; return yDISABLE; } @@ -329,7 +330,6 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "$writeh" { FL; RETURN_BBOX_SYS_OR_MSG("Unsupported: Use $write with %%x format instead: %s",yytext); } "$writeo" { FL; RETURN_BBOX_SYS_OR_MSG("Unsupported: Use $write with %%o format instead: %s",yytext); } /* Generic unsupported warnings */ - "deassign" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } "event" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } "force" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } "fork" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } diff --git a/src/verilog.y b/src/verilog.y index 5c480796a..f17aa8afe 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -320,6 +320,7 @@ class AstSenTree; %token yCONTEXT "context" %token yCONTINUE "continue" %token yCOVER "cover" +%token yDEASSIGN "deassign" %token yDEFAULT "default" %token yDEFPARAM "defparam" %token yDISABLE "disable" @@ -2263,7 +2264,8 @@ statement_item: // IEEE: statement_item // // IEEE: procedural_continuous_assignment | yASSIGN idClassSel '=' delayE expr ';' { $$ = new AstAssign($1,$2,$5); } //UNSUP: delay_or_event_controlE above - //UNSUP yDEASSIGN variable_lvalue ';' { UNSUP } + | yDEASSIGN variable_lvalue ';' { if (!v3Global.opt.bboxUnsup()) $1->v3error("Unsupported: Verilog 1995 deassign"); $$ = NULL; } + //UNSUP yFORCE expr '=' expr ';' { UNSUP } //UNSUP yRELEASE variable_lvalue ';' { UNSUP } // diff --git a/test_regress/t/t_lint_unsup_deassign.pl b/test_regress/t/t_lint_unsup_deassign.pl new file mode 100755 index 000000000..3aea080dd --- /dev/null +++ b/test_regress/t/t_lint_unsup_deassign.pl @@ -0,0 +1,18 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +compile ( + v_flags2 => ["--lint-only --bbox-unsup"], + verilator_make_gcc => 0, + make_top_shell => 0, + make_main => 0, + ); + +ok(1); +1; diff --git a/test_regress/t/t_lint_unsup_deassign.v b/test_regress/t/t_lint_unsup_deassign.v new file mode 100644 index 000000000..f2bca1540 --- /dev/null +++ b/test_regress/t/t_lint_unsup_deassign.v @@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2016 by Wilson Snyder. + +module t + ( + input wire rst + ); + + integer q; + + always @(*) + if (rst) + assign q = 0; + else + deassign q; + +endmodule diff --git a/test_regress/t/t_lint_unsup_mixed.pl b/test_regress/t/t_lint_unsup_mixed.pl new file mode 100755 index 000000000..3aea080dd --- /dev/null +++ b/test_regress/t/t_lint_unsup_mixed.pl @@ -0,0 +1,18 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +compile ( + v_flags2 => ["--lint-only --bbox-unsup"], + verilator_make_gcc => 0, + make_top_shell => 0, + make_main => 0, + ); + +ok(1); +1; diff --git a/test_regress/t/t_lint_unsup_mixed.v b/test_regress/t/t_lint_unsup_mixed.v new file mode 100644 index 000000000..c57068b59 --- /dev/null +++ b/test_regress/t/t_lint_unsup_mixed.v @@ -0,0 +1,22 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2016 by Wilson Snyder. + +module t + ( + input wire clk, + input wire a + ); + + integer q; + + always @ (a or posedge clk) + begin + if (a) + q = 0; + else + q = q + 1; + end + +endmodule