diff --git a/test_regress/t/t_extend.py b/test_regress/t/t_extend.py index d4f986441..fc5a55e3f 100755 --- a/test_regress/t/t_extend.py +++ b/test_regress/t/t_extend.py @@ -9,7 +9,7 @@ import vltest_bootstrap -test.scenarios('simulator') +test.scenarios('vlt') test.compile() diff --git a/test_regress/t/t_extend_class.py b/test_regress/t/t_extend_c_class.py similarity index 94% rename from test_regress/t/t_extend_class.py rename to test_regress/t/t_extend_c_class.py index 6795aaac5..56d3b8278 100755 --- a/test_regress/t/t_extend_class.py +++ b/test_regress/t/t_extend_c_class.py @@ -9,7 +9,7 @@ import vltest_bootstrap -test.scenarios('vlt_all') +test.scenarios('vlt') test.compile(make_flags=["CPPFLAGS_ADD=-I" + test.t_dir]) diff --git a/test_regress/t/t_extend_class.v b/test_regress/t/t_extend_c_class.v similarity index 77% rename from test_regress/t/t_extend_class.v rename to test_regress/t/t_extend_c_class.v index 5ecbf8c4a..f564d06c3 100644 --- a/test_regress/t/t_extend_class.v +++ b/test_regress/t/t_extend_c_class.v @@ -14,7 +14,7 @@ module t (/*AUTOARG*/ reg [31:0] in; wire [31:0] out; - t_extend_class_v sub (.in(in), .out(out)); + t_extend_c_class_v sub (.in(in), .out(out)); always @ (posedge clk) begin cyc <= cyc + 8'd1; @@ -31,7 +31,7 @@ module t (/*AUTOARG*/ end endmodule -module t_extend_class_v (/*AUTOARG*/ +module t_extend_c_class_v (/*AUTOARG*/ // Outputs out, // Inputs @@ -47,11 +47,11 @@ module t_extend_class_v (/*AUTOARG*/ end `systemc_header -#include "t_extend_class_c.h" // Header for contained object +#include "t_extend_c_class_c.h" // Header for contained object `systemc_interface - t_extend_class_c* m_myobjp; // Pointer to object we are embedding + t_extend_c_class_c* m_myobjp; // Pointer to object we are embedding `systemc_ctor - m_myobjp = new t_extend_class_c(); // Construct contained object + m_myobjp = new t_extend_c_class_c(); // Construct contained object `systemc_dtor delete m_myobjp; // Destruct contained object `verilog diff --git a/test_regress/t/t_extend_class_c.h b/test_regress/t/t_extend_c_class_c.h similarity index 81% rename from test_regress/t/t_extend_class_c.h rename to test_regress/t/t_extend_c_class_c.h index d1bd62610..6a4996916 100644 --- a/test_regress/t/t_extend_class_c.h +++ b/test_regress/t/t_extend_c_class_c.h @@ -6,11 +6,11 @@ // any use, without warranty, 2006-2009 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -class t_extend_class_c { +class t_extend_c_class_c { public: // CONSTRUCTORS - t_extend_class_c() = default; - ~t_extend_class_c() = default; + t_extend_c_class_c() = default; + ~t_extend_c_class_c() = default; // METHODS // This function will be called from an instance created in Verilog uint32_t my_math(uint32_t in) { return in + 1; }