diff --git a/Changes b/Changes
index e5ecd160f..d1fcf40c1 100644
--- a/Changes
+++ b/Changes
@@ -30,6 +30,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Fix segfault on multidimensional dotted arrays, bug607.  [Jie Xu]
 
+****  Fix per-bit array output connection error, bug414.  [Jan Egil Ruud]
+
 ****  Fix package logic var compile error.
 
 ****  Fix enums with X values.
diff --git a/src/V3Inst.cpp b/src/V3Inst.cpp
index b7890aa1b..97caaf84e 100644
--- a/src/V3Inst.cpp
+++ b/src/V3Inst.cpp
@@ -198,6 +198,7 @@ private:
 		AstNode* exprp = nodep->exprp()->unlinkFrBack();
 		bool inputPin = nodep->modVarp()->isInput();
 		if (!inputPin && !exprp->castVarRef()
+		    && !exprp->castConcat()  // V3Const will collapse the SEL with the one we're about to make
 		    && !exprp->castSel()) {  // V3Const will collapse the SEL with the one we're about to make
 		    nodep->v3error("Unsupported: Per-bit array instantiations with output connections to non-wires.");
 		    // Note spec allows more complicated matches such as slices and such
diff --git a/test_regress/t/t_inst_array_partial.v b/test_regress/t/t_inst_array_partial.v
index da6439ee2..3ae5a9000 100644
--- a/test_regress/t/t_inst_array_partial.v
+++ b/test_regress/t/t_inst_array_partial.v
@@ -9,8 +9,8 @@ module t (/*AUTOARG*/
    );
    input clk;
 
-   wire [17:10] bitout;
-   wire [27:24] short_bitout;
+   wire [19:10] bitout;
+   wire [29:24] short_bitout;
    wire [7:0] 	allbits;
    wire [15:0] 	twobits;
 
@@ -37,6 +37,11 @@ module t (/*AUTOARG*/
 		   .twobits (twobits),
 		   .bitout (bitout[17:10]));
 
+   sub
+     i_sub6 [7:4] (.allbits (allbits),
+		   .twobits (twobits[15:8]),
+		   .bitout ({bitout[18+:2],short_bitout[28+:2]}));
+
    integer 	cyc=0;
    reg [63:0] 	crc;
    reg [63:0] 	sum;
@@ -44,7 +49,7 @@ module t (/*AUTOARG*/
    // Signals under test
    assign allbits = crc[7:0];
    assign twobits = crc[15:0];
-   wire [63:0] result = {52'h0, short_bitout, bitout};
+   wire [63:0] result = {48'h0, short_bitout, bitout};
 
    // Test loop
    always @ (posedge clk) begin
@@ -68,7 +73,7 @@ module t (/*AUTOARG*/
 	 $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
 	 if (crc !== 64'hc77bb9b3784ea091) $stop;
 	 // What checksum will we end up with (above print should match)
-`define EXPECTED_SUM 64'h0bf9559ce1f98425
+`define EXPECTED_SUM 64'ha1da9ff8082a4ff6
 	 if (sum !== `EXPECTED_SUM) $stop;
 	 $write("*-* All Finished *-*\n");
 	 $finish;