From 6d3dd98e77f64ecdd5c306137a891cd99fb9b63e Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Mon, 6 Apr 2009 22:26:38 -0400
Subject: [PATCH] Fix "cloning" error with -y/--top-module, bug76. Caused by
 missorting top-module cells; so move code from V3LinkLevel into V3LinkCells.

---
 test_regress/t/t_flag_topmodule_inline.pl | 18 ++++++++++++++
 test_regress/t/t_flag_topmodule_inline.v  | 29 +++++++++++++++++++++++
 2 files changed, 47 insertions(+)
 create mode 100755 test_regress/t/t_flag_topmodule_inline.pl
 create mode 100644 test_regress/t/t_flag_topmodule_inline.v

diff --git a/test_regress/t/t_flag_topmodule_inline.pl b/test_regress/t/t_flag_topmodule_inline.pl
new file mode 100755
index 000000000..da2d5fe95
--- /dev/null
+++ b/test_regress/t/t_flag_topmodule_inline.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 v_flags2 => ["--top-module b"],
+	 ) if $Self->{v3};
+
+execute (
+	 check_finished=>1,
+	 ) if $Self->{v3};
+
+ok(1);
+1;
diff --git a/test_regress/t/t_flag_topmodule_inline.v b/test_regress/t/t_flag_topmodule_inline.v
new file mode 100644
index 000000000..1b9b737ea
--- /dev/null
+++ b/test_regress/t/t_flag_topmodule_inline.v
@@ -0,0 +1,29 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2008 by Wilson Snyder.
+
+module a;
+   a2 a2 (.tmp(1'b0));
+   initial begin
+      $write("Bad top modules\n");
+      $stop;
+   end
+endmodule
+
+module a2 (input tmp);
+   l3 l3 (.tmp(tmp));
+endmodule
+
+module b;
+   l3 l3 (.tmp(1'b1));
+endmodule
+
+module l3 (input tmp);
+   initial begin
+      if (tmp) begin
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+endmodule