From 6cd26edb642645aff8b777d59ba0e2ef43ebe447 Mon Sep 17 00:00:00 2001 From: github action Date: Wed, 18 Jan 2023 16:48:16 +0000 Subject: [PATCH] Apply 'make format' --- src/verilog.y | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/verilog.y b/src/verilog.y index c6b3ccfdc..bdbd218af 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -96,8 +96,10 @@ public: bool m_tracingParse = true; // Tracing disable for parser bool m_insideProperty = false; // Is inside property declaration bool m_typedPropertyPort = false; // True if typed property port occurred on port lists - bool m_modportImpExpActive = false; // Standalone ID is a tf_identifier instead of port_identifier - bool m_modportImpExpLastIsExport = false; // Last import_export statement in modportPortsDecl is an export + bool m_modportImpExpActive + = false; // Standalone ID is a tf_identifier instead of port_identifier + bool m_modportImpExpLastIsExport + = false; // Last import_export statement in modportPortsDecl is an export int m_pinNum = -1; // Pin number currently parsing std::stack m_pinStack; // Queue of pin numbers being parsed