diff --git a/test_regress/t/t_specparam_unsup.out b/test_regress/t/t_specparam_unsup.out
new file mode 100644
index 000000000..ec5eee3ee
--- /dev/null
+++ b/test_regress/t/t_specparam_unsup.out
@@ -0,0 +1,4 @@
+%Error: t/t_specparam_unsup.v:16:8: Can't find definition of variable: 'tdevice_PU'
+   16 |       #tdevice_PU PoweredUp = 1'b1;
+      |        ^~~~~~~~~~
+%Error: Exiting due to
diff --git a/test_regress/t/t_specparam_unsup.py b/test_regress/t/t_specparam_unsup.py
new file mode 100755
index 000000000..e33e10acf
--- /dev/null
+++ b/test_regress/t/t_specparam_unsup.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.lint(fails=True, expect_filename=test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_specparam_unsup.v b/test_regress/t/t_specparam_unsup.v
new file mode 100644
index 000000000..3ac81249a
--- /dev/null
+++ b/test_regress/t/t_specparam_unsup.v
@@ -0,0 +1,18 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+// FIXME
+
+module t ();
+   reg PoweredUp;
+   specify
+      specparam tdevice_PU = 3e8;
+   endspecify
+   initial begin
+      PoweredUp = 1'b0;
+      #tdevice_PU PoweredUp = 1'b1;
+   end
+endmodule