From 6bf253deda510a12f34df9077dd0fea06cab42ff Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 24 Dec 2023 13:11:09 -0500
Subject: [PATCH] Tests: Test for unsupported default disable (#4016)

---
 test_regress/t/t_disable_iff_multi_bad.out |  8 ++++++++
 test_regress/t/t_disable_iff_multi_bad.pl  | 20 ++++++++++++++++++++
 test_regress/t/t_disable_iff_multi_bad.v   | 16 ++++++++++++++++
 3 files changed, 44 insertions(+)
 create mode 100644 test_regress/t/t_disable_iff_multi_bad.out
 create mode 100755 test_regress/t/t_disable_iff_multi_bad.pl
 create mode 100644 test_regress/t/t_disable_iff_multi_bad.v

diff --git a/test_regress/t/t_disable_iff_multi_bad.out b/test_regress/t/t_disable_iff_multi_bad.out
new file mode 100644
index 000000000..24b6b78a6
--- /dev/null
+++ b/test_regress/t/t_disable_iff_multi_bad.out
@@ -0,0 +1,8 @@
+%Error-UNSUPPORTED: t/t_disable_iff_multi_bad.v:13:4: Unsupported: default disable iff
+   13 |    default disable iff (!rstn);
+      |    ^~~~~~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error-UNSUPPORTED: t/t_disable_iff_multi_bad.v:14:4: Unsupported: default disable iff
+   14 |    default disable iff (!rstn);
+      |    ^~~~~~~
+%Error: Exiting due to
diff --git a/test_regress/t/t_disable_iff_multi_bad.pl b/test_regress/t/t_disable_iff_multi_bad.pl
new file mode 100755
index 000000000..7fdfc93e0
--- /dev/null
+++ b/test_regress/t/t_disable_iff_multi_bad.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2023 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    verilator_flags2 => ["--timing"],
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_disable_iff_multi_bad.v b/test_regress/t/t_disable_iff_multi_bad.v
new file mode 100644
index 000000000..624ab3268
--- /dev/null
+++ b/test_regress/t/t_disable_iff_multi_bad.v
@@ -0,0 +1,16 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t(/*AUTOARG*/
+   // Inputs
+   rstn
+   );
+   input rstn;
+
+   default disable iff (!rstn);
+   default disable iff (!rstn);
+
+endmodule