From 6b42d789af238eea3b91fd0c69419117f3f4764c Mon Sep 17 00:00:00 2001 From: Zhen Yan <89853352+sdjasj@users.noreply.github.com> Date: Thu, 15 May 2025 22:43:45 +0800 Subject: [PATCH] Fix checking for too-wide divide and modulus (#6003) (#6006) --- docs/CONTRIBUTORS | 1 + src/V3AstNodeExpr.h | 4 ++++ test_regress/t/t_math_wide_bad.out | 24 ++++++++++++++++++------ test_regress/t/t_math_wide_bad.v | 15 +++++++++++++-- 4 files changed, 36 insertions(+), 8 deletions(-) diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS index 28f3c1c1f..fbdf1f998 100644 --- a/docs/CONTRIBUTORS +++ b/docs/CONTRIBUTORS @@ -256,3 +256,4 @@ Zixi Li أحمد المحمودي 404allen404 Tobias Jensen +Zhen Yan diff --git a/src/V3AstNodeExpr.h b/src/V3AstNodeExpr.h index 111edca1e..8366f6f8d 100644 --- a/src/V3AstNodeExpr.h +++ b/src/V3AstNodeExpr.h @@ -2546,6 +2546,7 @@ public: string emitVerilog() override { return "%k(%l %f/ %r)"; } string emitC() override { return "VL_DIV_%nq%lq%rq(%lw, %P, %li, %ri)"; } string emitSMT() const override { return "(bvudiv %l %r)"; } + bool emitCheckMaxWords() override { return true; } bool cleanOut() const override { return false; } bool cleanLhs() const override { return true; } bool cleanRhs() const override { return true; } @@ -2593,6 +2594,7 @@ public: string emitVerilog() override { return "%k(%l %f/ %r)"; } string emitC() override { return "VL_DIVS_%nq%lq%rq(%lw, %P, %li, %ri)"; } string emitSMT() const override { return "(bvsdiv %l %r)"; } + bool emitCheckMaxWords() override { return true; } bool cleanOut() const override { return false; } bool cleanLhs() const override { return true; } bool cleanRhs() const override { return true; } @@ -3195,6 +3197,7 @@ public: string emitVerilog() override { return "%k(%l %f%% %r)"; } string emitC() override { return "VL_MODDIV_%nq%lq%rq(%lw, %P, %li, %ri)"; } string emitSMT() const override { return "(bvurem %l %r)"; } + bool emitCheckMaxWords() override { return true; } bool cleanOut() const override { return false; } bool cleanLhs() const override { return true; } bool cleanRhs() const override { return true; } @@ -3218,6 +3221,7 @@ public: string emitVerilog() override { return "%k(%l %f%% %r)"; } string emitC() override { return "VL_MODDIVS_%nq%lq%rq(%lw, %P, %li, %ri)"; } string emitSMT() const override { return "(bvsmod %l %r)"; } + bool emitCheckMaxWords() override { return true; } bool cleanOut() const override { return false; } bool cleanLhs() const override { return true; } bool cleanRhs() const override { return true; } diff --git a/test_regress/t/t_math_wide_bad.out b/test_regress/t/t_math_wide_bad.out index a95cc5a0d..826015a72 100644 --- a/test_regress/t/t_math_wide_bad.out +++ b/test_regress/t/t_math_wide_bad.out @@ -1,11 +1,23 @@ -%Error-UNSUPPORTED: t/t_math_wide_bad.v:23:19: Unsupported: operator ISTORD operator of 64 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h - 23 | assign r = real'(a); +%Error-UNSUPPORTED: t/t_math_wide_bad.v:34:19: Unsupported: operator ISTORD operator of 64 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h + 34 | assign r = real'(a); | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_math_wide_bad.v:22:18: Unsupported: operator POWSS operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h - 22 | assign z2 = a ** 3; +%Error-UNSUPPORTED: t/t_math_wide_bad.v:28:18: Unsupported: operator POWSS operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h + 28 | assign z2 = a ** 3; | ^~ -%Error-UNSUPPORTED: t/t_math_wide_bad.v:21:17: Unsupported: operator MULS operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h - 21 | assign z = a * b; +%Error-UNSUPPORTED: t/t_math_wide_bad.v:27:17: Unsupported: operator MULS operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h + 27 | assign z = a * b; | ^ +%Error-UNSUPPORTED: t/t_math_wide_bad.v:29:18: Unsupported: operator DIVS operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h + 29 | assign z3 = a / b; + | ^ +%Error-UNSUPPORTED: t/t_math_wide_bad.v:30:18: Unsupported: operator MODDIVS operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h + 30 | assign z4 = a % b; + | ^ +%Error-UNSUPPORTED: t/t_math_wide_bad.v:31:19: Unsupported: operator DIV operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h + 31 | assign z5 = ua / ub; + | ^ +%Error-UNSUPPORTED: t/t_math_wide_bad.v:32:19: Unsupported: operator MODDIV operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h + 32 | assign z6 = ua % ub; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_math_wide_bad.v b/test_regress/t/t_math_wide_bad.v index fa8705010..2f54d5456 100644 --- a/test_regress/t/t_math_wide_bad.v +++ b/test_regress/t/t_math_wide_bad.v @@ -6,20 +6,31 @@ module t (/*AUTOARG*/ // Outputs - z, z2, r, + z, z2, z3, z4, z5, z6, r, // Inputs - a, b + a, b, ua, ub ); input signed [170*32 : 0] a; input signed [170*32 : 0] b; + input [170*32 : 0] ua; + input [170*32 : 0] ub; output signed [170*32 : 0] z; output signed [170*32 : 0] z2; + output signed [170*32 : 0] z3; + output signed [170*32 : 0] z4; + output [170*32 : 0] z5; + output [170*32 : 0] z6; output real r; assign z = a * b; assign z2 = a ** 3; + assign z3 = a / b; + assign z4 = a % b; + assign z5 = ua / ub; + assign z6 = ua % ub; + assign r = real'(a); endmodule