From 6b32bb635d3089cd4b64a11c134815a812183776 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 7 May 2016 14:10:33 -0400 Subject: [PATCH] Change --l2-name default to remove 'v' naming. --- Changes | 5 ++++- bin/verilator | 9 ++++---- src/V3Options.cpp | 2 +- test_regress/t/t_assert_synth_full.pl | 2 +- test_regress/t/t_assert_synth_parallel.pl | 2 +- test_regress/t/t_cdc_async_bad.pl | 6 ++--- test_regress/t/t_cover_line.out | 12 +++++----- test_regress/t/t_cover_line.v | 12 +++++----- test_regress/t/t_cover_sva_notflat.pl | 2 +- test_regress/t/t_cover_toggle.v | 26 +++++++++++----------- test_regress/t/t_display.pl | 10 ++++----- test_regress/t/t_display_noopt.pl | 10 ++++----- test_regress/t/t_dpi_accessors.cpp | 2 +- test_regress/t/t_dpi_display.pl | 4 ++-- test_regress/t/t_dpi_dup_bad.pl | 2 +- test_regress/t/t_gen_upscope.pl | 22 +++++++++--------- test_regress/t/t_inst_tree_inl0_pub0.pl | 2 +- test_regress/t/t_inst_tree_inl0_pub1.pl | 2 +- test_regress/t/t_inst_tree_inl1_pub0.pl | 2 +- test_regress/t/t_inst_tree_inl1_pub1.pl | 2 +- test_regress/t/t_lint_multidriven_bad.pl | 2 +- test_regress/t/t_order_loop_bad.pl | 2 +- test_regress/t/t_sys_sformat.v | 4 ---- test_regress/t/t_trace_cat.out | 2 +- test_regress/t/t_trace_cat_renew.out | 2 +- test_regress/t/t_trace_cat_renew_0000.out | 2 +- test_regress/t/t_trace_cat_renew_0100.out | 2 +- test_regress/t/t_trace_cat_reopen.out | 2 +- test_regress/t/t_trace_cat_reopen_0000.out | 2 +- test_regress/t/t_trace_cat_reopen_0100.out | 2 +- test_regress/t/t_trace_complex.out | 2 +- test_regress/t/t_trace_complex_params.out | 2 +- test_regress/t/t_trace_complex_structs.out | 2 +- test_regress/t/t_trace_public.out | 2 +- test_regress/t/t_trace_public_func.cpp | 2 +- test_regress/t/t_trace_public_sig.cpp | 2 +- test_regress/t/t_uniqueif_fail1.pl | 2 +- test_regress/t/t_uniqueif_fail2.pl | 2 +- test_regress/t/t_uniqueif_fail3.pl | 2 +- test_regress/t/t_uniqueif_fail4.pl | 2 +- test_regress/t/t_unopt_combo_bad.pl | 8 +++---- test_regress/t/t_unoptflat_simple_2_bad.pl | 2 +- test_regress/t/t_var_escape.out | 2 +- test_regress/t/t_var_nonamebegin.out | 2 +- test_regress/t/t_var_nonamebegin.pl | 16 ++++++------- test_verilated/sim_main.cpp | 2 +- 46 files changed, 105 insertions(+), 105 deletions(-) diff --git a/Changes b/Changes index b91e2f6bc..4784bb24b 100644 --- a/Changes +++ b/Changes @@ -10,7 +10,10 @@ indicates the contributor was also the author of the fix; Thanks! ** Support command-line -G/+pvalue param overrides, bug1045. [Stefan Wallentowitz] -*** Add --l2-name option for controlling "v" naming, bug1050. +*** The default l2 scope name is now the same as the top-level module, bug1050. + Use "--l2-name v" for the historical behavior. + +*** Add --l2-name option for controlling "v" naming. * Verilator 3.882 2016-03-01 diff --git a/bin/verilator b/bin/verilator index 4d912b987..a805ad3b2 100755 --- a/bin/verilator +++ b/bin/verilator @@ -789,11 +789,12 @@ in the Make variable LDLIBS, not LDFLAGS.) =item --l2-name I Instead of using the module name when showing Verilog scope, use the name -provided. Default is "--l2-name v" and is used to standardize some wrapping -methodologies. +provided. This allows simplifying some Verilator-embedded modeling +methodologies. Default is an l2-name matching the top module. The default +before 3.884 was "--l2-name v" -The program "module t; initial $display("= %m"); endmodule" will show by -default "= t". With "--l2-name v" it will print "= v". +For example, the program "module t; initial $display("%m"); endmodule" will +show by default "t". With "--l2-name v" it will print "v". =item --language I diff --git a/src/V3Options.cpp b/src/V3Options.cpp index 844aaa5f2..fa30d16a6 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -1250,7 +1250,7 @@ V3Options::V3Options() { m_makeDir = "obj_dir"; m_bin = ""; m_flags = ""; - m_l2Name = "v"; + m_l2Name = ""; m_unusedRegexp = "*unused*"; m_xAssign = "fast"; diff --git a/test_regress/t/t_assert_synth_full.pl b/test_regress/t/t_assert_synth_full.pl index 46311ebea..30093da53 100755 --- a/test_regress/t/t_assert_synth_full.pl +++ b/test_regress/t/t_assert_synth_full.pl @@ -19,7 +19,7 @@ execute ( check_finished=>0, fails=> $Self->{vlt}, expect=> -'%Error: t_assert_synth.v:\d+: Assertion failed in top.v: synthesis full_case' +'%Error: t_assert_synth.v:\d+: Assertion failed in top.t: synthesis full_case' ); ok(1); diff --git a/test_regress/t/t_assert_synth_parallel.pl b/test_regress/t/t_assert_synth_parallel.pl index 599eaa232..b6776f9c4 100755 --- a/test_regress/t/t_assert_synth_parallel.pl +++ b/test_regress/t/t_assert_synth_parallel.pl @@ -19,7 +19,7 @@ execute ( check_finished=>0, fails => $Self->{v3}, expect=> -'%Error: t_assert_synth.v:\d+: Assertion failed in top.v: synthesis parallel_case' +'%Error: t_assert_synth.v:\d+: Assertion failed in top.t: synthesis parallel_case' ); ok(1); diff --git a/test_regress/t/t_cdc_async_bad.pl b/test_regress/t/t_cdc_async_bad.pl index 6da31872a..d231e9506 100755 --- a/test_regress/t/t_cdc_async_bad.pl +++ b/test_regress/t/t_cdc_async_bad.pl @@ -12,11 +12,11 @@ compile ( verilator_make_gcc => 0, fails => 1, expect=> -'%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:\d+: Logic in path that feeds async reset, via signal: v.rst2_bad_n +'%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:\d+: Logic in path that feeds async reset, via signal: t.rst2_bad_n %Warning-CDCRSTLOGIC: Use "/\* verilator lint_off CDCRSTLOGIC \*/" and lint_on around source to disable this message. %Warning-CDCRSTLOGIC: See details in obj_dir/t_cdc_async_bad/Vt_cdc_async_bad__cdc.txt -%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:\d+: Logic in path that feeds async reset, via signal: v.rst6a_bad_n -%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:\d+: Logic in path that feeds async reset, via signal: v.rst6b_bad_n +%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:\d+: Logic in path that feeds async reset, via signal: t.rst6a_bad_n +%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:\d+: Logic in path that feeds async reset, via signal: t.rst6b_bad_n %Error: Exiting due to.*', ); diff --git a/test_regress/t/t_cover_line.out b/test_regress/t/t_cover_line.out index c6840d21a..31873558e 100644 --- a/test_regress/t/t_cover_line.out +++ b/test_regress/t/t_cover_line.out @@ -77,7 +77,7 @@ input toggle; always @ (posedge clk) begin %000002 if (toggle) begin - // CHECK_COVER(-1,"top.v.a*",2) + // CHECK_COVER(-1,"top.t.a*",2) // t.a1 and t.a2 collapse to a count of 2 end if (toggle) begin @@ -100,11 +100,11 @@ always @ (posedge clk) begin %000000 if (0) begin - // CHECK_COVER(-1,"top.v.b*",0) + // CHECK_COVER(-1,"top.t.b*",0) // Make sure that we don't optimize away zero buckets end %000002 if (toggle) begin - // CHECK_COVER(-1,"top.v.b*",2) + // CHECK_COVER(-1,"top.t.b*",2) // t.b1 and t.b2 collapse to a count of 2 end if (toggle) begin @@ -133,10 +133,10 @@ input external; begin %000001 if (toggle) begin - // CHECK_COVER(-1,"top.v.t1",1) + // CHECK_COVER(-1,"top.t.t1",1) end %000001 if (external) begin - // CHECK_COVER(-1,"top.v.t1",1) + // CHECK_COVER(-1,"top.t.t1",1) $write("[%0t] Got external pulse\n", $time); end end @@ -161,7 +161,7 @@ // verilator coverage_on always @ (posedge clk) begin %000001 if (toggle) begin - // CHECK_COVER(-1,"top.v.o1",1) + // CHECK_COVER(-1,"top.t.o1",1) // because under coverage_module_off end end diff --git a/test_regress/t/t_cover_line.v b/test_regress/t/t_cover_line.v index 65c8d521a..7cb84decf 100644 --- a/test_regress/t/t_cover_line.v +++ b/test_regress/t/t_cover_line.v @@ -76,7 +76,7 @@ module alpha (/*AUTOARG*/ input toggle; always @ (posedge clk) begin if (toggle) begin - // CHECK_COVER(-1,"top.v.a*",2) + // CHECK_COVER(-1,"top.t.a*",2) // t.a1 and t.a2 collapse to a count of 2 end if (toggle) begin @@ -99,11 +99,11 @@ module beta (/*AUTOARG*/ always @ (posedge clk) begin if (0) begin - // CHECK_COVER(-1,"top.v.b*",0) + // CHECK_COVER(-1,"top.t.b*",0) // Make sure that we don't optimize away zero buckets end if (toggle) begin - // CHECK_COVER(-1,"top.v.b*",2) + // CHECK_COVER(-1,"top.t.b*",2) // t.b1 and t.b2 collapse to a count of 2 end if (toggle) begin @@ -132,10 +132,10 @@ module tsk (/*AUTOARG*/ input external; begin if (toggle) begin - // CHECK_COVER(-1,"top.v.t1",1) + // CHECK_COVER(-1,"top.t.t1",1) end if (external) begin - // CHECK_COVER(-1,"top.v.t1",1) + // CHECK_COVER(-1,"top.t.t1",1) $write("[%0t] Got external pulse\n", $time); end end @@ -160,7 +160,7 @@ module off (/*AUTOARG*/ // verilator coverage_on always @ (posedge clk) begin if (toggle) begin - // CHECK_COVER(-1,"top.v.o1",1) + // CHECK_COVER(-1,"top.t.o1",1) // because under coverage_module_off end end diff --git a/test_regress/t/t_cover_sva_notflat.pl b/test_regress/t/t_cover_sva_notflat.pl index 9ee0511c3..5b60c8781 100755 --- a/test_regress/t/t_cover_sva_notflat.pl +++ b/test_regress/t/t_cover_sva_notflat.pl @@ -20,7 +20,7 @@ execute ( # Allow old Perl format dump, or new binary dump # Check that the hierarchy doesn't include __PVT__ # Otherwise our coverage reports would look really ugly -file_grep ($Self->{coverage_filename}, qr/(top\.v\.sub.*.cyc_eq_5)/) +file_grep ($Self->{coverage_filename}, qr/(top\.t\.sub.*.cyc_eq_5)/) if $Self->{vlt}; ok(1); diff --git a/test_regress/t/t_cover_toggle.v b/test_regress/t/t_cover_toggle.v index 8dce8e3c8..e1979e639 100644 --- a/test_regress/t/t_cover_toggle.v +++ b/test_regress/t/t_cover_toggle.v @@ -95,25 +95,25 @@ module alpha (/*AUTOARG*/ input clk; input toggle; - // CHECK_COVER(-1,"top.v.a*",4) + // CHECK_COVER(-1,"top.t.a*",4) // 2 edges * (t.a1 and t.a2) input [7:0] cyc_copy; - // CHECK_COVER(-1,"top.v.a*","cyc_copy[0]",22) - // CHECK_COVER(-2,"top.v.a*","cyc_copy[1]",10) - // CHECK_COVER(-3,"top.v.a*","cyc_copy[2]",4) - // CHECK_COVER(-4,"top.v.a*","cyc_copy[3]",2) - // CHECK_COVER(-5,"top.v.a*","cyc_copy[4]",0) - // CHECK_COVER(-6,"top.v.a*","cyc_copy[5]",0) - // CHECK_COVER(-7,"top.v.a*","cyc_copy[6]",0) - // CHECK_COVER(-8,"top.v.a*","cyc_copy[7]",0) + // CHECK_COVER(-1,"top.t.a*","cyc_copy[0]",22) + // CHECK_COVER(-2,"top.t.a*","cyc_copy[1]",10) + // CHECK_COVER(-3,"top.t.a*","cyc_copy[2]",4) + // CHECK_COVER(-4,"top.t.a*","cyc_copy[3]",2) + // CHECK_COVER(-5,"top.t.a*","cyc_copy[4]",0) + // CHECK_COVER(-6,"top.t.a*","cyc_copy[5]",0) + // CHECK_COVER(-7,"top.t.a*","cyc_copy[6]",0) + // CHECK_COVER(-8,"top.t.a*","cyc_copy[7]",0) reg toggle_internal; - // CHECK_COVER(-1,"top.v.a*",4) + // CHECK_COVER(-1,"top.t.a*",4) // 2 edges * (t.a1 and t.a2) output reg toggle_up; - // CHECK_COVER(-1,"top.v.a*",4) + // CHECK_COVER(-1,"top.t.a*",4) // 2 edges * (t.a1 and t.a2) always @ (posedge clk) begin @@ -130,7 +130,7 @@ module beta (/*AUTOARG*/ input clk; input toggle_up; - // CHECK_COVER(-1,"top.v.b1","toggle_up",2) + // CHECK_COVER(-1,"top.t.b1","toggle_up",2) /* verilator public_module */ @@ -150,6 +150,6 @@ module off (/*AUTOARG*/ // verilator coverage_on input toggle; - // CHECK_COVER(-1,"top.v.o1","toggle",2) + // CHECK_COVER(-1,"top.t.o1","toggle",2) endmodule diff --git a/test_regress/t/t_display.pl b/test_regress/t/t_display.pl index df8a0c615..64f3c27b1 100755 --- a/test_regress/t/t_display.pl +++ b/test_regress/t/t_display.pl @@ -13,11 +13,11 @@ compile ( execute ( check_finished=>1, expect=>dequote( -q{[0] In top.v: Hi -[0] In top.v.sub (sub) -[0] In top.v.sub.subblock (sub) -[0] In top.v.sub2 (sub2) -[0] In top.v.sub2.subblock2 (sub2) +q{[0] In top.t: Hi +[0] In top.t.sub (sub) +[0] In top.t.sub.subblock (sub) +[0] In top.t.sub2 (sub2) +[0] In top.t.sub2.subblock2 (sub2) [0] Back \ Quote " [0] %b=000001100 %0b=1100 %b=00000101010111011101110111100110011001100 %0b=101010111011101110111100110011001100 %b=000001010101111000001001000110100010101100111100000010010001101000101011001111000 %0b=1010101111000001001000110100010101100111100000010010001101000101011001111000 [0] %B=000001100 %0B=1100 %B=00000101010111011101110111100110011001100 %0B=101010111011101110111100110011001100 %B=000001010101111000001001000110100010101100111100000010010001101000101011001111000 %0B=1010101111000001001000110100010101100111100000010010001101000101011001111000 diff --git a/test_regress/t/t_display_noopt.pl b/test_regress/t/t_display_noopt.pl index d49c6e580..59cbb7ee0 100755 --- a/test_regress/t/t_display_noopt.pl +++ b/test_regress/t/t_display_noopt.pl @@ -16,11 +16,11 @@ compile ( execute ( check_finished=>1, expect=>dequote( -q{[0] In top.v: Hi -[0] In top.v.sub (sub) -[0] In top.v.sub.subblock (sub) -[0] In top.v.sub2 (sub2) -[0] In top.v.sub2.subblock2 (sub2) +q{[0] In top.t: Hi +[0] In top.t.sub (sub) +[0] In top.t.sub.subblock (sub) +[0] In top.t.sub2 (sub2) +[0] In top.t.sub2.subblock2 (sub2) [0] Back \ Quote " [0] %b=000001100 %0b=1100 %b=00000101010111011101110111100110011001100 %0b=101010111011101110111100110011001100 %b=000001010101111000001001000110100010101100111100000010010001101000101011001111000 %0b=1010101111000001001000110100010101100111100000010010001101000101011001111000 [0] %B=000001100 %0B=1100 %B=00000101010111011101110111100110011001100 %0B=101010111011101110111100110011001100 %B=000001010101111000001001000110100010101100111100000010010001101000101011001111000 %0B=1010101111000001001000110100010101100111100000010010001101000101011001111000 diff --git a/test_regress/t/t_dpi_accessors.cpp b/test_regress/t/t_dpi_accessors.cpp index b30aafdd0..4645638cf 100644 --- a/test_regress/t/t_dpi_accessors.cpp +++ b/test_regress/t/t_dpi_accessors.cpp @@ -90,7 +90,7 @@ checkResult (bool p, int main () { Vt_dpi_accessors *dut = new Vt_dpi_accessors ("dut"); - svSetScope (svGetScopeFromName ("dut.v")); + svSetScope (svGetScopeFromName ("dut.t")); // evaluate the model with no signal changes to get the initial blocks // executed. diff --git a/test_regress/t/t_dpi_display.pl b/test_regress/t/t_dpi_display.pl index 61d536338..ac27ec314 100755 --- a/test_regress/t/t_dpi_display.pl +++ b/test_regress/t/t_dpi_display.pl @@ -22,8 +22,8 @@ dpii_display_call: constant dpii_display_call: constant_value one10=0000000a dpii_display_call: one10=0000000a -Mod=top.v 16= 10 10=0000000a -dpii_display_call: Mod=top.v 16= 10 10=0000000a +Mod=top.t 16= 10 10=0000000a +dpii_display_call: Mod=top.t 16= 10 10=0000000a *-* All Finished *-* }), ); diff --git a/test_regress/t/t_dpi_dup_bad.pl b/test_regress/t/t_dpi_dup_bad.pl index 97d32f718..f5bd35556 100755 --- a/test_regress/t/t_dpi_dup_bad.pl +++ b/test_regress/t/t_dpi_dup_bad.pl @@ -11,7 +11,7 @@ compile ( v_flags2 => ["--lint-only"], fails=>$Self->{v3}, expect=> -'%Error: t/t_dpi_dup_bad.v:\d+: Duplicate declaration of DPI function with different formal arguments: v.oth_f_int2 +'%Error: t/t_dpi_dup_bad.v:\d+: Duplicate declaration of DPI function with different formal arguments: t.oth_f_int2 %Error: t/t_dpi_dup_bad.v:\d+: ... New prototype: pure int dpii_fa_bit \(int, int\) %Error: t/t_dpi_dup_bad.v:\d+: ... Original prototype: int dpii_fa_bit \(int\) %Error: Exiting due to .*' diff --git a/test_regress/t/t_gen_upscope.pl b/test_regress/t/t_gen_upscope.pl index b6cd565dd..1d26eb10b 100755 --- a/test_regress/t/t_gen_upscope.pl +++ b/test_regress/t/t_gen_upscope.pl @@ -13,17 +13,17 @@ compile ( execute ( check_finished=>1, expect=>quotemeta( -q{created tag with scope = top.v.b.gen[0].tag -created tag with scope = top.v.b.gen[1].tag -created tag with scope = top.v.tag -mod a has scope = top.v -mod a has tag = top.v.tag -mod b has scope = top.v.b -mod b has tag = top.v.tag -mod c has scope = top.v.b.gen[0].c -mod c has tag = top.v.b.gen[0].tag -mod c has scope = top.v.b.gen[1].c -mod c has tag = top.v.b.gen[1].tag +q{created tag with scope = top.t.b.gen[0].tag +created tag with scope = top.t.b.gen[1].tag +created tag with scope = top.t.tag +mod a has scope = top.t +mod a has tag = top.t.tag +mod b has scope = top.t.b +mod b has tag = top.t.tag +mod c has scope = top.t.b.gen[0].c +mod c has tag = top.t.b.gen[0].tag +mod c has scope = top.t.b.gen[1].c +mod c has tag = top.t.b.gen[1].tag *-* All Finished *-*}), ); diff --git a/test_regress/t/t_inst_tree_inl0_pub0.pl b/test_regress/t/t_inst_tree_inl0_pub0.pl index 4ca581eab..cb1704bb1 100755 --- a/test_regress/t/t_inst_tree_inl0_pub0.pl +++ b/test_regress/t/t_inst_tree_inl0_pub0.pl @@ -16,7 +16,7 @@ compile ( execute ( check_finished=>1, expect=> -'\] (%m|.*v\.ps): Clocked +'\] (%m|.*t\.ps): Clocked ', ); diff --git a/test_regress/t/t_inst_tree_inl0_pub1.pl b/test_regress/t/t_inst_tree_inl0_pub1.pl index 84f019831..e39952266 100755 --- a/test_regress/t/t_inst_tree_inl0_pub1.pl +++ b/test_regress/t/t_inst_tree_inl0_pub1.pl @@ -20,7 +20,7 @@ if ($Self->{vlt}) { execute ( check_finished=>1, expect=> -'\] (%m|.*v\.ps): Clocked +'\] (%m|.*t\.ps): Clocked ', ); diff --git a/test_regress/t/t_inst_tree_inl1_pub0.pl b/test_regress/t/t_inst_tree_inl1_pub0.pl index a23533243..001d36d28 100755 --- a/test_regress/t/t_inst_tree_inl1_pub0.pl +++ b/test_regress/t/t_inst_tree_inl1_pub0.pl @@ -16,7 +16,7 @@ compile ( execute ( check_finished=>1, expect=> -'\] (%m|.*v\.ps): Clocked +'\] (%m|.*t\.ps): Clocked ', ); diff --git a/test_regress/t/t_inst_tree_inl1_pub1.pl b/test_regress/t/t_inst_tree_inl1_pub1.pl index 9ad44cd20..d6905ac09 100755 --- a/test_regress/t/t_inst_tree_inl1_pub1.pl +++ b/test_regress/t/t_inst_tree_inl1_pub1.pl @@ -16,7 +16,7 @@ compile ( execute ( check_finished=>1, expect=> -'\] (%m|.*v\.ps): Clocked +'\] (%m|.*t\.ps): Clocked ', ); diff --git a/test_regress/t/t_lint_multidriven_bad.pl b/test_regress/t/t_lint_multidriven_bad.pl index bfdfa9906..8eb339845 100755 --- a/test_regress/t/t_lint_multidriven_bad.pl +++ b/test_regress/t/t_lint_multidriven_bad.pl @@ -16,7 +16,7 @@ compile ( make_top_shell => 0, make_main => 0, expect=> -'%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:\d+: Signal has multiple driving blocks: v.mem +'%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:\d+: Signal has multiple driving blocks: t.mem %Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:\d+: ... Location of first driving block %Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:\d+: ... Location of other driving block %Warning-MULTIDRIVEN: Use ".*" and lint_on around source to disable this message. diff --git a/test_regress/t/t_order_loop_bad.pl b/test_regress/t/t_order_loop_bad.pl index a2b472616..1275a65f0 100755 --- a/test_regress/t/t_order_loop_bad.pl +++ b/test_regress/t/t_order_loop_bad.pl @@ -16,7 +16,7 @@ compile ( expect=> '%Error: Circular logic when ordering code .* %Error: Example path: t/t_order_loop_bad.v:\d+: ALWAYS -%Error: Example path: t/t_order_loop_bad.v:\d+: v.ready +%Error: Example path: t/t_order_loop_bad.v:\d+: t.ready %Error: Example path: t/t_order_loop_bad.v:\d+: ACTIVE .*', ); diff --git a/test_regress/t/t_sys_sformat.v b/test_regress/t/t_sys_sformat.v index 4ea8fc522..29ea527b0 100644 --- a/test_regress/t/t_sys_sformat.v +++ b/test_regress/t/t_sys_sformat.v @@ -49,11 +49,7 @@ module t; $swrite(str2, "mod=%m"); `ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif -`ifdef verilator - if (str2 !== "mod=top.v") $stop; -`else if (str2 !== "mod=top.t") $stop; -`endif $swrite(str2, "lib=%l"); `ifdef TEST_VERBOSE $display("chkl %0s",str2); `endif diff --git a/test_regress/t/t_trace_cat.out b/test_regress/t/t_trace_cat.out index 5d363ff4e..f3182da5d 100644 --- a/test_regress/t/t_trace_cat.out +++ b/test_regress/t/t_trace_cat.out @@ -5,7 +5,7 @@ $timescale 1ns $end $scope module top $end $var wire 1 $ clk $end - $scope module v $end + $scope module t $end $var wire 1 $ clk $end $var wire 32 # cyc [31:0] $end $upscope $end diff --git a/test_regress/t/t_trace_cat_renew.out b/test_regress/t/t_trace_cat_renew.out index 4dcea00bf..127461f51 100644 --- a/test_regress/t/t_trace_cat_renew.out +++ b/test_regress/t/t_trace_cat_renew.out @@ -5,7 +5,7 @@ $timescale 1ns $end $scope module top $end $var wire 1 $ clk $end - $scope module v $end + $scope module t $end $var wire 1 $ clk $end $var wire 32 # cyc [31:0] $end $upscope $end diff --git a/test_regress/t/t_trace_cat_renew_0000.out b/test_regress/t/t_trace_cat_renew_0000.out index 51dddba4d..a9bb8fde5 100644 --- a/test_regress/t/t_trace_cat_renew_0000.out +++ b/test_regress/t/t_trace_cat_renew_0000.out @@ -5,7 +5,7 @@ $timescale 1ns $end $scope module top $end $var wire 1 $ clk $end - $scope module v $end + $scope module t $end $var wire 1 $ clk $end $var wire 32 # cyc [31:0] $end $upscope $end diff --git a/test_regress/t/t_trace_cat_renew_0100.out b/test_regress/t/t_trace_cat_renew_0100.out index 40746638f..f5fb14784 100644 --- a/test_regress/t/t_trace_cat_renew_0100.out +++ b/test_regress/t/t_trace_cat_renew_0100.out @@ -5,7 +5,7 @@ $timescale 1ns $end $scope module top $end $var wire 1 $ clk $end - $scope module v $end + $scope module t $end $var wire 1 $ clk $end $var wire 32 # cyc [31:0] $end $upscope $end diff --git a/test_regress/t/t_trace_cat_reopen.out b/test_regress/t/t_trace_cat_reopen.out index 4dcea00bf..127461f51 100644 --- a/test_regress/t/t_trace_cat_reopen.out +++ b/test_regress/t/t_trace_cat_reopen.out @@ -5,7 +5,7 @@ $timescale 1ns $end $scope module top $end $var wire 1 $ clk $end - $scope module v $end + $scope module t $end $var wire 1 $ clk $end $var wire 32 # cyc [31:0] $end $upscope $end diff --git a/test_regress/t/t_trace_cat_reopen_0000.out b/test_regress/t/t_trace_cat_reopen_0000.out index 51dddba4d..a9bb8fde5 100644 --- a/test_regress/t/t_trace_cat_reopen_0000.out +++ b/test_regress/t/t_trace_cat_reopen_0000.out @@ -5,7 +5,7 @@ $timescale 1ns $end $scope module top $end $var wire 1 $ clk $end - $scope module v $end + $scope module t $end $var wire 1 $ clk $end $var wire 32 # cyc [31:0] $end $upscope $end diff --git a/test_regress/t/t_trace_cat_reopen_0100.out b/test_regress/t/t_trace_cat_reopen_0100.out index 40746638f..f5fb14784 100644 --- a/test_regress/t/t_trace_cat_reopen_0100.out +++ b/test_regress/t/t_trace_cat_reopen_0100.out @@ -5,7 +5,7 @@ $timescale 1ns $end $scope module top $end $var wire 1 $ clk $end - $scope module v $end + $scope module t $end $var wire 1 $ clk $end $var wire 32 # cyc [31:0] $end $upscope $end diff --git a/test_regress/t/t_trace_complex.out b/test_regress/t/t_trace_complex.out index ea1006e99..8182e06a9 100644 --- a/test_regress/t/t_trace_complex.out +++ b/test_regress/t/t_trace_complex.out @@ -8,7 +8,7 @@ $timescale 1ns $end $scope module $unit $end $var wire 1 # global_bit $end $upscope $end - $scope module v $end + $scope module t $end $var wire 1 9 clk $end $var wire 32 $ cyc [31:0] $end $var real 64 3 v_arr_real(0) $end diff --git a/test_regress/t/t_trace_complex_params.out b/test_regress/t/t_trace_complex_params.out index 850d62d35..156554949 100644 --- a/test_regress/t/t_trace_complex_params.out +++ b/test_regress/t/t_trace_complex_params.out @@ -8,7 +8,7 @@ $timescale 1ns $end $scope module $unit $end $var wire 1 # global_bit $end $upscope $end - $scope module v $end + $scope module t $end $var wire 1 9 clk $end $var wire 32 $ cyc [31:0] $end $var real 64 3 v_arr_real(0) $end diff --git a/test_regress/t/t_trace_complex_structs.out b/test_regress/t/t_trace_complex_structs.out index f1274bc1b..0940b4eb6 100644 --- a/test_regress/t/t_trace_complex_structs.out +++ b/test_regress/t/t_trace_complex_structs.out @@ -8,7 +8,7 @@ $timescale 1ns $end $scope module $unit $end $var wire 1 # global_bit $end $upscope $end - $scope module v $end + $scope module t $end $var wire 1 D clk $end $var wire 32 $ cyc [31:0] $end $var real 64 > v_arr_real(0) $end diff --git a/test_regress/t/t_trace_public.out b/test_regress/t/t_trace_public.out index 75cb651c4..0eb246678 100644 --- a/test_regress/t/t_trace_public.out +++ b/test_regress/t/t_trace_public.out @@ -6,7 +6,7 @@ $timescale 1ns $end $scope module top $end $var wire 1 6 CLK $end $var wire 1 7 RESET $end - $scope module v $end + $scope module t $end $var wire 1 6 CLK $end $var wire 1 # RESET $end $var wire 32 $ val [31:0] $end diff --git a/test_regress/t/t_trace_public_func.cpp b/test_regress/t/t_trace_public_func.cpp index 8a1aafd82..a69bbca8d 100644 --- a/test_regress/t/t_trace_public_func.cpp +++ b/test_regress/t/t_trace_public_func.cpp @@ -33,7 +33,7 @@ int main(int argc, char **argv, char **env) { top->CLK = (main_time/dt_2)%2; top->eval(); - top->v->glbl->setGSR(main_time < 7); + top->t->glbl->setGSR(main_time < 7); tfp->dump((unsigned int)(main_time)); ++main_time; diff --git a/test_regress/t/t_trace_public_sig.cpp b/test_regress/t/t_trace_public_sig.cpp index 4ad487d7b..03283a514 100644 --- a/test_regress/t/t_trace_public_sig.cpp +++ b/test_regress/t/t_trace_public_sig.cpp @@ -33,7 +33,7 @@ int main(int argc, char **argv, char **env) { top->CLK = (main_time/dt_2)%2; top->eval(); - top->v->glbl->GSR = (main_time < 7); + top->t->glbl->GSR = (main_time < 7); tfp->dump((unsigned int)(main_time)); ++main_time; diff --git a/test_regress/t/t_uniqueif_fail1.pl b/test_regress/t/t_uniqueif_fail1.pl index c63c5dfd3..19b745598 100755 --- a/test_regress/t/t_uniqueif_fail1.pl +++ b/test_regress/t/t_uniqueif_fail1.pl @@ -19,7 +19,7 @@ compile ( execute ( fails => $Self->{vlt}, expect=> -'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.v: \'unique if\' statement violated +'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.t: \'unique if\' statement violated %Error: t/t_uniqueif.v:\d+: Verilog \$stop .*', ); diff --git a/test_regress/t/t_uniqueif_fail2.pl b/test_regress/t/t_uniqueif_fail2.pl index 6b1977571..a534ca47b 100755 --- a/test_regress/t/t_uniqueif_fail2.pl +++ b/test_regress/t/t_uniqueif_fail2.pl @@ -19,7 +19,7 @@ compile ( execute ( fails => $Self->{vlt}, expect=> -'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.v: \'unique if\' statement violated +'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.t: \'unique if\' statement violated %Error: t/t_uniqueif.v:\d+: Verilog \$stop .*', ); diff --git a/test_regress/t/t_uniqueif_fail3.pl b/test_regress/t/t_uniqueif_fail3.pl index 3a069f18d..43d8b0194 100755 --- a/test_regress/t/t_uniqueif_fail3.pl +++ b/test_regress/t/t_uniqueif_fail3.pl @@ -19,7 +19,7 @@ compile ( execute ( fails => $Self->{vlt}, expect=> -'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.v: \'unique if\' statement violated +'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.t: \'unique if\' statement violated %Error: t/t_uniqueif.v:\d+: Verilog \$stop .*', ); diff --git a/test_regress/t/t_uniqueif_fail4.pl b/test_regress/t/t_uniqueif_fail4.pl index 2f16cd47f..29170b282 100755 --- a/test_regress/t/t_uniqueif_fail4.pl +++ b/test_regress/t/t_uniqueif_fail4.pl @@ -19,7 +19,7 @@ compile ( execute ( fails => $Self->{vlt}, expect=> -'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.v: \'unique if\' statement violated +'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.t: \'unique if\' statement violated %Error: t/t_uniqueif.v:\d+: Verilog \$stop .*', ); diff --git a/test_regress/t/t_unopt_combo_bad.pl b/test_regress/t/t_unopt_combo_bad.pl index 109e08aff..a5a4c3e20 100755 --- a/test_regress/t/t_unopt_combo_bad.pl +++ b/test_regress/t/t_unopt_combo_bad.pl @@ -12,13 +12,13 @@ top_filename("t/t_unopt_combo.v"); compile ( fails=>$Self->{vlt}, expect=> -'%Warning-UNOPTFLAT: t/t_unopt_combo.v:\d+: Signal unoptimizable: Feedback to clock or circular logic: v.c +'%Warning-UNOPTFLAT: t/t_unopt_combo.v:\d+: Signal unoptimizable: Feedback to clock or circular logic: t.c %Warning-UNOPTFLAT: Use "/\* verilator lint_off UNOPTFLAT \*/" and lint_on around source to disable this message. -%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: v.c +%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: t.c %Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: ALWAYS -%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: v.b +%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: t.b %Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: ALWAYS -%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: v.c +%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: t.c %Error: Exiting due to ' ); diff --git a/test_regress/t/t_unoptflat_simple_2_bad.pl b/test_regress/t/t_unoptflat_simple_2_bad.pl index ecb077c39..e3db81c7e 100755 --- a/test_regress/t/t_unoptflat_simple_2_bad.pl +++ b/test_regress/t/t_unoptflat_simple_2_bad.pl @@ -16,7 +16,7 @@ compile ( fails => 1, expect=> '.*%Warning-UNOPTFLAT: Widest candidate vars to split: -%Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:\d+: v.x, width 3, fanout \d+ +%Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:\d+: t.x, width 3, fanout \d+ .*%Error: Exiting due to ', ); diff --git a/test_regress/t/t_var_escape.out b/test_regress/t/t_var_escape.out index 44f578b16..81c3ce6af 100644 --- a/test_regress/t/t_var_escape.out +++ b/test_regress/t/t_var_escape.out @@ -9,7 +9,7 @@ $timescale 1ns $end $var wire 1 ' clk $end $var wire 1 ) double__underscore $end $var wire 1 ( escaped_normal $end - $scope module v $end + $scope module t $end $var wire 1 * 9num $end $var wire 32 & a0.cyc [31:0] $end $var wire 1 + bra[ket]slash/dash-colon:9backslash\done $end diff --git a/test_regress/t/t_var_nonamebegin.out b/test_regress/t/t_var_nonamebegin.out index 1fecfae58..cad20277c 100644 --- a/test_regress/t/t_var_nonamebegin.out +++ b/test_regress/t/t_var_nonamebegin.out @@ -6,7 +6,7 @@ $timescale 1ns $end $scope module top $end $var wire 1 # clk $end $var wire 1 $ reset_l $end - $scope module v $end + $scope module t $end $var wire 1 # clk $end $var wire 1 % inmod $end $var wire 32 & rawmod [31:0] $end diff --git a/test_regress/t/t_var_nonamebegin.pl b/test_regress/t/t_var_nonamebegin.pl index 57b09328c..fea02309b 100755 --- a/test_regress/t/t_var_nonamebegin.pl +++ b/test_regress/t/t_var_nonamebegin.pl @@ -13,14 +13,14 @@ compile ( execute ( expect=>quotemeta( -'ingen: {mod}.genblk1 top.v.genblk1 -d3a: {mod}.d3nameda top.v.d3nameda -b2: {mod} top.v -b3n: {mod}.b3named: top.v.b3named -b3: {mod} top.v -b4: {mod} top.v -t1 {mod}.tsk top.v -t2 {mod}.tsk top.v +'ingen: {mod}.genblk1 top.t.genblk1 +d3a: {mod}.d3nameda top.t.d3nameda +b2: {mod} top.t +b3n: {mod}.b3named: top.t.b3named +b3: {mod} top.t +b4: {mod} top.t +t1 {mod}.tsk top.t +t2 {mod}.tsk top.t *-* All Finished *-*'), ); diff --git a/test_verilated/sim_main.cpp b/test_verilated/sim_main.cpp index 839ff9b96..5fc2d4f53 100644 --- a/test_verilated/sim_main.cpp +++ b/test_verilated/sim_main.cpp @@ -29,7 +29,7 @@ int main(int argc, char **argv, char **env) { #define CYCTIME 10 // Cycle the interpreter - while (main_time < CYCTIME*top->v->CYCLES) { + while (main_time < CYCTIME*top->vgen->CYCLES) { top->eval(); main_time += CYCTIME/2; top->clk = !top->clk;