diff --git a/src/verilog.y b/src/verilog.y
index 9ee9888ea..ea9b10d96 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -3786,6 +3786,7 @@ system_f_call_or_t<nodep>:	// IEEE: part of system_tf_call (can be task or func)
 	|	yD_UNSIGNED '(' expr ')'		{ $$ = new AstUnsigned($1, $3); }
 	|	yD_URANDOM '(' expr ')'			{ $$ = new AstRand($1, $3, true); }
 	|	yD_URANDOM parenE			{ $$ = new AstRand($1, nullptr, true); }
+	|	yD_URANDOM_RANGE '(' expr ')'		{ $$ = new AstURandomRange($1, $3, new AstConst($1, 0)); }
 	|	yD_URANDOM_RANGE '(' expr ',' expr ')'	{ $$ = new AstURandomRange($1, $3, $5); }
 	|	yD_VALUEPLUSARGS '(' expr ',' expr ')'	{ $$ = new AstValuePlusArgs($1, $3, $5); }
 	;
diff --git a/test_regress/t/t_urandom.v b/test_regress/t/t_urandom.v
index f20529134..885118ab7 100644
--- a/test_regress/t/t_urandom.v
+++ b/test_regress/t/t_urandom.v
@@ -40,6 +40,8 @@ module t(/*AUTOARG*/);
          if (v1 != 0 && v1 != 1) $stop;
          v1 = $urandom_range(2, 0);
          if (v1 != 0 && v1 != 1) $stop;
+         v1 = $urandom_range(3);
+         if (v1 != 0 && v1 != 1 && v1 != 2) $stop;
       end
 
       // Seed stability