From 6aaef67e7373552661779514813927821f0b96d3 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Wed, 17 Sep 2008 20:58:01 -0400 Subject: [PATCH] Fix test_verilated running under ncsim --- test_regress/t/t_EXAMPLE.v | 5 ++--- test_verilated/Makefile | 4 +++- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/test_regress/t/t_EXAMPLE.v b/test_regress/t/t_EXAMPLE.v index e67a19f5e..dfbaf816b 100644 --- a/test_regress/t/t_EXAMPLE.v +++ b/test_regress/t/t_EXAMPLE.v @@ -43,9 +43,6 @@ module t (/*AUTOARG*/ // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, out}; - // What checksum will we end up with -`define EXPECTED_SUM 64'h4afe43fb79d7b71e - // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE @@ -66,6 +63,8 @@ module t (/*AUTOARG*/ else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h4afe43fb79d7b71e if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; diff --git a/test_verilated/Makefile b/test_verilated/Makefile index 00562c303..7afc40f39 100644 --- a/test_verilated/Makefile +++ b/test_verilated/Makefile @@ -17,6 +17,8 @@ default: test VERILATOR_ROOT := $(shell pwd)/.. export VERILATOR_ROOT +VERILATOR_NCVERILOG ?= ncverilog + # Pick up PERL and other variable settings include $(VERILATOR_ROOT)/include/verilated.mk @@ -93,7 +95,7 @@ nonc: nc: nc_passed.log nc_passed.log: vgen.v sim_main.v - ncverilog +licqueue +define+ncverilog=1 -q vgen.v sim_main.v + $(VERILATOR_NCVERILOG) +licqueue +define+ncverilog=1 -q vgen.v sim_main.v -rm -f nc_passed.log grep -q Finished ncverilog.log && grep Finished ncverilog.log > nc_passed.log