diff --git a/src/V3Premit.cpp b/src/V3Premit.cpp
index 5a2acec92..dae0a03db 100644
--- a/src/V3Premit.cpp
+++ b/src/V3Premit.cpp
@@ -288,6 +288,11 @@ class PremitVisitor final : public VNVisitor {
         iterateChildren(nodep);
         checkNode(nodep);
     }
+    void visit(AstCvtPackedToArray* nodep) override {
+        iterateChildren(nodep);
+        checkNode(nodep);
+        if (!VN_IS(nodep->backp(), NodeAssign)) createWideTemp(nodep);
+    }
     void visit(AstCvtUnpackedToQueue* nodep) override {
         iterateChildren(nodep);
         checkNode(nodep);
@@ -303,13 +308,11 @@ class PremitVisitor final : public VNVisitor {
         checkNode(nodep);
     }
     void visit(AstArraySel* nodep) override {
-        // Skip straight to children. Don't replace the array
-        iterateChildren(nodep->fromp());
+        iterateAndNextNull(nodep->fromp());
         {  // Only the 'from' is part of the assignment LHS
             VL_RESTORER(m_assignLhs);
             m_assignLhs = false;
-            // Index is never wide, so skip straight to children
-            iterateChildren(nodep->bitp());
+            iterateAndNextNull(nodep->bitp());
         }
         // ArraySel are just pointer arithmetic and should never be replaced
     }
diff --git a/src/V3Subst.cpp b/src/V3Subst.cpp
index 049258a17..f5745a277 100644
--- a/src/V3Subst.cpp
+++ b/src/V3Subst.cpp
@@ -120,6 +120,8 @@ public:
         if (!m_varp->isWide() && !m_whole.m_complex && m_whole.m_assignp && !m_wordAssign) {
             const AstNodeAssign* const assp = m_whole.m_assignp;
             UASSERT_OBJ(assp, errp, "Reading whole that was never assigned");
+            // AstCvtPackedToArray can't be anywhere else than on the RHS of assignment
+            if (VN_IS(assp->rhsp(), CvtPackedToArray)) return nullptr;
             return assp->rhsp();
         } else {
             return nullptr;
diff --git a/test_regress/t/t_stream_trace.out b/test_regress/t/t_stream_trace.out
new file mode 100644
index 000000000..3b29c5aa9
--- /dev/null
+++ b/test_regress/t/t_stream_trace.out
@@ -0,0 +1,112 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module top $end
+  $var wire 1 * clk $end
+  $scope module t $end
+   $var wire 1 * clk $end
+   $var wire 32 + cyc [31:0] $end
+   $var wire 3 # cmd_ready [2:0] $end
+   $var wire 1 $ cmd_ready_unpack[0] $end
+   $var wire 1 % cmd_ready_unpack[1] $end
+   $var wire 1 & cmd_ready_unpack[2] $end
+   $var wire 1 ' cmd_ready_o[0] $end
+   $var wire 1 ( cmd_ready_o[1] $end
+   $var wire 1 ) cmd_ready_o[2] $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b101 #
+1$
+0%
+1&
+1'
+0(
+1)
+0*
+b00000000000000000000000000000000 +
+#10
+b110 #
+0$
+1%
+0'
+1(
+1*
+b00000000000000000000000000000001 +
+#15
+b101 #
+1$
+0%
+1'
+0(
+0*
+#20
+b110 #
+0$
+1%
+0'
+1(
+1*
+b00000000000000000000000000000010 +
+#25
+b101 #
+1$
+0%
+1'
+0(
+0*
+#30
+b110 #
+0$
+1%
+0'
+1(
+1*
+b00000000000000000000000000000011 +
+#35
+b101 #
+1$
+0%
+1'
+0(
+0*
+#40
+b110 #
+0$
+1%
+0'
+1(
+1*
+b00000000000000000000000000000100 +
+#45
+b101 #
+1$
+0%
+1'
+0(
+0*
+#50
+b110 #
+0$
+1%
+0'
+1(
+1*
+b00000000000000000000000000000101 +
+#55
+b101 #
+1$
+0%
+1'
+0(
+0*
+#60
+b110 #
+0$
+1%
+0'
+1(
+1*
+b00000000000000000000000000000110 +
diff --git a/test_regress/t/t_stream_trace.py b/test_regress/t/t_stream_trace.py
new file mode 100755
index 000000000..c326fed7b
--- /dev/null
+++ b/test_regress/t/t_stream_trace.py
@@ -0,0 +1,20 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=['--cc --trace-vcd'])
+
+test.execute()
+
+test.vcd_identical(test.trace_filename, test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_stream_trace.v b/test_regress/t/t_stream_trace.v
new file mode 100644
index 000000000..cc6e98cc5
--- /dev/null
+++ b/test_regress/t/t_stream_trace.v
@@ -0,0 +1,26 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (clk);
+   input clk;
+   integer cyc = 0;
+
+   logic [2:0] cmd_ready;
+   logic       cmd_ready_unpack[3];
+   logic       cmd_ready_o[3];
+
+   assign cmd_ready = {1'b1, clk, ~clk};
+   assign cmd_ready_unpack = {<<{cmd_ready}};
+   assign cmd_ready_o = cmd_ready_unpack;
+
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      if (cyc == 5) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+endmodule