From 6965e138aa84a2b3ffc18a26918ef483c6f496d1 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 8 Nov 2020 23:26:58 -0500 Subject: [PATCH] Add clearer unsupported message for inside on array (#2566) --- src/V3Width.cpp | 3 ++ test_regress/t/t_inside_unpack.out | 4 +++ test_regress/t/t_inside_unpack.pl | 23 +++++++++++++ test_regress/t/t_inside_unpack.v | 54 ++++++++++++++++++++++++++++++ 4 files changed, 84 insertions(+) create mode 100644 test_regress/t/t_inside_unpack.out create mode 100755 test_regress/t/t_inside_unpack.pl create mode 100644 test_regress/t/t_inside_unpack.v diff --git a/src/V3Width.cpp b/src/V3Width.cpp index d735de1f4..9719b0988 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -2134,6 +2134,9 @@ private: // Similar logic in V3Case inewp = irangep->newAndFromInside(nodep->exprp(), irangep->lhsp()->unlinkFrBack(), irangep->rhsp()->unlinkFrBack()); + } else if (auto* irangep = VN_CAST(itemp->dtypep(), UnpackArrayDType)) { + irangep->v3error("Unsupported: inside on unpacked array"); + continue; } else { inewp = new AstEqWild(itemp->fileline(), nodep->exprp()->cloneTree(true), itemp->unlinkFrBack()); diff --git a/test_regress/t/t_inside_unpack.out b/test_regress/t/t_inside_unpack.out new file mode 100644 index 000000000..e7037fc4a --- /dev/null +++ b/test_regress/t/t_inside_unpack.out @@ -0,0 +1,4 @@ +%Error: t/t_inside_unpack.v:13:31: Unsupported: inside on unpacked array + 13 | localparam int CHECKLIST_P [2:0] = '{0, 1, 2}; + | ^ +%Error: Exiting due to diff --git a/test_regress/t/t_inside_unpack.pl b/test_regress/t/t_inside_unpack.pl new file mode 100755 index 000000000..40f69d41d --- /dev/null +++ b/test_regress/t/t_inside_unpack.pl @@ -0,0 +1,23 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + fails => $Self->{vlt_all}, + expect_filename => $Self->{golden_filename}, + ); + +execute( + check_finished => 1, + ) if !$Self->{vlt_all}; + +ok(1); +1; diff --git a/test_regress/t/t_inside_unpack.v b/test_regress/t/t_inside_unpack.v new file mode 100644 index 000000000..f15184aa5 --- /dev/null +++ b/test_regress/t/t_inside_unpack.v @@ -0,0 +1,54 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t(/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + localparam int CHECKLIST_P [2:0] = '{0, 1, 2}; + + localparam HIT_LP = 1; + localparam MISS_LP = 4; + localparam HIT_INSIDE = HIT_LP inside {CHECKLIST_P}; + localparam MISS_INSIDE = MISS_LP inside {CHECKLIST_P}; + + initial begin + if (HIT_INSIDE != 1) $stop; + if (MISS_INSIDE != 0) $stop; + end + + integer cyc=0; + + int array [10]; + logic l; + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + // Setup + array[0] = 10; + array[1] = 20; + array[9] = 90; + end + else if (cyc < 99) begin + l = (10 inside {array}); + if (l != 1) $stop; + l = (20 inside {array}); + if (l != 1) $stop; + l = (90 inside {array}); + if (l != 1) $stop; + l = (99 inside {array}); + if (l != 0) $stop; + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule