diff --git a/Changes b/Changes
index 35ece85a1..b91e2f6bc 100644
--- a/Changes
+++ b/Changes
@@ -10,6 +10,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **    Support command-line -G/+pvalue param overrides, bug1045. [Stefan Wallentowitz]
 
+***   Add --l2-name option for controlling "v" naming, bug1050.
+
 
 * Verilator 3.882 2016-03-01
 
diff --git a/bin/verilator b/bin/verilator
index f7f0e2c25..4d912b987 100755
--- a/bin/verilator
+++ b/bin/verilator
@@ -291,6 +291,7 @@ descriptions in the next sections for more information.
     --inline-mult <value>       Tune module inlining
      -LDFLAGS <flags>           Linker pre-object flags for makefile
      -LDLIBS <flags>            Linker library flags for makefile
+    --l2-name <value>           Verilog scope name of the top module
     --language <lang>           Default language standard to parse
      +libext+<ext>+[ext]...     Extensions for finding modules
     --lint-only                 Lint, but do not make output
@@ -785,6 +786,15 @@ called LDLIBS as that's the Makefile variable it controls.  (In Make,
 LDFLAGS is before the first object, LDLIBS after.  -L libraries need to be
 in the Make variable LDLIBS, not LDFLAGS.)
 
+=item --l2-name I<value>
+
+Instead of using the module name when showing Verilog scope, use the name
+provided. Default is "--l2-name v" and is used to standardize some wrapping
+methodologies.
+
+The program "module t; initial $display("= %m"); endmodule" will show by
+default "= t". With "--l2-name v" it will print "= v".
+
 =item --language I<value>
 
 A synonym for C<--default-langauge>, for compatibility with other tools and
diff --git a/src/V3LinkLevel.cpp b/src/V3LinkLevel.cpp
index 6ac4ae6fb..7cea0580d 100644
--- a/src/V3LinkLevel.cpp
+++ b/src/V3LinkLevel.cpp
@@ -113,7 +113,7 @@ void V3LinkLevel::wrapTopCell(AstNetlist* netlistp) {
 
     // Add instance
     AstCell* cellp = new AstCell(newmodp->fileline(),
-				 (v3Global.opt.l2Name() ? "v" : oldmodp->name()),
+				 ((v3Global.opt.l2Name()!="") ? v3Global.opt.l2Name() : oldmodp->name()),
 				 oldmodp->name(),
 				 NULL, NULL, NULL);
     cellp->modp(oldmodp);
diff --git a/src/V3Options.cpp b/src/V3Options.cpp
index 7fdb1730c..844aaa5f2 100644
--- a/src/V3Options.cpp
+++ b/src/V3Options.cpp
@@ -693,7 +693,6 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char
 	    else if ( onoff   (sw, "-exe", flag/*ref*/) )	{ m_exe = flag; }
 	    else if ( onoff   (sw, "-ignc", flag/*ref*/) )	{ m_ignc = flag; }
 	    else if ( onoff   (sw, "-inhibit-sim", flag/*ref*/)){ m_inhibitSim = flag; }
-	    else if ( onoff   (sw, "-l2name", flag/*ref*/) )	{ m_l2Name = flag; }
 	    else if ( onoff   (sw, "-lint-only", flag/*ref*/) )	{ m_lintOnly = flag; }
 	    else if ( !strcmp (sw, "-no-pins64") )		{ m_pinsBv = 33; }
 	    else if ( onoff   (sw, "-order-clock-delay", flag/*ref*/) )	{ m_orderClockDly = flag; }
@@ -813,6 +812,16 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char
 		shift;
 		addLdLibs(argv[i]);
 	    }
+	    else if ( !strcmp (sw, "-l2-name") && (i+1)<argc ) {
+		shift;
+		m_l2Name = argv[i];
+	    }
+	    else if ( !strcmp (sw, "-l2name")) {  // Historical and undocumented
+		m_l2Name = "v";
+	    }
+	    else if ( !strcmp (sw, "-no-l2name")) {  // Historical and undocumented
+		m_l2Name = "";
+	    }
 	    else if ( (!strcmp (sw, "-language") && (i+1)<argc)
 		      || (!strcmp (sw, "-default-language") && (i+1)<argc)) {
 		shift;
@@ -1192,7 +1201,6 @@ V3Options::V3Options() {
     m_exe = false;
     m_ignc = false;
     m_inhibitSim = false;
-    m_l2Name = true;
     m_lintOnly = false;
     m_makeDepend = true;
     m_makePhony = false;
@@ -1242,6 +1250,7 @@ V3Options::V3Options() {
     m_makeDir = "obj_dir";
     m_bin = "";
     m_flags = "";
+    m_l2Name = "v";
     m_unusedRegexp = "*unused*";
     m_xAssign = "fast";
 
diff --git a/src/V3Options.h b/src/V3Options.h
index e18e36265..d5040d564 100644
--- a/src/V3Options.h
+++ b/src/V3Options.h
@@ -78,7 +78,6 @@ class V3Options {
     bool	m_exe;		// main switch: --exe
     bool	m_ignc;		// main switch: --ignc
     bool	m_inhibitSim;	// main switch: --inhibit-sim
-    bool	m_l2Name;	// main switch: --l2name
     bool	m_lintOnly;	// main switch: --lint-only
     bool	m_orderClockDly;// main switch: --order-clock-delay
     bool	m_outFormatOk;	// main switch: --cc, --sc or --sp was specified
@@ -124,6 +123,7 @@ class V3Options {
     string	m_bin;		// main switch: --bin {binary}
     string	m_exeName;	// main switch: -o {name}
     string	m_flags;	// main switch: -f {name}
+    string	m_l2Name;	// main switch: --l2name; "" for top-module's name
     string	m_makeDir;	// main switch: -Mdir
     string	m_modPrefix;	// main switch: --mod-prefix
     string	m_pipeFilter;	// main switch: --pipe-filter
@@ -240,7 +240,6 @@ class V3Options {
     bool pinsUint8() const { return m_pinsUint8; }
     bool profileCFuncs() const { return m_profileCFuncs; }
     bool allPublic() const { return m_public; }
-    bool l2Name() const { return m_l2Name; }
     bool lintOnly() const { return m_lintOnly; }
     bool ignc() const { return m_ignc; }
     bool inhibitSim() const { return m_inhibitSim; }
@@ -267,6 +266,7 @@ class V3Options {
     int    compLimitParens() const { return m_compLimitParens; }
 
     string exeName() const { return m_exeName!="" ? m_exeName : prefix(); }
+    string l2Name() const { return m_l2Name; }
     string makeDir() const { return m_makeDir; }
     string modPrefix() const { return m_modPrefix; }
     string pipeFilter() const { return m_pipeFilter; }
diff --git a/test_regress/t/t_flag_names.pl b/test_regress/t/t_flag_names.pl
new file mode 100755
index 000000000..f5b84d9ba
--- /dev/null
+++ b/test_regress/t/t_flag_names.pl
@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    verilator_flags2 => ["--mod-prefix modPrefix --top-module t --l2-name l2Name"],
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_flag_names.v b/test_regress/t/t_flag_names.v
new file mode 100644
index 000000000..3f9b43bb2
--- /dev/null
+++ b/test_regress/t/t_flag_names.v
@@ -0,0 +1,23 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2016 by Wilson Snyder.
+
+module t;
+   sub sub ();
+endmodule
+
+module sub;
+   string scope;
+   initial begin
+      scope = $sformatf("%m");
+      $write("[%0t] In %s\n", $time, scope);
+`ifdef VERILATOR
+      if (scope != "top.l2Name.sub") $stop;
+`else
+      if (scope != "top.t.sub") $stop;
+`endif
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule