diff --git a/Changes b/Changes
index 6e446b702..a60586559 100644
--- a/Changes
+++ b/Changes
@@ -13,6 +13,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Fix missing VL_SHIFTRS_IQI with WIDTH warning, bug714. [Fabrizio Ferrandi]
 
+****  Fix internal error on "input x =" syntax error, bug716. [Lane Brooks]
+
 
 * Verilator 3.855 2014-01-18
 
diff --git a/src/V3LinkParse.cpp b/src/V3LinkParse.cpp
index 89cb19cfa..f33d42c6c 100644
--- a/src/V3LinkParse.cpp
+++ b/src/V3LinkParse.cpp
@@ -61,6 +61,7 @@ private:
     bool		m_needStart;	// Need start marker on lower AstParse
     AstNodeModule*	m_valueModp;	// If set, move AstVar->valuep() initial values to this module
     AstNodeModule*	m_modp;		// Current module
+    AstNodeFTask*	m_ftaskp;	// Current task
 
     // METHODS
     static int debug() {
@@ -85,6 +86,14 @@ private:
     }
 
     // VISITs
+    virtual void visit(AstNodeFTask* nodep, AstNUser*) {
+	if (!nodep->user1SetOnce()) {  // Process only once.
+	    cleanFileline(nodep);
+	    m_ftaskp = nodep;
+	    nodep->iterateChildren(*this);
+	    m_ftaskp = NULL;
+	}
+    }
     virtual void visit(AstNodeFTaskRef* nodep, AstNUser*) {
 	if (!nodep->user1SetOnce()) {  // Process only once.
 	    cleanFileline(nodep);
@@ -138,7 +147,11 @@ private:
 	    // A variable with an = value can be three things:
 	    FileLine* fl = nodep->valuep()->fileline();
 	    // 1. Parameters and function inputs: It's a default to use if not overridden
-	    if (nodep->isParam() || nodep->isInOnly()) {
+	    if (nodep->isParam() || (m_ftaskp && nodep->isInOnly())) {
+	    }
+	    else if (!m_ftaskp && nodep->isInOnly()) {
+		nodep->v3error("Unsupported: Default value on module input: "<<nodep->prettyName());
+		nodep->valuep()->unlinkFrBack()->deleteTree();
 	    } // 2. Under modules, it's an initial value to be loaded at time 0 via an AstInitial
 	    else if (m_valueModp) {
 		nodep->addNextHere
@@ -313,6 +326,7 @@ public:
     LinkParseVisitor(AstNetlist* rootp) {
 	m_varp = NULL;
 	m_modp = NULL;
+	m_ftaskp = NULL;
 	m_inAlways = false;
 	m_inGenerate = false;
 	m_needStart = false;
diff --git a/test_regress/t/t_lint_input_eq_bad.pl b/test_regress/t/t_lint_input_eq_bad.pl
new file mode 100755
index 000000000..6d78af529
--- /dev/null
+++ b/test_regress/t/t_lint_input_eq_bad.pl
@@ -0,0 +1,24 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+compile (
+    v_flags2 => ["--lint-only"],
+    fails=>1,
+    verilator_make_gcc => 0,
+    make_top_shell => 0,
+    make_main => 0,
+    expect=>
+'%Error: t/t_lint_input_eq_bad.v:\d+: Unsupported: Default value on module input: i2
+%Error: Exiting due to.*',
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_lint_input_eq_bad.v b/test_regress/t/t_lint_input_eq_bad.v
new file mode 100644
index 000000000..809247f12
--- /dev/null
+++ b/test_regress/t/t_lint_input_eq_bad.v
@@ -0,0 +1,12 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2010 by Wilson Snyder.
+
+module t
+   (
+   input wire i,
+   input wire i2 = i   // BAD
+   );
+
+endmodule