diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS index a865eefe5..a789b171a 100644 --- a/docs/CONTRIBUTORS +++ b/docs/CONTRIBUTORS @@ -32,6 +32,7 @@ Bartłomiej Chmiel Brian Li Cameron Kirk Cameron Waite +Charitha Jeewanka Chih-Mao Chen Chris Bachhuber Chris Randall diff --git a/src/V3Gate.cpp b/src/V3Gate.cpp index 182a451c7..89c2f23dc 100644 --- a/src/V3Gate.cpp +++ b/src/V3Gate.cpp @@ -1291,26 +1291,33 @@ void V3Gate::gateAll(AstNetlist* netlistp) { graphp->removeRedundantEdgesSum(&V3GraphEdge::followAlwaysTrue); if (dumpGraphLevel() >= 6) graphp->dumpDotFilePrefixed("gate_simp"); - // Inline variables + // Inline variables (CRITICAL for downstream scheduling) GateInline::apply(*graphp); if (dumpGraphLevel() >= 6) graphp->dumpDotFilePrefixed("gate_inline"); - // Remove redundant logic - if (v3Global.opt.fDedupe()) { - GateDedupe::apply(*graphp); - if (dumpGraphLevel() >= 6) graphp->dumpDotFilePrefixed("gate_dedup"); - } + // --- NON-CRITICAL OPTIMIZATIONS --- + // Only run these aggressive logic reducers if gate optimization is enabled + if (v3Global.opt.fGate()) { - // Merge assignments - if (v3Global.opt.fAssemble()) { - GateMergeAssignments::apply(*graphp); - if (dumpGraphLevel() >= 6) graphp->dumpDotFilePrefixed("gate_merge"); - } + // Remove redundant logic + if (v3Global.opt.fDedupe()) { + GateDedupe::apply(*graphp); + if (dumpGraphLevel() >= 6) graphp->dumpDotFilePrefixed("gate_dedup"); + } - // Remove unused logic - GateUnused::apply(*graphp); - if (dumpGraphLevel() >= 3) graphp->dumpDotFilePrefixed("gate_final"); + // Merge assignments + if (v3Global.opt.fAssemble()) { + GateMergeAssignments::apply(*graphp); + if (dumpGraphLevel() >= 6) graphp->dumpDotFilePrefixed("gate_merge"); + } + + // Remove unused logic + GateUnused::apply(*graphp); + if (dumpGraphLevel() >= 3) graphp->dumpDotFilePrefixed("gate_final"); + + } // End of fGate() check } V3Global::dumpCheckGlobalTree("gate", 0, dumpTreeEitherLevel() >= 3); } + diff --git a/src/Verilator.cpp b/src/Verilator.cpp index 1d8c523f8..112b8e9b4 100644 --- a/src/Verilator.cpp +++ b/src/Verilator.cpp @@ -430,12 +430,13 @@ static void process() { // Gate-based logic elimination; eliminate signals and push constant across cell // boundaries Instant propagation makes lots-o-constant reduction possibilities. - if (v3Global.opt.fGate()) { - V3Gate::gateAll(v3Global.rootp()); - // V3Gate calls constant propagation itself. - } else { - v3info("Command Line disabled gate optimization with -fno-gate. " - "This may cause ordering problems."); + // Always run gateAll to perform critical downstream normalizations + // (like GateInline) even if fGate is false. + V3Gate::gateAll(v3Global.rootp()); + + if (!v3Global.opt.fGate()) { + v3info("Command Line disabled gate optimization with -fno-gate. " + "Only critical normalizations will be performed."); } // Combine COVERINCs with duplicate terms