From b28fde7e57a565224ea9bcf1b3ba9bbf95aa5c8a Mon Sep 17 00:00:00 2001 From: wsxarcher Date: Mon, 23 Mar 2026 00:48:44 +0100 Subject: [PATCH 01/13] Handle correctly --- include/verilated.cpp | 14 ++++ include/verilated.h | 16 ++++ include/verilated_fst_c.cpp | 3 +- include/verilated_saif_c.cpp | 3 +- include/verilated_trace.h | 74 ++++++++++++++++++- include/verilated_trace_imp.h | 29 ++------ include/verilated_vcd_c.cpp | 3 +- src/V3AstNodeStmt.h | 7 +- src/V3Begin.cpp | 6 ++ src/V3EmitCFunc.h | 59 ++++++++++++++- src/V3EmitCSyms.cpp | 4 + src/V3LinkDot.cpp | 52 +++++++++++++ src/V3LinkResolve.cpp | 8 ++ src/V3ParseGrammar.cpp | 7 ++ src/V3ParseGrammar.h | 2 + src/V3Task.cpp | 23 ++++++ src/V3Width.cpp | 9 ++- src/verilog.y | 2 +- test_regress/t/t_trace_dumpvars.out | 28 +++++++ test_regress/t/t_trace_dumpvars.py | 20 +++++ test_regress/t/t_trace_dumpvars.v | 38 ++++++++++ test_regress/t/t_trace_dumpvars_abs_scope.out | 29 ++++++++ test_regress/t/t_trace_dumpvars_abs_scope.py | 20 +++++ test_regress/t/t_trace_dumpvars_abs_scope.v | 50 +++++++++++++ test_regress/t/t_trace_dumpvars_add_module.py | 21 ++++++ test_regress/t/t_trace_dumpvars_add_module.v | 58 +++++++++++++++ .../t/t_trace_dumpvars_add_module_0.out | 26 +++++++ .../t/t_trace_dumpvars_add_module_1.out | 53 +++++++++++++ test_regress/t/t_trace_dumpvars_func.out | 29 ++++++++ test_regress/t/t_trace_dumpvars_func.py | 20 +++++ test_regress/t/t_trace_dumpvars_func.v | 61 +++++++++++++++ .../t/t_trace_dumpvars_hier_scope.out | 24 ++++++ test_regress/t/t_trace_dumpvars_hier_scope.py | 20 +++++ test_regress/t/t_trace_dumpvars_hier_scope.v | 50 +++++++++++++ test_regress/t/t_trace_dumpvars_level.out | 22 ++++++ test_regress/t/t_trace_dumpvars_level.py | 20 +++++ test_regress/t/t_trace_dumpvars_level.v | 50 +++++++++++++ .../t/t_trace_dumpvars_level_scope.out | 24 ++++++ .../t/t_trace_dumpvars_level_scope.py | 20 +++++ test_regress/t/t_trace_dumpvars_level_scope.v | 50 +++++++++++++ .../t/t_trace_dumpvars_missing_scope.out | 15 ++++ .../t/t_trace_dumpvars_missing_scope.py | 21 ++++++ .../t/t_trace_dumpvars_missing_scope.v | 50 +++++++++++++ .../t/t_trace_dumpvars_multi_scope.out | 27 +++++++ .../t/t_trace_dumpvars_multi_scope.py | 20 +++++ test_regress/t/t_trace_dumpvars_multi_scope.v | 50 +++++++++++++ .../t/t_trace_dumpvars_nonconst_scope.out | 31 ++++++++ .../t/t_trace_dumpvars_nonconst_scope.py | 20 +++++ .../t/t_trace_dumpvars_nonconst_scope.v | 52 +++++++++++++ test_regress/t/t_trace_dumpvars_override.out | 42 +++++++++++ test_regress/t/t_trace_dumpvars_override.py | 20 +++++ test_regress/t/t_trace_dumpvars_override.v | 51 +++++++++++++ test_regress/t/t_trace_dumpvars_scope.out | 29 ++++++++ test_regress/t/t_trace_dumpvars_scope.py | 20 +++++ test_regress/t/t_trace_dumpvars_scope.v | 50 +++++++++++++ test_regress/t/t_trace_dumpvars_struct.out | 36 +++++++++ test_regress/t/t_trace_dumpvars_struct.py | 20 +++++ test_regress/t/t_trace_dumpvars_struct.v | 57 ++++++++++++++ test_regress/t/t_trace_dumpvars_sub.out | 29 ++++++++ test_regress/t/t_trace_dumpvars_sub.py | 20 +++++ test_regress/t/t_trace_dumpvars_sub.v | 54 ++++++++++++++ test_regress/t/t_trace_dumpvars_sub0.out | 39 ++++++++++ test_regress/t/t_trace_dumpvars_sub0.py | 20 +++++ test_regress/t/t_trace_dumpvars_sub0.v | 54 ++++++++++++++ test_regress/t/t_trace_dumpvars_task.out | 29 ++++++++ test_regress/t/t_trace_dumpvars_task.py | 20 +++++ test_regress/t/t_trace_dumpvars_task.v | 61 +++++++++++++++ test_regress/t/t_trace_dumpvars_task2.out | 29 ++++++++ test_regress/t/t_trace_dumpvars_task2.py | 20 +++++ test_regress/t/t_trace_dumpvars_task2.v | 65 ++++++++++++++++ test_regress/t/t_trace_dumpvars_wire.out | 18 +++++ test_regress/t/t_trace_dumpvars_wire.py | 20 +++++ test_regress/t/t_trace_dumpvars_wire.v | 41 ++++++++++ 73 files changed, 2150 insertions(+), 34 deletions(-) create mode 100644 test_regress/t/t_trace_dumpvars.out create mode 100644 test_regress/t/t_trace_dumpvars.py create mode 100644 test_regress/t/t_trace_dumpvars.v create mode 100644 test_regress/t/t_trace_dumpvars_abs_scope.out create mode 100644 test_regress/t/t_trace_dumpvars_abs_scope.py create mode 100644 test_regress/t/t_trace_dumpvars_abs_scope.v create mode 100644 test_regress/t/t_trace_dumpvars_add_module.py create mode 100644 test_regress/t/t_trace_dumpvars_add_module.v create mode 100644 test_regress/t/t_trace_dumpvars_add_module_0.out create mode 100644 test_regress/t/t_trace_dumpvars_add_module_1.out create mode 100644 test_regress/t/t_trace_dumpvars_func.out create mode 100644 test_regress/t/t_trace_dumpvars_func.py create mode 100644 test_regress/t/t_trace_dumpvars_func.v create mode 100644 test_regress/t/t_trace_dumpvars_hier_scope.out create mode 100644 test_regress/t/t_trace_dumpvars_hier_scope.py create mode 100644 test_regress/t/t_trace_dumpvars_hier_scope.v create mode 100644 test_regress/t/t_trace_dumpvars_level.out create mode 100644 test_regress/t/t_trace_dumpvars_level.py create mode 100644 test_regress/t/t_trace_dumpvars_level.v create mode 100644 test_regress/t/t_trace_dumpvars_level_scope.out create mode 100644 test_regress/t/t_trace_dumpvars_level_scope.py create mode 100644 test_regress/t/t_trace_dumpvars_level_scope.v create mode 100644 test_regress/t/t_trace_dumpvars_missing_scope.out create mode 100644 test_regress/t/t_trace_dumpvars_missing_scope.py create mode 100644 test_regress/t/t_trace_dumpvars_missing_scope.v create mode 100644 test_regress/t/t_trace_dumpvars_multi_scope.out create mode 100644 test_regress/t/t_trace_dumpvars_multi_scope.py create mode 100644 test_regress/t/t_trace_dumpvars_multi_scope.v create mode 100644 test_regress/t/t_trace_dumpvars_nonconst_scope.out create mode 100644 test_regress/t/t_trace_dumpvars_nonconst_scope.py create mode 100644 test_regress/t/t_trace_dumpvars_nonconst_scope.v create mode 100644 test_regress/t/t_trace_dumpvars_override.out create mode 100644 test_regress/t/t_trace_dumpvars_override.py create mode 100644 test_regress/t/t_trace_dumpvars_override.v create mode 100644 test_regress/t/t_trace_dumpvars_scope.out create mode 100644 test_regress/t/t_trace_dumpvars_scope.py create mode 100644 test_regress/t/t_trace_dumpvars_scope.v create mode 100644 test_regress/t/t_trace_dumpvars_struct.out create mode 100644 test_regress/t/t_trace_dumpvars_struct.py create mode 100644 test_regress/t/t_trace_dumpvars_struct.v create mode 100644 test_regress/t/t_trace_dumpvars_sub.out create mode 100644 test_regress/t/t_trace_dumpvars_sub.py create mode 100644 test_regress/t/t_trace_dumpvars_sub.v create mode 100644 test_regress/t/t_trace_dumpvars_sub0.out create mode 100644 test_regress/t/t_trace_dumpvars_sub0.py create mode 100644 test_regress/t/t_trace_dumpvars_sub0.v create mode 100644 test_regress/t/t_trace_dumpvars_task.out create mode 100644 test_regress/t/t_trace_dumpvars_task.py create mode 100644 test_regress/t/t_trace_dumpvars_task.v create mode 100644 test_regress/t/t_trace_dumpvars_task2.out create mode 100644 test_regress/t/t_trace_dumpvars_task2.py create mode 100644 test_regress/t/t_trace_dumpvars_task2.v create mode 100644 test_regress/t/t_trace_dumpvars_wire.out create mode 100644 test_regress/t/t_trace_dumpvars_wire.py create mode 100644 test_regress/t/t_trace_dumpvars_wire.v diff --git a/include/verilated.cpp b/include/verilated.cpp index 158cdbac3..1f7987af6 100644 --- a/include/verilated.cpp +++ b/include/verilated.cpp @@ -2926,6 +2926,20 @@ std::string VerilatedContext::dumpfileCheck() const VL_MT_SAFE_EXCLUDES(m_timeDu } return out; } +void VerilatedContext::dumpvarsAdd(int level, + const std::string& hier) VL_MT_SAFE_EXCLUDES(m_timeDumpMutex) { + const VerilatedLockGuard lock{m_timeDumpMutex}; + if (level == 0 && hier.empty()) { + m_dumpvars.clear(); + } else { + m_dumpvars.emplace_back(level, hier); + } +} +std::vector +VerilatedContext::dumpvars() const VL_MT_SAFE_EXCLUDES(m_timeDumpMutex) { + const VerilatedLockGuard lock{m_timeDumpMutex}; + return m_dumpvars; +} void VerilatedContext::errorCount(int val) VL_MT_SAFE { const VerilatedLockGuard lock{m_mutex}; m_s.m_errorCount = val; diff --git a/include/verilated.h b/include/verilated.h index 909956d82..a7cd7d734 100644 --- a/include/verilated.h +++ b/include/verilated.h @@ -110,6 +110,15 @@ class VerilatedVcd; class VerilatedVcdC; class VerilatedVcdSc; +struct VerilatedTraceDumpvarsEntry final { + int m_level; + std::string m_hier; + + VerilatedTraceDumpvarsEntry(int level, const std::string& hier) + : m_level{level} + , m_hier{hier} {} +}; + //========================================================================= // Basic types @@ -404,6 +413,8 @@ protected: mutable VerilatedMutex m_timeDumpMutex; // Protect misc slow strings std::string m_timeFormatSuffix VL_GUARDED_BY(m_timeDumpMutex); // $timeformat printf format std::string m_dumpfile VL_GUARDED_BY(m_timeDumpMutex); // $dumpfile setting + std::vector + m_dumpvars VL_GUARDED_BY(m_timeDumpMutex); // $dumpvars settings struct NonSerialized final { // Non-serialized information // These are reloaded from on command-line settings, so do not need to persist @@ -656,6 +667,11 @@ public: void dumpfile(const std::string& flag) VL_MT_SAFE_EXCLUDES(m_timeDumpMutex); std::string dumpfileCheck() const VL_MT_SAFE_EXCLUDES(m_timeDumpMutex); + // Internal: $dumpvars + void dumpvarsAdd(int level, const std::string& hier) VL_MT_SAFE_EXCLUDES(m_timeDumpMutex); + std::vector dumpvars() const + VL_MT_SAFE_EXCLUDES(m_timeDumpMutex); + // Internal: --prof-exec related settings uint64_t profExecStart() const VL_MT_SAFE { return m_ns.m_profExecStart; } void profExecStart(uint64_t flag) VL_MT_SAFE; diff --git a/include/verilated_fst_c.cpp b/include/verilated_fst_c.cpp index a0f636dc4..c47dc93ca 100644 --- a/include/verilated_fst_c.cpp +++ b/include/verilated_fst_c.cpp @@ -220,8 +220,9 @@ void VerilatedFst::declare(uint32_t code, const char* name, int dtypenum, const int bits = ((msb > lsb) ? (msb - lsb) : (lsb - msb)) + 1; const std::string hierarchicalName = m_prefixStack.back().first + name; + const auto dumpvarsPath = Super::dumpvarsPath(m_prefixStack, name); - const bool enabled = Super::declCode(code, hierarchicalName, bits); + const bool enabled = Super::declCode(code, dumpvarsPath, bits); if (!enabled) return; assert(hierarchicalName.rfind(' ') != std::string::npos); diff --git a/include/verilated_saif_c.cpp b/include/verilated_saif_c.cpp index abff785ce..09e2df1df 100644 --- a/include/verilated_saif_c.cpp +++ b/include/verilated_saif_c.cpp @@ -539,8 +539,9 @@ void VerilatedSaif::declare(const uint32_t code, uint32_t fidx, const char* name const int bits = ((msb > lsb) ? (msb - lsb) : (lsb - msb)) + 1; const std::string hierarchicalName = m_prefixStack.back().first + name; + const auto dumpvarsPath = Super::dumpvarsPath(m_prefixStack, name); - if (!Super::declCode(code, hierarchicalName, bits)) return; + if (!Super::declCode(code, dumpvarsPath, bits)) return; std::string variableName = lastWord(hierarchicalName); m_currentScope->addActivityVar(code, variableName); diff --git a/include/verilated_trace.h b/include/verilated_trace.h index 15e3cd964..c107a76cc 100644 --- a/include/verilated_trace.h +++ b/include/verilated_trace.h @@ -313,7 +313,7 @@ private: uint32_t m_maxBits = 0; // Number of bits in the widest signal void* m_initUserp = nullptr; // The callback userp of the instance currently being initialized // TODO: Should keep this as a Trie, that is how it's accessed all the time. - std::vector> m_dumpvars; // dumpvar() entries + std::vector m_dumpvars; // dumpvar() entries double m_timeRes = 1e-9; // Time resolution (ns/ms etc) double m_timeUnit = 1e-0; // Time units (ns/ms etc) uint64_t m_timeLastDump = 0; // Last time we did a dump @@ -371,6 +371,59 @@ private: VL_UNCOPYABLE(VerilatedTrace); protected: + struct DumpvarsPath final { + std::string m_name; + std::vector m_scopeEndps; + + static bool countsAsScopeLevel(VerilatedTracePrefixType type) { + return type == VerilatedTracePrefixType::SCOPE_MODULE + || type == VerilatedTracePrefixType::SCOPE_INTERFACE + || type == VerilatedTracePrefixType::ROOTIO_WRAPPER; + } + + static char separator(VerilatedTracePrefixType type) { + return (type == VerilatedTracePrefixType::ARRAY_PACKED + || type == VerilatedTracePrefixType::ARRAY_UNPACKED) + ? '\0' + : '.'; + } + + static std::string trimPrefix(const std::string& prefix) { + if (!prefix.empty() && prefix.back() == ' ') { + return prefix.substr(0, prefix.size() - 1); + } + return prefix; + } + + void append(const std::string& piece, VerilatedTracePrefixType type, + bool countLevel = true) { + if (piece.empty()) return; + const char sep = separator(type); + if (sep && !m_name.empty()) m_name += sep; + m_name += piece; + if (countLevel && countsAsScopeLevel(type)) m_scopeEndps.push_back(m_name.size()); + } + + bool matchesPrefix(const std::string& prefix) const { + if (prefix.empty()) return true; + if (m_name.compare(0, prefix.size(), prefix) != 0) return false; + return prefix.size() >= m_name.size() || m_name[prefix.size()] == '.'; + } + + int scopeLevelsBelow(size_t prefixLen) const { + int levels = 0; + for (const size_t endp : m_scopeEndps) { + if (endp > prefixLen) ++levels; + } + return levels; + } + + bool matches(const VerilatedTraceDumpvarsEntry& entry) const { + if (!matchesPrefix(entry.m_hier)) return false; + return entry.m_level <= 0 || scopeLevelsBelow(entry.m_hier.size()) < entry.m_level; + } + }; + //========================================================================= // Internals available to format-specific implementations @@ -390,7 +443,7 @@ protected: void traceInit() VL_MT_UNSAFE; // Declare new signal and return true if enabled - bool declCode(uint32_t code, const std::string& declName, uint32_t bits); + bool declCode(uint32_t code, const DumpvarsPath& path, uint32_t bits); void closeBase(); void flushBase(); @@ -405,6 +458,23 @@ protected: return str.substr(idx + 1); } + static DumpvarsPath dumpvarsPath( + const std::vector>& prefixStack, + const char* namep) { + DumpvarsPath out; + std::string prev; + for (size_t i = 1; i < prefixStack.size(); ++i) { + const std::string curr = DumpvarsPath::trimPrefix(prefixStack[i].first); + if (curr.size() < prev.size()) continue; + std::string piece = curr.substr(prev.size()); + if (!piece.empty() && piece.front() == ' ') piece.erase(0, 1); + out.append(piece, prefixStack[i].second); + prev = curr; + } + out.append(namep ? namep : "", prefixStack.back().second, false); + return out; + } + //========================================================================= // Virtual functions to be provided by the format-specific implementation diff --git a/include/verilated_trace_imp.h b/include/verilated_trace_imp.h index 635e3e897..758d97dfa 100644 --- a/include/verilated_trace_imp.h +++ b/include/verilated_trace_imp.h @@ -369,7 +369,8 @@ void VerilatedTrace::traceInit() VL_MT_UNSAFE { } template <> -bool VerilatedTrace::declCode(uint32_t code, const std::string& declName, +bool VerilatedTrace::declCode(uint32_t code, + const DumpvarsPath& path, uint32_t bits) { if (VL_UNCOVERABLE(!code)) { VL_FATAL_MT(__FILE__, __LINE__, "", "Internal: internal trace problem, code 0 is illegal"); @@ -377,21 +378,8 @@ bool VerilatedTrace::declCode(uint32_t code, const std::stri // To keep it simple, this is O(enables * signals), but we expect few enables bool enabled = false; if (m_dumpvars.empty()) enabled = true; - for (const auto& item : m_dumpvars) { - const int dumpvarsLevel = item.first; - const char* dvp = item.second.c_str(); - const char* np = declName.c_str(); - while (*dvp && *dvp == *np) { - ++dvp; - ++np; - } - if (*dvp) continue; // Didn't match dumpvar item - if (*np && *np != ' ') continue; // e.g. "t" isn't a match for "top" - int levels = 0; - while (*np) { - if (*np++ == ' ') ++levels; - } - if (levels > dumpvarsLevel) continue; // Too deep + for (const auto& entry : m_dumpvars) { + if (!path.matches(entry)) continue; // We only need to set first code word if it's a multicode signal // as that's all we'll check for later if (m_sigs_enabledVec.size() <= code) m_sigs_enabledVec.resize((code + 1024) * 2); @@ -434,15 +422,10 @@ void VerilatedTrace::set_time_resolution(const std::string& } template <> void VerilatedTrace::dumpvars(int level, const std::string& hier) VL_MT_SAFE { - if (level == 0) { + if (level == 0 && hier.empty()) { m_dumpvars.clear(); // empty = everything on } else { - // Convert Verilog . separators to trace space separators - std::string hierSpaced = hier; - for (auto& i : hierSpaced) { - if (i == '.') i = ' '; - } - m_dumpvars.emplace_back(level, hierSpaced); + m_dumpvars.emplace_back(level, hier); } } diff --git a/include/verilated_vcd_c.cpp b/include/verilated_vcd_c.cpp index d36cb85da..d3086afe3 100644 --- a/include/verilated_vcd_c.cpp +++ b/include/verilated_vcd_c.cpp @@ -383,8 +383,9 @@ void VerilatedVcd::declare(uint32_t code, const char* name, const char* wirep, b const int bits = ((msb > lsb) ? (msb - lsb) : (lsb - msb)) + 1; const std::string hierarchicalName = m_prefixStack.back().first + name; + const auto dumpvarsPath = Super::dumpvarsPath(m_prefixStack, name); - const bool enabled = Super::declCode(code, hierarchicalName, bits); + const bool enabled = Super::declCode(code, dumpvarsPath, bits); if (m_suffixes.size() <= nextCode() * VL_TRACE_SUFFIX_ENTRY_SIZE) { m_suffixes.resize(nextCode() * VL_TRACE_SUFFIX_ENTRY_SIZE * 2, 0); diff --git a/src/V3AstNodeStmt.h b/src/V3AstNodeStmt.h index 76f32b64a..d5eb0b884 100644 --- a/src/V3AstNodeStmt.h +++ b/src/V3AstNodeStmt.h @@ -636,6 +636,8 @@ class AstDumpCtl final : public AstNodeStmt { // $dumpon etc // Parents: expr // @astgen op1 := exprp : Optional[AstNodeExpr] // Expression based on type of statement + // @astgen op2 := scopeNamep : Optional[AstScopeName] // Scope of the $dumpvars call site + // @astgen op3 := targetsp : List[AstNode] // Optional scope/signal targets for $dumpvars const VDumpCtlType m_ctlType; // Type of operation public: AstDumpCtl(FileLine* fl, VDumpCtlType ctlType, AstNodeExpr* exprp = nullptr) @@ -649,8 +651,9 @@ public: bool isOutputter() override { return true; } bool isPredictOptimizable() const override { return false; } bool isPure() override { return false; } - virtual bool cleanOut() const { return true; } - bool sameNode(const AstNode* /*samep*/) const override { return true; } + bool sameNode(const AstNode* samep) const override { + return ctlType() == VN_DBG_AS(samep, DumpCtl)->ctlType(); + } VDumpCtlType ctlType() const { return m_ctlType; } }; class AstEventControl final : public AstNodeStmt { diff --git a/src/V3Begin.cpp b/src/V3Begin.cpp index b1b02ca0a..b5dd82aad 100644 --- a/src/V3Begin.cpp +++ b/src/V3Begin.cpp @@ -377,6 +377,12 @@ class BeginVisitor final : public VNVisitor { // If there's a %m in the display text, we add a special node that will contain the name() // Similar code in V3Inline if (nodep->user1SetOnce()) return; // Don't double-add text's + // $dumpvars scope names resolve relative to the enclosing module, + // not the block, so don't add block scope components for them. + if (VN_IS(nodep->backp(), DumpCtl)) { + iterateChildren(nodep); + return; + } // DPI svGetScope doesn't include function name, but %m does const std::string scname = nodep->forFormat() ? m_displayScope : m_namedScope; // To keep correct visual order, must add before exising diff --git a/src/V3EmitCFunc.h b/src/V3EmitCFunc.h index aeab8fe8e..05272ee74 100644 --- a/src/V3EmitCFunc.h +++ b/src/V3EmitCFunc.h @@ -895,6 +895,62 @@ public: if (nodep->addNewline()) text += "\n"; displayNode(nodep, nodep->fmtp(), text, nodep->fmtp()->exprsp(), false); } + static bool dumpvarsHasScopePrefix(const string& target, const string& scope) { + return target == scope + || (target.length() > scope.length() && target.compare(0, scope.length(), scope) == 0 + && target[scope.length()] == '.'); + } + + static string dumpvarsHierPath(const string& scope, const string& target) { + if (target.empty()) return scope; + if (scope.empty() || dumpvarsHasScopePrefix(target, scope)) return target; + return scope + "." + target; + } + + // Emit C++ code that registers a $dumpvars filter at runtime. + // Builds the full hierarchy path from vlSymsp->name() and the given suffix, + // then calls dumpvarsAdd with the specified level expression. + void emitDumpVarsAdd(const AstDumpCtl* nodep, const string& hierPath, + const string& levelExpr) { + putns(nodep, "{ std::string __vlDvHier{vlSymsp->name()};\n"); + if (!hierPath.empty()) { + puts("if (!__vlDvHier.empty()) __vlDvHier += '.';\n"); + puts("__vlDvHier += \""); + puts(V3OutFormatter::quoteNameControls(hierPath)); + puts("\";\n"); + } + puts("vlSymsp->_vm_contextp__->dumpvarsAdd("); + puts(levelExpr); + puts(", __vlDvHier); }\n"); + } + // Emit $dumpvars filter logic when scope info is available. + void emitDumpVarsWithScope(AstDumpCtl* nodep) { + UASSERT_OBJ(nodep->scopeNamep(), nodep, "$dumpvars missing AstScopeName"); + const string scope = nodep->scopeNamep()->scopePrettySymName(); + // Resolve the level expression (constant or runtime) + const AstConst* const levelp = VN_CAST(nodep->exprp(), Const); + string levelExpr; + if (levelp) { + levelExpr = cvtToStr(levelp->toUInt()); + } else { + putns(nodep, "{ const int __vlDvLevel = "); + iterateConst(nodep->exprp()); + puts(";\n"); + levelExpr = "__vlDvLevel"; + } + // Emit one dumpvarsAdd call per target, or one for the scope itself + if (nodep->targetsp()) { + for (AstNode* tp = nodep->targetsp(); tp; tp = tp->nextp()) { + const string target = VN_AS(tp, Text)->text(); + emitDumpVarsAdd(nodep, dumpvarsHierPath(scope, target), levelExpr); + } + } else { + emitDumpVarsAdd(nodep, scope, levelExpr); + } + if (!levelp) puts("}\n"); + putns(nodep, "vlSymsp->_traceDumpClose();\n"); + putns(nodep, "vlSymsp->_traceDumpOpen();\n"); + } void visit(AstDumpCtl* nodep) override { switch (nodep->ctlType()) { case VDumpCtlType::FILE: @@ -903,9 +959,8 @@ public: puts(");\n"); break; case VDumpCtlType::VARS: - // We ignore number of levels to dump in exprp() if (v3Global.opt.trace()) { - putns(nodep, "vlSymsp->_traceDumpOpen();\n"); + emitDumpVarsWithScope(nodep); } else { putns(nodep, "VL_PRINTF_MT(\"-Info: "); puts(V3OutFormatter::quoteNameControls(protect(nodep->fileline()->filename()))); diff --git a/src/V3EmitCSyms.cpp b/src/V3EmitCSyms.cpp index 58bc6c621..e4e014208 100644 --- a/src/V3EmitCSyms.cpp +++ b/src/V3EmitCSyms.cpp @@ -1215,6 +1215,10 @@ void EmitCSyms::emitSymImp(const AstNetlist* netlistp) { puts("const VerilatedLockGuard lock{__Vm_dumperMutex};\n"); puts("if (VL_UNLIKELY(!__Vm_dumperp)) {\n"); puts("__Vm_dumperp = new " + v3Global.opt.traceClassLang() + "();\n"); + puts("const auto dvars = _vm_contextp__->dumpvars();\n"); + puts("for (const auto& dv : dvars) {\n"); + puts("__Vm_dumperp->dumpvars(dv.m_level, dv.m_hier);\n"); + puts("}\n"); puts("__Vm_modelp->trace(__Vm_dumperp, 0, 0);\n"); puts("const std::string dumpfile = _vm_contextp__->dumpfileCheck();\n"); puts("__Vm_dumperp->open(dumpfile.c_str());\n"); diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index 9a39a4afd..629fd074a 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -80,6 +80,27 @@ VL_DEFINE_DEBUG_FUNCTIONS; +static string dumpvarsTargetText(const AstNode* nodep) { + if (!nodep) return ""; + if (const AstText* const textp = VN_CAST(nodep, Text)) return textp->text(); + if (const AstCellRef* const refp = VN_CAST(nodep, CellRef)) return refp->name(); + if (const AstCellArrayRef* const refp = VN_CAST(nodep, CellArrayRef)) return refp->name(); + if (const AstParseRef* const refp = VN_CAST(nodep, ParseRef)) return refp->prettyName(); + if (const AstVarRef* const refp = VN_CAST(nodep, VarRef)) return refp->name(); + if (const AstVarXRef* const refp = VN_CAST(nodep, VarXRef)) { + if (refp->dotted().empty()) return refp->name(); + return refp->dotted() + "." + refp->name(); + } + if (const AstDot* const dotp = VN_CAST(nodep, Dot)) { + const string lhs = dumpvarsTargetText(dotp->lhsp()); + const string rhs = dumpvarsTargetText(dotp->rhsp()); + if (lhs.empty()) return rhs; + if (rhs.empty()) return lhs; + return lhs + "." + rhs; + } + return nodep->prettyName(); +} + static string extractDottedPath(AstNode* nodep, bool& hasPartSelect) { if (AstParseRef* const refp = VN_CAST(nodep, ParseRef)) { return refp->name(); @@ -6029,6 +6050,37 @@ class LinkDotResolveVisitor final : public VNVisitor { UINFO(5, indent() << "visit " << nodep); iterateChildren(nodep); } + void visit(AstDumpCtl* nodep) override { + LINKDOT_VISIT_START(); + UINFO(5, indent() << "visit " << nodep); + if (nodep->exprp()) iterateAndNextNull(nodep->exprp()); + AstNode* targetsp = nodep->targetsp(); + if (!targetsp) return; + // Resolve each target from its parse-tree form (AstParseRef/AstDot) + // into a plain text name, validating it against the symbol table. + VNRelinker relinker; + targetsp->unlinkFrBackWithNext(&relinker); + AstNode* newTargetsp = nullptr; + for (AstNode* targetp = targetsp; targetp;) { + AstNode* const nextp = targetp->nextp(); + if (nextp) nextp->unlinkFrBackWithNext(); + const string target = dumpvarsTargetText(targetp); + if (!target.empty() && m_curSymp) { + string baddot; + VSymEnt* matchSymp = nullptr; + if (!m_statep->findDotted(nodep->fileline(), m_curSymp, target, + baddot, matchSymp, true)) { + UINFO(5, "$dumpvars target '" << target + << "' not found in hierarchy" << endl); + } + } + VL_DO_DANGLING(pushDeletep(targetp), targetp); + newTargetsp + = AstNode::addNextNull(newTargetsp, new AstText{nodep->fileline(), target}); + targetp = nextp; + } + relinker.relink(newTargetsp); + } void visit(AstCellArrayRef* nodep) override { LINKDOT_VISIT_START(); UINFO(5, indent() << "visit " << nodep); diff --git a/src/V3LinkResolve.cpp b/src/V3LinkResolve.cpp index 3690fdb39..09c5475eb 100644 --- a/src/V3LinkResolve.cpp +++ b/src/V3LinkResolve.cpp @@ -461,6 +461,14 @@ class LinkResolveVisitor final : public VNVisitor { } } + void visit(AstDumpCtl* nodep) override { + if (nodep->ctlType() == VDumpCtlType::VARS && !nodep->scopeNamep()) { + // Attach AstScopeName so V3Scope/V3Inline build the call-site scope path + nodep->scopeNamep(new AstScopeName{nodep->fileline(), false}); + } + iterateChildren(nodep); + } + void visit(AstUdpTable* nodep) override { UINFO(5, "UDPTABLE " << nodep); if (!v3Global.opt.bboxUnsup()) { diff --git a/src/V3ParseGrammar.cpp b/src/V3ParseGrammar.cpp index fdc0e218b..5ba13aba5 100644 --- a/src/V3ParseGrammar.cpp +++ b/src/V3ParseGrammar.cpp @@ -96,6 +96,13 @@ AstArg* V3ParseGrammar::argWrapList(AstNodeExpr* nodep) { return outp; } +AstDumpCtl* V3ParseGrammar::createDumpVarsScoped(FileLine* fl, AstNodeExpr* levelp, + AstNode* exprListp) { + AstDumpCtl* const resultp = new AstDumpCtl{fl, VDumpCtlType::VARS, levelp}; + resultp->addTargetsp(exprListp); + return resultp; +} + AstAssignW* V3ParseGrammar::createSupplyExpr(FileLine* fileline, const string& name, int value) { AstAssignW* assignp = new AstAssignW{fileline, new AstParseRef{fileline, name}, value ? new AstConst{fileline, AstConst::All1{}} diff --git a/src/V3ParseGrammar.h b/src/V3ParseGrammar.h index 276ed2ffb..5f4f28b86 100644 --- a/src/V3ParseGrammar.h +++ b/src/V3ParseGrammar.h @@ -67,6 +67,8 @@ public: // METHODS AstArg* argWrapList(AstNodeExpr* nodep) VL_MT_DISABLED; + AstDumpCtl* createDumpVarsScoped(FileLine* fl, AstNodeExpr* levelp, + AstNode* exprListp) VL_MT_DISABLED; bool allTracingOn(const FileLine* fl) const { return v3Global.opt.trace() && m_tracingParse && fl->tracingOn(); } diff --git a/src/V3Task.cpp b/src/V3Task.cpp index f92d11c5b..32ae1ee83 100644 --- a/src/V3Task.cpp +++ b/src/V3Task.cpp @@ -1598,6 +1598,29 @@ class TaskVisitor final : public VNVisitor { beginp = createInlinedFTask(nodep, namePrefix, outvscp); ++m_statInlines; } + // When a function call has inlinedDots (from V3Inline's cell hierarchy), + // propagate that info to: + // 1. Any AstDumpCtl/AstScopeName in the inlined body (direct $dumpvars) + // 2. Any nested AstNodeFTaskRef in the inlined body (indirect $dumpvars) + if (!nodep->inlinedDots().empty()) { + const string& callerDots = nodep->inlinedDots(); + string dots = callerDots; + string::size_type pos; + while ((pos = dots.find('.')) != string::npos) dots.replace(pos, 1, "__DOT__"); + const string scopePath = "__DOT__"s + m_scopep->name() + "__DOT__" + dots; + beginp->foreachAndNext([&](AstDumpCtl* dcp) { + if (AstScopeName* const snp = dcp->scopeNamep()) { + snp->scopeAttr(scopePath); + snp->scopeEntr(scopePath); + } + }); + // Propagate inlinedDots to nested task references + beginp->foreachAndNext([&](AstNodeFTaskRef* refp) { + if (refp->inlinedDots().empty()) { + refp->inlinedDots(callerDots); + } + }); + } if (VN_IS(nodep, New)) { // New not legal as while() condition insertBeforeStmt(nodep, beginp); diff --git a/src/V3Width.cpp b/src/V3Width.cpp index eec39fe8a..8545842fb 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -6202,7 +6202,14 @@ class WidthVisitor final : public VNVisitor { } void visit(AstDumpCtl* nodep) override { assertAtStatement(nodep); - if (nodep->exprp()) iterateCheckString(nodep, "LHS", nodep->exprp(), BOTH); + if (nodep->exprp()) { + if (nodep->ctlType() == VDumpCtlType::VARS) { + // $dumpvars level argument is an integer + userIterateAndNext(nodep->exprp(), WidthVP{SELF, BOTH}.p()); + } else { + iterateCheckString(nodep, "LHS", nodep->exprp(), BOTH); + } + } } void visit(AstFOpen* nodep) override { // Although a system function in IEEE, here a statement which sets the file pointer (MCD) diff --git a/src/verilog.y b/src/verilog.y index bb23f452c..38ae6e802 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -4223,7 +4223,7 @@ system_t_stmt_call: // IEEE: part of system_tf_call (as task returni | yD_DUMPVARS parenE { $$ = new AstDumpCtl{$1, VDumpCtlType::VARS, new AstConst{$1, 0}}; } | yD_DUMPVARS '(' expr ')' { $$ = new AstDumpCtl{$1, VDumpCtlType::VARS, $3}; } - | yD_DUMPVARS '(' expr ',' exprList ')' { $$ = new AstDumpCtl{$1, VDumpCtlType::VARS, $3}; DEL($5); } + | yD_DUMPVARS '(' expr ',' exprList ')' { $$ = GRAMMARP->createDumpVarsScoped($1, $3, $5); } | yD_DUMPALL parenE { $$ = new AstDumpCtl{$1, VDumpCtlType::ALL}; } | yD_DUMPALL '(' expr ')' { $$ = new AstDumpCtl{$1, VDumpCtlType::ALL}; DEL($3); } | yD_DUMPFLUSH parenE { $$ = new AstDumpCtl{$1, VDumpCtlType::FLUSH}; } diff --git a/test_regress/t/t_trace_dumpvars.out b/test_regress/t/t_trace_dumpvars.out new file mode 100644 index 000000000..652dd879a --- /dev/null +++ b/test_regress/t/t_trace_dumpvars.out @@ -0,0 +1,28 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $var wire 1 % clk $end + $var wire 32 " cyc [31:0] $end + $scope module sub_a $end + $var wire 32 & ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 # value [31:0] $end + $upscope $end + $scope module sub_b $end + $var wire 32 ' ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 $ value [31:0] $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 " +b00000000000000000000000000001010 # +b00000000000000000000000000010100 $ +0% +b00000000000000000000000000001010 & +b00000000000000000000000000010100 ' diff --git a/test_regress/t/t_trace_dumpvars.py b/test_regress/t/t_trace_dumpvars.py new file mode 100644 index 000000000..1eaecdb79 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--binary --trace-vcd']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars.v b/test_regress/t/t_trace_dumpvars.v new file mode 100644 index 000000000..6a65753e0 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars.v @@ -0,0 +1,38 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + $dumpvars(0); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_abs_scope.out b/test_regress/t/t_trace_dumpvars_abs_scope.out new file mode 100644 index 000000000..0a31846b7 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_abs_scope.out @@ -0,0 +1,29 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $scope module sub_a $end + $var wire 32 ( ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 # value [31:0] $end + $scope module deep_i $end + $var wire 32 ) ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 $ inner [31:0] $end + $upscope $end + $upscope $end + $scope module sub_b $end + $scope module deep_i $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 " +b00000000000000000000000000001010 # +b00000000000000000000000000001011 $ +b00000000000000000000000000001010 ( +b00000000000000000000000000001011 ) diff --git a/test_regress/t/t_trace_dumpvars_abs_scope.py b/test_regress/t/t_trace_dumpvars_abs_scope.py new file mode 100644 index 000000000..1eaecdb79 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_abs_scope.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--binary --trace-vcd']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_abs_scope.v b/test_regress/t/t_trace_dumpvars_abs_scope.v new file mode 100644 index 000000000..aa9d28fa2 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_abs_scope.v @@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // Test $dumpvars with absolute hierarchical scope path + $dumpvars(0, t.sub_a); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + deep #(ADD + 1) deep_i(.*); +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_add_module.py b/test_regress/t/t_trace_dumpvars_add_module.py new file mode 100644 index 000000000..51c1f9091 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_add_module.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--binary --timing --trace-vcd']) + +test.execute() + +test.vcd_identical(test.obj_dir + '/simx0.vcd', test.t_dir + '/t_trace_dumpvars_add_module_0.out') +test.vcd_identical(test.obj_dir + '/simx1.vcd', test.t_dir + '/t_trace_dumpvars_add_module_1.out') + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_add_module.v b/test_regress/t/t_trace_dumpvars_add_module.v new file mode 100644 index 000000000..26f7acbac --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_add_module.v @@ -0,0 +1,58 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( +); + logic clk; + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + initial begin + clk = 0; + forever #1 clk = !clk; + end + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 1) begin + $dumpfile({`STRINGIFY(`TEST_OBJ_DIR), "/simx1.vcd"}); + $dumpvars(0, sub_b); + end + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile({`STRINGIFY(`TEST_OBJ_DIR), "/simx0.vcd"}); + $dumpvars(1, sub_a); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + deep #(ADD + 1) deep_i(.*); +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_add_module_0.out b/test_regress/t/t_trace_dumpvars_add_module_0.out new file mode 100644 index 000000000..7a2a58e70 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_add_module_0.out @@ -0,0 +1,26 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module t $end + $scope module sub_a $end + $var wire 32 ( ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 # value [31:0] $end + $scope module deep_i $end + $upscope $end + $upscope $end + $scope module sub_b $end + $scope module deep_i $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 " +b00000000000000000000000000001010 # +b00000000000000000000000000001010 ( +#1 +b00000000000000000000000000000001 " +b00000000000000000000000000001011 # +#2 diff --git a/test_regress/t/t_trace_dumpvars_add_module_1.out b/test_regress/t/t_trace_dumpvars_add_module_1.out new file mode 100644 index 000000000..023264f2f --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_add_module_1.out @@ -0,0 +1,53 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module t $end + $scope module sub_a $end + $var wire 32 ( ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 # value [31:0] $end + $scope module deep_i $end + $upscope $end + $upscope $end + $scope module sub_b $end + $var wire 32 * ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 % value [31:0] $end + $scope module deep_i $end + $var wire 32 + ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 & inner [31:0] $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#3 +b00000000000000000000000000000010 " +b00000000000000000000000000001100 # +b00000000000000000000000000010110 % +b00000000000000000000000000010111 & +b00000000000000000000000000001010 ( +b00000000000000000000000000010100 * +b00000000000000000000000000010101 + +#5 +b00000000000000000000000000000011 " +b00000000000000000000000000001101 # +b00000000000000000000000000010111 % +b00000000000000000000000000011000 & +#7 +b00000000000000000000000000000100 " +b00000000000000000000000000001110 # +b00000000000000000000000000011000 % +b00000000000000000000000000011001 & +#9 +b00000000000000000000000000000101 " +b00000000000000000000000000001111 # +b00000000000000000000000000011001 % +b00000000000000000000000000011010 & +#11 +b00000000000000000000000000000110 " +b00000000000000000000000000010000 # +b00000000000000000000000000011010 % +b00000000000000000000000000011011 & + diff --git a/test_regress/t/t_trace_dumpvars_func.out b/test_regress/t/t_trace_dumpvars_func.out new file mode 100644 index 000000000..73b55a8a8 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_func.out @@ -0,0 +1,29 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $scope module sub_a $end + $var wire 32 ( ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 # value [31:0] $end + $scope module deep_i $end + $upscope $end + $upscope $end + $scope module sub_b $end + $var wire 32 * ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 % value [31:0] $end + $scope module deep_i $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 " +b00000000000000000000000000001010 # +b00000000000000000000000000010100 % +b00000000000000000000000000001010 ( +b00000000000000000000000000010100 * diff --git a/test_regress/t/t_trace_dumpvars_func.py b/test_regress/t/t_trace_dumpvars_func.py new file mode 100644 index 000000000..1eaecdb79 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_func.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--binary --trace-vcd']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_func.v b/test_regress/t/t_trace_dumpvars_func.v new file mode 100644 index 000000000..1a5def5eb --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_func.v @@ -0,0 +1,61 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +function int get_trace_level; + return 1; +endfunction + +function void varsdump; + $dumpvars(get_trace_level()); +endfunction + +function void setup_trace; + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + varsdump(); +endfunction + +module t( + input clk +); + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + initial begin + setup_trace; + end + + deep #(ADD + 1) deep_i(.*); +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_hier_scope.out b/test_regress/t/t_trace_dumpvars_hier_scope.out new file mode 100644 index 000000000..033f569da --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_hier_scope.out @@ -0,0 +1,24 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $scope module sub_a $end + $scope module deep_i $end + $var wire 32 ) ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 $ inner [31:0] $end + $upscope $end + $upscope $end + $scope module sub_b $end + $scope module deep_i $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 " +b00000000000000000000000000001011 $ +b00000000000000000000000000001011 ) diff --git a/test_regress/t/t_trace_dumpvars_hier_scope.py b/test_regress/t/t_trace_dumpvars_hier_scope.py new file mode 100644 index 000000000..1eaecdb79 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_hier_scope.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--binary --trace-vcd']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_hier_scope.v b/test_regress/t/t_trace_dumpvars_hier_scope.v new file mode 100644 index 000000000..899bbeea9 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_hier_scope.v @@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // Test $dumpvars with hierarchical scope: level 1 limits to direct signals of sub_a.deep_i + $dumpvars(1, sub_a.deep_i); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + deep #(ADD + 1) deep_i(.*); +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_level.out b/test_regress/t/t_trace_dumpvars_level.out new file mode 100644 index 000000000..b64676095 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_level.out @@ -0,0 +1,22 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $var wire 1 ' clk $end + $var wire 32 " cyc [31:0] $end + $scope module sub_a $end + $scope module deep_i $end + $upscope $end + $upscope $end + $scope module sub_b $end + $scope module deep_i $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 " +0' diff --git a/test_regress/t/t_trace_dumpvars_level.py b/test_regress/t/t_trace_dumpvars_level.py new file mode 100644 index 000000000..1eaecdb79 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_level.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--binary --trace-vcd']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_level.v b/test_regress/t/t_trace_dumpvars_level.v new file mode 100644 index 000000000..55c3ccc64 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_level.v @@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // Test $dumpvars with level argument (level 1 = top-level signals only) + $dumpvars(1); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + deep #(ADD + 1) deep_i(.*); +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_level_scope.out b/test_regress/t/t_trace_dumpvars_level_scope.out new file mode 100644 index 000000000..f2b9e53a4 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_level_scope.out @@ -0,0 +1,24 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $scope module sub_a $end + $var wire 32 ( ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 # value [31:0] $end + $scope module deep_i $end + $upscope $end + $upscope $end + $scope module sub_b $end + $scope module deep_i $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 " +b00000000000000000000000000001010 # +b00000000000000000000000000001010 ( diff --git a/test_regress/t/t_trace_dumpvars_level_scope.py b/test_regress/t/t_trace_dumpvars_level_scope.py new file mode 100644 index 000000000..1eaecdb79 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_level_scope.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--binary --trace-vcd']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_level_scope.v b/test_regress/t/t_trace_dumpvars_level_scope.v new file mode 100644 index 000000000..64c074c27 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_level_scope.v @@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // Test $dumpvars with level AND scope: level 1 limits to sub_a direct signals only + $dumpvars(1, sub_a); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + deep #(ADD + 1) deep_i(.*); +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_missing_scope.out b/test_regress/t/t_trace_dumpvars_missing_scope.out new file mode 100644 index 000000000..8bda5d834 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_missing_scope.out @@ -0,0 +1,15 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $scope module sub_a $end + $scope module deep_i $end + $upscope $end + $upscope $end + $scope module sub_b $end + $scope module deep_i $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end diff --git a/test_regress/t/t_trace_dumpvars_missing_scope.py b/test_regress/t/t_trace_dumpvars_missing_scope.py new file mode 100644 index 000000000..d38577388 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_missing_scope.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--binary --trace-vcd']) + +test.execute() + +test.file_grep(test.trace_filename, r'^\$enddefinitions \$end') +test.file_grep_not(test.trace_filename, r'^\s*\$var\s') + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_missing_scope.v b/test_regress/t/t_trace_dumpvars_missing_scope.v new file mode 100644 index 000000000..aac875054 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_missing_scope.v @@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // Test $dumpvars with a non-existent module scope argument + $dumpvars(0, missing_module); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + deep #(ADD + 1) deep_i(.*); +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_multi_scope.out b/test_regress/t/t_trace_dumpvars_multi_scope.out new file mode 100644 index 000000000..1fc4774b1 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_multi_scope.out @@ -0,0 +1,27 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $var wire 1 ' clk $end + $var wire 32 " cyc [31:0] $end + $scope module sub_a $end + $scope module deep_i $end + $var wire 32 ) ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 $ inner [31:0] $end + $upscope $end + $upscope $end + $scope module sub_b $end + $scope module deep_i $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 " +b00000000000000000000000000001011 $ +0' +b00000000000000000000000000001011 ) diff --git a/test_regress/t/t_trace_dumpvars_multi_scope.py b/test_regress/t/t_trace_dumpvars_multi_scope.py new file mode 100644 index 000000000..1eaecdb79 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_multi_scope.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--binary --trace-vcd']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_multi_scope.v b/test_regress/t/t_trace_dumpvars_multi_scope.v new file mode 100644 index 000000000..56a1fdbee --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_multi_scope.v @@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // Test multiple scopes with non-constant level expression + $dumpvars(0+1, t, t.sub_a.deep_i); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + deep #(ADD + 1) deep_i(.*); +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_nonconst_scope.out b/test_regress/t/t_trace_dumpvars_nonconst_scope.out new file mode 100644 index 000000000..b1f35509d --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_nonconst_scope.out @@ -0,0 +1,31 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $scope module dumpblock $end + $upscope $end + $scope module sub_a $end + $var wire 32 ) ADD [31:0] $end + $var wire 32 # cyc [31:0] $end + $var wire 32 $ value [31:0] $end + $scope module deep_i $end + $var wire 32 * ADD [31:0] $end + $var wire 32 # cyc [31:0] $end + $var wire 32 % inner [31:0] $end + $upscope $end + $upscope $end + $scope module sub_b $end + $scope module deep_i $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 # +b00000000000000000000000000001010 $ +b00000000000000000000000000001011 % +b00000000000000000000000000001010 ) +b00000000000000000000000000001011 * diff --git a/test_regress/t/t_trace_dumpvars_nonconst_scope.py b/test_regress/t/t_trace_dumpvars_nonconst_scope.py new file mode 100644 index 000000000..07e99a967 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_nonconst_scope.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--binary --trace-vcd']) + +test.execute(all_run_flags=['+LEVEL=0']) + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_nonconst_scope.v b/test_regress/t/t_trace_dumpvars_nonconst_scope.v new file mode 100644 index 000000000..82310bb9e --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_nonconst_scope.v @@ -0,0 +1,52 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin: dumpblock + int level; + if (!$value$plusargs("LEVEL=%d", level)) level = 0; + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // Test $dumpvars with non-constant level expression and scope argument + $dumpvars(level, t.sub_a); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + deep #(ADD + 1) deep_i(.*); +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_override.out b/test_regress/t/t_trace_dumpvars_override.out new file mode 100644 index 000000000..2d2474dc9 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_override.out @@ -0,0 +1,42 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $var wire 1 ' clk $end + $var wire 32 " cyc [31:0] $end + $scope module sub_a $end + $var wire 32 ( ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 # value [31:0] $end + $scope module deep_i $end + $var wire 32 ) ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 $ inner [31:0] $end + $upscope $end + $upscope $end + $scope module sub_b $end + $var wire 32 * ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 % value [31:0] $end + $scope module deep_i $end + $var wire 32 + ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 & inner [31:0] $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 " +b00000000000000000000000000001010 # +b00000000000000000000000000001011 $ +b00000000000000000000000000010100 % +b00000000000000000000000000010101 & +0' +b00000000000000000000000000001010 ( +b00000000000000000000000000001011 ) +b00000000000000000000000000010100 * +b00000000000000000000000000010101 + diff --git a/test_regress/t/t_trace_dumpvars_override.py b/test_regress/t/t_trace_dumpvars_override.py new file mode 100644 index 000000000..1eaecdb79 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_override.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--binary --trace-vcd']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_override.v b/test_regress/t/t_trace_dumpvars_override.v new file mode 100644 index 000000000..ca4c1fad9 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_override.v @@ -0,0 +1,51 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // First restrict to deep_i only, then override with $dumpvars(0) to dump all + $dumpvars(1, t.sub_a.deep_i); + $dumpvars(0); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + deep #(ADD + 1) deep_i(.*); +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_scope.out b/test_regress/t/t_trace_dumpvars_scope.out new file mode 100644 index 000000000..0a31846b7 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_scope.out @@ -0,0 +1,29 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $scope module sub_a $end + $var wire 32 ( ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 # value [31:0] $end + $scope module deep_i $end + $var wire 32 ) ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 $ inner [31:0] $end + $upscope $end + $upscope $end + $scope module sub_b $end + $scope module deep_i $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 " +b00000000000000000000000000001010 # +b00000000000000000000000000001011 $ +b00000000000000000000000000001010 ( +b00000000000000000000000000001011 ) diff --git a/test_regress/t/t_trace_dumpvars_scope.py b/test_regress/t/t_trace_dumpvars_scope.py new file mode 100644 index 000000000..1eaecdb79 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_scope.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--binary --trace-vcd']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_scope.v b/test_regress/t/t_trace_dumpvars_scope.v new file mode 100644 index 000000000..fb2155d2e --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_scope.v @@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // Test $dumpvars with module scope argument + $dumpvars(0, sub_a); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + deep #(ADD + 1) deep_i(.*); +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_struct.out b/test_regress/t/t_trace_dumpvars_struct.out new file mode 100644 index 000000000..48d50a1af --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_struct.out @@ -0,0 +1,36 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $var wire 1 * clk $end + $var wire 32 " cyc [31:0] $end + $scope module rect $end + $scope module origin $end + $var wire 8 # x [7:0] $end + $var wire 8 $ y [7:0] $end + $upscope $end + $scope module size $end + $var wire 8 % x [7:0] $end + $var wire 8 & y [7:0] $end + $upscope $end + $upscope $end + $scope module pt $end + $var wire 8 ' x [7:0] $end + $var wire 8 ( y [7:0] $end + $upscope $end + $scope module sub_a $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 " +b00000000 # +b00000000 $ +b00000000 % +b00000000 & +b00000000 ' +b00000000 ( +0* diff --git a/test_regress/t/t_trace_dumpvars_struct.py b/test_regress/t/t_trace_dumpvars_struct.py new file mode 100644 index 000000000..3768a51af --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_struct.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--binary --trace-vcd --trace-structs']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_struct.v b/test_regress/t/t_trace_dumpvars_struct.v new file mode 100644 index 000000000..132e3438f --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_struct.v @@ -0,0 +1,57 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + typedef struct packed { + logic [7:0] x; + logic [7:0] y; + } point_t; + + typedef struct packed { + point_t origin; + point_t size; + } rect_t; + + int cyc; + rect_t rect; + point_t pt; + + sub #(10) sub_a(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + pt.x <= pt.x + 1; + pt.y <= pt.y + 2; + rect.origin.x <= rect.origin.x + 1; + rect.origin.y <= rect.origin.y + 2; + rect.size.x <= 8'd100; + rect.size.y <= 8'd200; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // Level 1 counts only module nesting, so nested struct members under t + // are dumped, but sub_a's signals are still excluded. + $dumpvars(1); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_sub.out b/test_regress/t/t_trace_dumpvars_sub.out new file mode 100644 index 000000000..73b55a8a8 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_sub.out @@ -0,0 +1,29 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $scope module sub_a $end + $var wire 32 ( ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 # value [31:0] $end + $scope module deep_i $end + $upscope $end + $upscope $end + $scope module sub_b $end + $var wire 32 * ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 % value [31:0] $end + $scope module deep_i $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 " +b00000000000000000000000000001010 # +b00000000000000000000000000010100 % +b00000000000000000000000000001010 ( +b00000000000000000000000000010100 * diff --git a/test_regress/t/t_trace_dumpvars_sub.py b/test_regress/t/t_trace_dumpvars_sub.py new file mode 100644 index 000000000..1eaecdb79 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_sub.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--binary --trace-vcd']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_sub.v b/test_regress/t/t_trace_dumpvars_sub.v new file mode 100644 index 000000000..dcddf9c90 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_sub.v @@ -0,0 +1,54 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + deep #(ADD + 1) deep_i(.*); + + // $dumpvars called from sub module scope with level 1 + // Should dump only this sub module's direct signals, not deep_i's + initial begin + $dumpvars(1); + end +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_sub0.out b/test_regress/t/t_trace_dumpvars_sub0.out new file mode 100644 index 000000000..7418ac167 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_sub0.out @@ -0,0 +1,39 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $scope module sub_a $end + $var wire 32 ( ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 # value [31:0] $end + $scope module deep_i $end + $var wire 32 ) ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 $ inner [31:0] $end + $upscope $end + $upscope $end + $scope module sub_b $end + $var wire 32 * ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 % value [31:0] $end + $scope module deep_i $end + $var wire 32 + ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 & inner [31:0] $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 " +b00000000000000000000000000001010 # +b00000000000000000000000000001011 $ +b00000000000000000000000000010100 % +b00000000000000000000000000010101 & +b00000000000000000000000000001010 ( +b00000000000000000000000000001011 ) +b00000000000000000000000000010100 * +b00000000000000000000000000010101 + diff --git a/test_regress/t/t_trace_dumpvars_sub0.py b/test_regress/t/t_trace_dumpvars_sub0.py new file mode 100644 index 000000000..1eaecdb79 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_sub0.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--binary --trace-vcd']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_sub0.v b/test_regress/t/t_trace_dumpvars_sub0.v new file mode 100644 index 000000000..ca936cd7e --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_sub0.v @@ -0,0 +1,54 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + deep #(ADD + 1) deep_i(.*); + + // $dumpvars called from sub module scope with level 0 + // Should dump all signals in this sub module and below (including deep_i) + initial begin + $dumpvars(0); + end +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_task.out b/test_regress/t/t_trace_dumpvars_task.out new file mode 100644 index 000000000..73b55a8a8 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_task.out @@ -0,0 +1,29 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $scope module sub_a $end + $var wire 32 ( ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 # value [31:0] $end + $scope module deep_i $end + $upscope $end + $upscope $end + $scope module sub_b $end + $var wire 32 * ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 % value [31:0] $end + $scope module deep_i $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 " +b00000000000000000000000000001010 # +b00000000000000000000000000010100 % +b00000000000000000000000000001010 ( +b00000000000000000000000000010100 * diff --git a/test_regress/t/t_trace_dumpvars_task.py b/test_regress/t/t_trace_dumpvars_task.py new file mode 100644 index 000000000..1eaecdb79 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_task.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--binary --trace-vcd']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_task.v b/test_regress/t/t_trace_dumpvars_task.v new file mode 100644 index 000000000..74e64feb7 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_task.v @@ -0,0 +1,61 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +function int get_trace_level; + return 1; +endfunction + +function void varsdump; + $dumpvars(get_trace_level()); +endfunction + +task setup_trace; + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + varsdump(); +endtask + +module t( + input clk +); + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + initial begin + setup_trace; + end + + deep #(ADD + 1) deep_i(.*); +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_task2.out b/test_regress/t/t_trace_dumpvars_task2.out new file mode 100644 index 000000000..73b55a8a8 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_task2.out @@ -0,0 +1,29 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $scope module sub_a $end + $var wire 32 ( ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 # value [31:0] $end + $scope module deep_i $end + $upscope $end + $upscope $end + $scope module sub_b $end + $var wire 32 * ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 % value [31:0] $end + $scope module deep_i $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 " +b00000000000000000000000000001010 # +b00000000000000000000000000010100 % +b00000000000000000000000000001010 ( +b00000000000000000000000000010100 * diff --git a/test_regress/t/t_trace_dumpvars_task2.py b/test_regress/t/t_trace_dumpvars_task2.py new file mode 100644 index 000000000..1eaecdb79 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_task2.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--binary --trace-vcd']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_task2.v b/test_regress/t/t_trace_dumpvars_task2.v new file mode 100644 index 000000000..6b0fe071e --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_task2.v @@ -0,0 +1,65 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +function int get_trace_level; + return 1; +endfunction + +function void varsdump; + $dumpvars(get_trace_level()); +endfunction + +task setup_trace; + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + varsdump(); +endtask + +task setup_trace_nested; + setup_trace(); +endtask + +module t( + input clk +); + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + initial begin + setup_trace_nested; + end + + deep #(ADD + 1) deep_i(.*); +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_wire.out b/test_regress/t/t_trace_dumpvars_wire.out new file mode 100644 index 000000000..d10cfb434 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_wire.out @@ -0,0 +1,18 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $var wire 32 " cyc [31:0] $end + $var wire 32 # counter [31:0] $end + $scope module sub_a $end + $upscope $end + $scope module sub_b $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 " +b00000000000000000000000000000000 # diff --git a/test_regress/t/t_trace_dumpvars_wire.py b/test_regress/t/t_trace_dumpvars_wire.py new file mode 100644 index 000000000..1eaecdb79 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_wire.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--binary --trace-vcd']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_wire.v b/test_regress/t/t_trace_dumpvars_wire.v new file mode 100644 index 000000000..2ec84035c --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_wire.v @@ -0,0 +1,41 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + int counter; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + counter <= counter + 2; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // Test $dumpvars with specific wire names + $dumpvars(0, cyc, counter); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; +endmodule From ad50b31077605f203a7c385a5ceba439256c8527 Mon Sep 17 00:00:00 2001 From: wsxarcher Date: Mon, 23 Mar 2026 23:45:43 +0100 Subject: [PATCH 02/13] Fix root global, arrays, no inline, escaped, fail on missing --- include/verilated.cpp | 7 +- include/verilated.h | 3 + include/verilated_fst_c.h | 3 + include/verilated_saif_c.h | 3 + include/verilated_trace.h | 5 + include/verilated_trace_imp.h | 7 +- include/verilated_vcd_c.h | 3 + src/CMakeLists.txt | 1 + src/V3Dumpvars.h | 47 +++++ src/V3EmitCFunc.h | 60 ++++++- src/V3EmitCSyms.cpp | 7 +- src/V3LinkDot.cpp | 161 ++++++++++++++++-- src/V3LinkDot.h | 1 + src/V3ParseGrammar.cpp | 7 - src/V3ParseGrammar.h | 2 - src/V3Task.cpp | 31 ++-- src/verilog.y | 8 +- test_regress/t/t_trace_dumpvars.out | 1 + test_regress/t/t_trace_dumpvars_context.out | 31 ++++ test_regress/t/t_trace_dumpvars_context.py | 20 +++ test_regress/t/t_trace_dumpvars_context.v | 57 +++++++ test_regress/t/t_trace_dumpvars_cpptop.cpp | 36 ++++ test_regress/t/t_trace_dumpvars_cpptop.out | 69 ++++++++ test_regress/t/t_trace_dumpvars_cpptop.py | 27 +++ test_regress/t/t_trace_dumpvars_cpptop.v | 39 +++++ test_regress/t/t_trace_dumpvars_cpptop2.cpp | 36 ++++ test_regress/t/t_trace_dumpvars_cpptop2.out | 2 + test_regress/t/t_trace_dumpvars_cpptop2.py | 25 +++ test_regress/t/t_trace_dumpvars_cpptop2.v | 38 +++++ .../t/t_trace_dumpvars_hier_array.out | 24 +++ test_regress/t/t_trace_dumpvars_hier_array.py | 20 +++ test_regress/t/t_trace_dumpvars_hier_array.v | 49 ++++++ .../t/t_trace_dumpvars_hier_global.out | 26 +++ .../t/t_trace_dumpvars_hier_global.py | 20 +++ test_regress/t/t_trace_dumpvars_hier_global.v | 56 ++++++ .../t/t_trace_dumpvars_hier_global_task.out | 26 +++ .../t/t_trace_dumpvars_hier_global_task.py | 20 +++ .../t/t_trace_dumpvars_hier_global_task.v | 71 ++++++++ .../t/t_trace_dumpvars_hier_struct.out | 20 +++ .../t/t_trace_dumpvars_hier_struct.py | 20 +++ test_regress/t/t_trace_dumpvars_hier_struct.v | 46 +++++ .../t/t_trace_dumpvars_missing_scope.out | 17 +- .../t/t_trace_dumpvars_missing_scope.py | 5 +- test_regress/t/t_trace_dumpvars_override.out | 1 + test_regress/t/t_trace_dumpvars_struct.out | 32 ++-- test_regress/t/t_trace_dumpvars_struct.v | 18 +- .../t/t_trace_dumpvars_task2_no_inl.out | 29 ++++ .../t/t_trace_dumpvars_task2_no_inl.py | 20 +++ .../t/t_trace_dumpvars_task2_no_inl.v | 65 +++++++ .../t/t_trace_dumpvars_task_no_inl.out | 29 ++++ .../t/t_trace_dumpvars_task_no_inl.py | 20 +++ test_regress/t/t_trace_dumpvars_task_no_inl.v | 61 +++++++ test_regress/t/t_trace_event.v | 2 +- test_regress/t/t_trace_two_a.v | 6 +- 54 files changed, 1326 insertions(+), 114 deletions(-) create mode 100644 src/V3Dumpvars.h create mode 100644 test_regress/t/t_trace_dumpvars_context.out create mode 100644 test_regress/t/t_trace_dumpvars_context.py create mode 100644 test_regress/t/t_trace_dumpvars_context.v create mode 100644 test_regress/t/t_trace_dumpvars_cpptop.cpp create mode 100644 test_regress/t/t_trace_dumpvars_cpptop.out create mode 100644 test_regress/t/t_trace_dumpvars_cpptop.py create mode 100644 test_regress/t/t_trace_dumpvars_cpptop.v create mode 100644 test_regress/t/t_trace_dumpvars_cpptop2.cpp create mode 100644 test_regress/t/t_trace_dumpvars_cpptop2.out create mode 100644 test_regress/t/t_trace_dumpvars_cpptop2.py create mode 100644 test_regress/t/t_trace_dumpvars_cpptop2.v create mode 100644 test_regress/t/t_trace_dumpvars_hier_array.out create mode 100644 test_regress/t/t_trace_dumpvars_hier_array.py create mode 100644 test_regress/t/t_trace_dumpvars_hier_array.v create mode 100644 test_regress/t/t_trace_dumpvars_hier_global.out create mode 100644 test_regress/t/t_trace_dumpvars_hier_global.py create mode 100644 test_regress/t/t_trace_dumpvars_hier_global.v create mode 100644 test_regress/t/t_trace_dumpvars_hier_global_task.out create mode 100644 test_regress/t/t_trace_dumpvars_hier_global_task.py create mode 100644 test_regress/t/t_trace_dumpvars_hier_global_task.v create mode 100644 test_regress/t/t_trace_dumpvars_hier_struct.out create mode 100644 test_regress/t/t_trace_dumpvars_hier_struct.py create mode 100644 test_regress/t/t_trace_dumpvars_hier_struct.v create mode 100644 test_regress/t/t_trace_dumpvars_task2_no_inl.out create mode 100644 test_regress/t/t_trace_dumpvars_task2_no_inl.py create mode 100644 test_regress/t/t_trace_dumpvars_task2_no_inl.v create mode 100644 test_regress/t/t_trace_dumpvars_task_no_inl.out create mode 100644 test_regress/t/t_trace_dumpvars_task_no_inl.py create mode 100644 test_regress/t/t_trace_dumpvars_task_no_inl.v diff --git a/include/verilated.cpp b/include/verilated.cpp index 1f7987af6..dbd5cdf24 100644 --- a/include/verilated.cpp +++ b/include/verilated.cpp @@ -2929,11 +2929,8 @@ std::string VerilatedContext::dumpfileCheck() const VL_MT_SAFE_EXCLUDES(m_timeDu void VerilatedContext::dumpvarsAdd(int level, const std::string& hier) VL_MT_SAFE_EXCLUDES(m_timeDumpMutex) { const VerilatedLockGuard lock{m_timeDumpMutex}; - if (level == 0 && hier.empty()) { - m_dumpvars.clear(); - } else { - m_dumpvars.emplace_back(level, hier); - } + if (level == 0 && hier.empty()) m_dumpvars.clear(); + m_dumpvars.emplace_back(level, hier); } std::vector VerilatedContext::dumpvars() const VL_MT_SAFE_EXCLUDES(m_timeDumpMutex) { diff --git a/include/verilated.h b/include/verilated.h index a7cd7d734..c605a98f8 100644 --- a/include/verilated.h +++ b/include/verilated.h @@ -110,8 +110,11 @@ class VerilatedVcd; class VerilatedVcdC; class VerilatedVcdSc; +// Internal: One $dumpvars call. struct VerilatedTraceDumpvarsEntry final { + /// Maximum hierarchy depth to dump modules. int m_level; + /// Hierarchy root to dump. std::string m_hier; VerilatedTraceDumpvarsEntry(int level, const std::string& hier) diff --git a/include/verilated_fst_c.h b/include/verilated_fst_c.h index beab35565..5de5f9a85 100644 --- a/include/verilated_fst_c.h +++ b/include/verilated_fst_c.h @@ -300,6 +300,9 @@ public: void dumpvars(int level, const std::string& hier) VL_MT_SAFE { m_sptrace.dumpvars(level, hier); } + void dumpvars(const std::vector& entries) VL_MT_SAFE { + m_sptrace.dumpvars(entries); + } // Internal class access VerilatedFst* spTrace() { return &m_sptrace; } diff --git a/include/verilated_saif_c.h b/include/verilated_saif_c.h index af7766b9e..adbdd6f00 100644 --- a/include/verilated_saif_c.h +++ b/include/verilated_saif_c.h @@ -318,6 +318,9 @@ public: void dumpvars(int level, const std::string& hier) VL_MT_SAFE { m_sptrace.dumpvars(level, hier); } + void dumpvars(const std::vector& entries) VL_MT_SAFE { + m_sptrace.dumpvars(entries); + } // Internal class access VerilatedSaif* spTrace() { return &m_sptrace; } diff --git a/include/verilated_trace.h b/include/verilated_trace.h index c107a76cc..9b6756695 100644 --- a/include/verilated_trace.h +++ b/include/verilated_trace.h @@ -509,6 +509,11 @@ public: // Set variables to dump, using $dumpvars format // If level = 0, dump everything and hier is then ignored void dumpvars(int level, const std::string& hier) VL_MT_SAFE; + void dumpvars(const std::vector& entries) VL_MT_SAFE { + for (const VerilatedTraceDumpvarsEntry& entry : entries) { + dumpvars(entry.m_level, entry.m_hier); + } + } // Call void dump(uint64_t timeui) VL_MT_SAFE_EXCLUDES(m_mutex); diff --git a/include/verilated_trace_imp.h b/include/verilated_trace_imp.h index 758d97dfa..603652005 100644 --- a/include/verilated_trace_imp.h +++ b/include/verilated_trace_imp.h @@ -422,11 +422,8 @@ void VerilatedTrace::set_time_resolution(const std::string& } template <> void VerilatedTrace::dumpvars(int level, const std::string& hier) VL_MT_SAFE { - if (level == 0 && hier.empty()) { - m_dumpvars.clear(); // empty = everything on - } else { - m_dumpvars.emplace_back(level, hier); - } + if (level == 0 && hier.empty()) m_dumpvars.clear(); + m_dumpvars.emplace_back(level, hier); } template <> diff --git a/include/verilated_vcd_c.h b/include/verilated_vcd_c.h index 4731facfe..b328a298d 100644 --- a/include/verilated_vcd_c.h +++ b/include/verilated_vcd_c.h @@ -351,6 +351,9 @@ public: void dumpvars(int level, const std::string& hier) VL_MT_SAFE { m_sptrace.dumpvars(level, hier); } + void dumpvars(const std::vector& entries) VL_MT_SAFE { + m_sptrace.dumpvars(entries); + } // Internal class access VerilatedVcd* spTrace() { return &m_sptrace; } diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index d03324eed..d8416bd1c 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -86,6 +86,7 @@ set(HEADERS V3DfgPeepholePatterns.h V3DfgVertices.h V3DiagSarif.h + V3Dumpvars.h V3DupFinder.h V3EmitC.h V3EmitCBase.h diff --git a/src/V3Dumpvars.h b/src/V3Dumpvars.h new file mode 100644 index 000000000..58b200369 --- /dev/null +++ b/src/V3Dumpvars.h @@ -0,0 +1,47 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//************************************************************************* +// DESCRIPTION: Verilator: Dumpvars helpers +// +// Code available from: https://verilator.org +// +//************************************************************************* +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +//************************************************************************* + +#ifndef VERILATOR_V3DUMPVARS_H_ +#define VERILATOR_V3DUMPVARS_H_ + +#include "config_build.h" +#include "verilatedos.h" + +// Tagged $dumpvars target string. During compile-time resolution in V3LinkDot +// each target is tagged with a prefix that tells EmitC how to emit the +// corresponding runtime code. The three tag types are: +// Resolved – fully resolved to a compile-time hierarchy path +// RuntimeRoot – first component must match the C++ wrapper root name at runtime +// Missing – proven invalid at compile time; emit VL_FATAL_MT at runtime +struct DumpvarsTag final { + const char* const prefix; + const size_t prefixLen; + template + constexpr DumpvarsTag(const char (&s)[N]) + : prefix{s} + , prefixLen{N - 1} {} + bool matches(const string& target) const { return target.compare(0, prefixLen, prefix) == 0; } + string make(const string& target) const { return string{prefix, prefixLen} + target; } + string strip(const string& target) const { + return matches(target) ? target.substr(prefixLen) : target; + } +}; + +constexpr DumpvarsTag kDumpvarsResolved{"@dumpvars:"}; +constexpr DumpvarsTag kDumpvarsRuntimeRoot{"@dumpvars_root:"}; +constexpr DumpvarsTag kDumpvarsMissing{"@dumpvars_missing:"}; + +#endif // Guard diff --git a/src/V3EmitCFunc.h b/src/V3EmitCFunc.h index 05272ee74..0a6d0bd07 100644 --- a/src/V3EmitCFunc.h +++ b/src/V3EmitCFunc.h @@ -21,6 +21,7 @@ #include "verilatedos.h" #include "V3EmitCConstInit.h" +#include "V3Dumpvars.h" #include "V3Global.h" #include "V3MemberMap.h" @@ -903,8 +904,9 @@ public: static string dumpvarsHierPath(const string& scope, const string& target) { if (target.empty()) return scope; + if (kDumpvarsResolved.matches(target)) return kDumpvarsResolved.strip(target); if (scope.empty() || dumpvarsHasScopePrefix(target, scope)) return target; - return scope + "." + target; + return VString::dot(scope, ".", target); } // Emit C++ code that registers a $dumpvars filter at runtime. @@ -923,6 +925,41 @@ public: puts(levelExpr); puts(", __vlDvHier); }\n"); } + void emitDumpVarsAddRuntimeRoot(const AstDumpCtl* nodep, const string& target, + const string& levelExpr) { + const string::size_type dotPos = target.find('.'); + const string rootName = dotPos == string::npos ? target : target.substr(0, dotPos); + const string suffix = dotPos == string::npos ? "" : target.substr(dotPos + 1); + putns(nodep, "{ const std::string __vlDvRoot{vlSymsp->name()};\n"); + puts("if (__vlDvRoot != \""); + puts(V3OutFormatter::quoteNameControls(rootName)); + puts("\") VL_FATAL_MT(\""); + puts(V3OutFormatter::quoteNameControls(protect(nodep->fileline()->filename()))); + puts("\", "); + puts(cvtToStr(nodep->fileline()->lineno())); + puts(", \"\", \"$dumpvars target not found: "); + puts(V3OutFormatter::quoteNameControls(target)); + puts("\");\n"); + puts("std::string __vlDvHier{__vlDvRoot};\n"); + if (!suffix.empty()) { + puts("__vlDvHier += '.';\n"); + puts("__vlDvHier += \""); + puts(V3OutFormatter::quoteNameControls(suffix)); + puts("\";\n"); + } + puts("vlSymsp->_vm_contextp__->dumpvarsAdd("); + puts(levelExpr); + puts(", __vlDvHier); }\n"); + } + void emitDumpVarsTargetMissing(const AstDumpCtl* nodep, const string& target) { + putns(nodep, "VL_FATAL_MT(\""); + puts(V3OutFormatter::quoteNameControls(protect(nodep->fileline()->filename()))); + puts("\", "); + puts(cvtToStr(nodep->fileline()->lineno())); + puts(", \"\", \"$dumpvars target not found: "); + puts(V3OutFormatter::quoteNameControls(target)); + puts("\");\n"); + } // Emit $dumpvars filter logic when scope info is available. void emitDumpVarsWithScope(AstDumpCtl* nodep) { UASSERT_OBJ(nodep->scopeNamep(), nodep, "$dumpvars missing AstScopeName"); @@ -938,14 +975,29 @@ public: puts(";\n"); levelExpr = "__vlDvLevel"; } - // Emit one dumpvarsAdd call per target, or one for the scope itself + // Emit one dumpvarsAdd call per target, or one for the scope itself. + // The no-target $dumpvars(0) form is design-global and should not be + // narrowed to the lexical scope where it appears. if (nodep->targetsp()) { for (AstNode* tp = nodep->targetsp(); tp; tp = tp->nextp()) { const string target = VN_AS(tp, Text)->text(); - emitDumpVarsAdd(nodep, dumpvarsHierPath(scope, target), levelExpr); + if (kDumpvarsMissing.matches(target)) { + emitDumpVarsTargetMissing(nodep, kDumpvarsMissing.strip(target)); + } else if (kDumpvarsRuntimeRoot.matches(target)) { + emitDumpVarsAddRuntimeRoot(nodep, kDumpvarsRuntimeRoot.strip(target), + levelExpr); + } else { + emitDumpVarsAdd(nodep, dumpvarsHierPath(scope, target), levelExpr); + } } } else { - emitDumpVarsAdd(nodep, scope, levelExpr); + if (levelp && levelp->toUInt() == 0 && scope.find('.') == string::npos) { + putns(nodep, "vlSymsp->_vm_contextp__->dumpvarsAdd("); + puts(levelExpr); + puts(", \"\"s);\n"); + } else { + emitDumpVarsAdd(nodep, scope, levelExpr); + } } if (!levelp) puts("}\n"); putns(nodep, "vlSymsp->_traceDumpClose();\n"); diff --git a/src/V3EmitCSyms.cpp b/src/V3EmitCSyms.cpp index e4e014208..7e858dd12 100644 --- a/src/V3EmitCSyms.cpp +++ b/src/V3EmitCSyms.cpp @@ -1215,11 +1215,8 @@ void EmitCSyms::emitSymImp(const AstNetlist* netlistp) { puts("const VerilatedLockGuard lock{__Vm_dumperMutex};\n"); puts("if (VL_UNLIKELY(!__Vm_dumperp)) {\n"); puts("__Vm_dumperp = new " + v3Global.opt.traceClassLang() + "();\n"); - puts("const auto dvars = _vm_contextp__->dumpvars();\n"); - puts("for (const auto& dv : dvars) {\n"); - puts("__Vm_dumperp->dumpvars(dv.m_level, dv.m_hier);\n"); - puts("}\n"); - puts("__Vm_modelp->trace(__Vm_dumperp, 0, 0);\n"); + puts("__Vm_dumperp->dumpvars(_vm_contextp__->dumpvars());\n"); + puts("_vm_contextp__->trace(__Vm_dumperp, 0, 0);\n"); puts("const std::string dumpfile = _vm_contextp__->dumpfileCheck();\n"); puts("__Vm_dumperp->open(dumpfile.c_str());\n"); puts("__Vm_dumping = true;\n"); diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index 629fd074a..281c289d2 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -84,19 +84,29 @@ static string dumpvarsTargetText(const AstNode* nodep) { if (!nodep) return ""; if (const AstText* const textp = VN_CAST(nodep, Text)) return textp->text(); if (const AstCellRef* const refp = VN_CAST(nodep, CellRef)) return refp->name(); - if (const AstCellArrayRef* const refp = VN_CAST(nodep, CellArrayRef)) return refp->name(); + if (const AstSelBit* const selp = VN_CAST(nodep, SelBit)) { + const string from = dumpvarsTargetText(selp->fromp()); + const string bit = dumpvarsTargetText(selp->bitp()); + if (from.empty()) return ""; + return from + "[" + bit + "]"; + } + if (const AstCellArrayRef* const refp = VN_CAST(nodep, CellArrayRef)) { + string out = refp->name(); + for (const AstNodeExpr* selp = refp->selp(); selp; selp = VN_CAST(selp->nextp(), NodeExpr)) { + out += "[" + dumpvarsTargetText(selp) + "]"; + } + return out; + } + if (const AstConst* const constp = VN_CAST(nodep, Const)) return cvtToStr(constp->toSInt()); if (const AstParseRef* const refp = VN_CAST(nodep, ParseRef)) return refp->prettyName(); if (const AstVarRef* const refp = VN_CAST(nodep, VarRef)) return refp->name(); if (const AstVarXRef* const refp = VN_CAST(nodep, VarXRef)) { - if (refp->dotted().empty()) return refp->name(); - return refp->dotted() + "." + refp->name(); + return VString::dot(refp->dotted(), ".", refp->name()); } if (const AstDot* const dotp = VN_CAST(nodep, Dot)) { const string lhs = dumpvarsTargetText(dotp->lhsp()); const string rhs = dumpvarsTargetText(dotp->rhsp()); - if (lhs.empty()) return rhs; - if (rhs.empty()) return lhs; - return lhs + "." + rhs; + return VString::dot(lhs, ".", rhs); } return nodep->prettyName(); } @@ -3163,6 +3173,127 @@ class LinkDotResolveVisitor final : public VNVisitor { } } m_ds; // State to preserve across recursions + static string dumpvarsSymPathPiece(const AstNode* nodep) { + if (!nodep) return ""; + if (const AstNodeModule* const modp = VN_CAST(nodep, NodeModule)) return modp->origName(); + if (const AstCell* const cellp = VN_CAST(nodep, Cell)) return cellp->origName(); + if (const AstCellInline* const inlinep = VN_CAST(nodep, CellInline)) return inlinep->name(); + if (const AstVarScope* const vscp = VN_CAST(nodep, VarScope)) return vscp->varp()->name(); + return nodep->name(); + } + + static bool dumpvarsMatchesLocalModule(const VSymEnt* symp, const string& ident) { + if (!symp) return false; + if (const AstCell* const cellp = VN_CAST(symp->nodep(), Cell)) { + return cellp->modp() && cellp->modp()->origName() == ident; + } + if (const AstCellInline* const inlinep = VN_CAST(symp->nodep(), CellInline)) { + return inlinep->origModName() == ident; + } + if (const AstNodeModule* const modp = VN_CAST(symp->nodep(), NodeModule)) { + return modp->origName() == ident; + } + return false; + } + + static string dumpvarsResolvedPath(VSymEnt* symp) { + std::vector pieces; + for (VSymEnt* walkp = symp; walkp && walkp->parentp(); walkp = walkp->parentp()) { + const string piece = dumpvarsSymPathPiece(walkp->nodep()); + if (!piece.empty()) pieces.push_back(piece); + } + std::reverse(pieces.begin(), pieces.end()); + string path; + for (const string& piece : pieces) { + if (!path.empty()) path += '.'; + path += piece; + } + return path; + } + + static bool dumpvarsHasBareTarget(AstNode* targetsp, const string& name) { + for (AstNode* tp = targetsp; tp; tp = tp->nextp()) { + if (dumpvarsTargetText(tp) == name) return true; + } + return false; + } + + VSymEnt* findDumpvarsLocal(FileLine* refLocationp, const string& dotname, string& baddot, + VSymEnt*& okSymp) { + if (!m_curSymp) return nullptr; + string leftname = dotname; + string::size_type pos; + string ident; + if ((pos = leftname.find('.')) != string::npos) { + ident = leftname.substr(0, pos); + leftname = leftname.substr(pos + 1); + } else { + ident = leftname; + leftname = ""; + } + + baddot = ident; + okSymp = m_curSymp; + string altIdent; + if (m_statep->forPrearray()) { + if ((pos = ident.rfind("__BRA__")) != string::npos) altIdent = ident.substr(0, pos); + } + + VSymEnt* symp = nullptr; + if (dumpvarsMatchesLocalModule(m_curSymp, ident)) { + symp = m_curSymp; + } else { + symp = m_curSymp->findIdFallback(ident); + if (!symp && !altIdent.empty()) symp = m_curSymp->findIdFallback(altIdent); + } + if (!symp) return nullptr; + if (leftname.empty()) { + okSymp = symp; + return symp; + } + return m_statep->findDotted(refLocationp, symp, leftname, baddot, okSymp, false); + } + + // Resolve a single $dumpvars target string against the symbol table. + // Returns a tagged string that tells EmitC how to generate the runtime code. + string resolveDumpvarsTarget(FileLine* fl, const string& target, AstNode* targetsp) { + if (target.empty() || !m_curSymp) return target; + + string baddot; + VSymEnt* matchSymp = nullptr; + + // Step 1: Try local scope lookup. + if (findDumpvarsLocal(fl, target, baddot, matchSymp)) return target; + + // Step 2: Try global lookup from $root. + if (VSymEnt* const rootSymp = m_statep->findDotted( + fl, m_statep->rootEntp(), target, baddot, matchSymp, true)) { + const string resolved = dumpvarsResolvedPath(rootSymp); + if (!resolved.empty()) return kDumpvarsResolved.make(resolved); + } + + // Step 3: Single-component name — defer to runtime root matching. + const string::size_type dotPos = target.find('.'); + const string firstComp = (dotPos != string::npos) ? target.substr(0, dotPos) : target; + + if (dotPos == string::npos) return kDumpvarsRuntimeRoot.make(target); + + // Step 4: Multi-component "X.y.z" where X might be the runtime root. + const string remaining = target.substr(dotPos + 1); + if (dumpvarsHasBareTarget(targetsp, firstComp)) { + string runtimeBaddot; + VSymEnt* runtimeMatchSymp = nullptr; + if (m_statep->findDotted(fl, m_statep->rootEntp(), remaining, runtimeBaddot, + runtimeMatchSymp, true)) { + return kDumpvarsRuntimeRoot.make(target); + } + return kDumpvarsMissing.make(target); + } + + UINFO(5, "$dumpvars target '" << target << "' not found in hierarchy" << endl); + return target; + } + // METHODS - Variables AstVar* createImplicitVar(VSymEnt* /*lookupSymp*/, AstParseRef* nodep, AstNodeModule* modp, VSymEnt* moduleSymp, bool noWarn) { @@ -6064,19 +6195,17 @@ class LinkDotResolveVisitor final : public VNVisitor { for (AstNode* targetp = targetsp; targetp;) { AstNode* const nextp = targetp->nextp(); if (nextp) nextp->unlinkFrBackWithNext(); - const string target = dumpvarsTargetText(targetp); - if (!target.empty() && m_curSymp) { - string baddot; - VSymEnt* matchSymp = nullptr; - if (!m_statep->findDotted(nodep->fileline(), m_curSymp, target, - baddot, matchSymp, true)) { - UINFO(5, "$dumpvars target '" << target - << "' not found in hierarchy" << endl); - } + // Skip if already resolved to text. + if (VN_IS(targetp, Text)) { + newTargetsp = AstNode::addNextNull(newTargetsp, targetp); + targetp = nextp; + continue; } + const string target = dumpvarsTargetText(targetp); + const string linkedTarget = resolveDumpvarsTarget(nodep->fileline(), target, targetsp); VL_DO_DANGLING(pushDeletep(targetp), targetp); newTargetsp - = AstNode::addNextNull(newTargetsp, new AstText{nodep->fileline(), target}); + = AstNode::addNextNull(newTargetsp, new AstText{nodep->fileline(), linkedTarget}); targetp = nextp; } relinker.relink(newTargetsp); diff --git a/src/V3LinkDot.h b/src/V3LinkDot.h index 257d522c3..e873dcef3 100644 --- a/src/V3LinkDot.h +++ b/src/V3LinkDot.h @@ -21,6 +21,7 @@ #include "verilatedos.h" #include "V3Ast.h" +#include "V3Dumpvars.h" #include "V3Error.h" //============================================================================ diff --git a/src/V3ParseGrammar.cpp b/src/V3ParseGrammar.cpp index 5ba13aba5..fdc0e218b 100644 --- a/src/V3ParseGrammar.cpp +++ b/src/V3ParseGrammar.cpp @@ -96,13 +96,6 @@ AstArg* V3ParseGrammar::argWrapList(AstNodeExpr* nodep) { return outp; } -AstDumpCtl* V3ParseGrammar::createDumpVarsScoped(FileLine* fl, AstNodeExpr* levelp, - AstNode* exprListp) { - AstDumpCtl* const resultp = new AstDumpCtl{fl, VDumpCtlType::VARS, levelp}; - resultp->addTargetsp(exprListp); - return resultp; -} - AstAssignW* V3ParseGrammar::createSupplyExpr(FileLine* fileline, const string& name, int value) { AstAssignW* assignp = new AstAssignW{fileline, new AstParseRef{fileline, name}, value ? new AstConst{fileline, AstConst::All1{}} diff --git a/src/V3ParseGrammar.h b/src/V3ParseGrammar.h index 5f4f28b86..276ed2ffb 100644 --- a/src/V3ParseGrammar.h +++ b/src/V3ParseGrammar.h @@ -67,8 +67,6 @@ public: // METHODS AstArg* argWrapList(AstNodeExpr* nodep) VL_MT_DISABLED; - AstDumpCtl* createDumpVarsScoped(FileLine* fl, AstNodeExpr* levelp, - AstNode* exprListp) VL_MT_DISABLED; bool allTracingOn(const FileLine* fl) const { return v3Global.opt.trace() && m_tracingParse && fl->tracingOn(); } diff --git a/src/V3Task.cpp b/src/V3Task.cpp index 32ae1ee83..66fe415be 100644 --- a/src/V3Task.cpp +++ b/src/V3Task.cpp @@ -1598,28 +1598,33 @@ class TaskVisitor final : public VNVisitor { beginp = createInlinedFTask(nodep, namePrefix, outvscp); ++m_statInlines; } - // When a function call has inlinedDots (from V3Inline's cell hierarchy), - // propagate that info to: + // Propagate the caller scope into the cloned task body so scope-sensitive + // operations such as $dumpvars reflect the call site even when the task + // was defined at $unit. When V3Inline added extra hierarchy, include it. + // This applies to: // 1. Any AstDumpCtl/AstScopeName in the inlined body (direct $dumpvars) // 2. Any nested AstNodeFTaskRef in the inlined body (indirect $dumpvars) - if (!nodep->inlinedDots().empty()) { + { const string& callerDots = nodep->inlinedDots(); - string dots = callerDots; - string::size_type pos; - while ((pos = dots.find('.')) != string::npos) dots.replace(pos, 1, "__DOT__"); - const string scopePath = "__DOT__"s + m_scopep->name() + "__DOT__" + dots; + string scopePath = "__DOT__"s + m_scopep->name(); + if (!callerDots.empty()) { + string dots = callerDots; + string::size_type pos; + while ((pos = dots.find('.')) != string::npos) dots.replace(pos, 1, "__DOT__"); + scopePath += "__DOT__" + dots; + } beginp->foreachAndNext([&](AstDumpCtl* dcp) { if (AstScopeName* const snp = dcp->scopeNamep()) { snp->scopeAttr(scopePath); snp->scopeEntr(scopePath); } }); - // Propagate inlinedDots to nested task references - beginp->foreachAndNext([&](AstNodeFTaskRef* refp) { - if (refp->inlinedDots().empty()) { - refp->inlinedDots(callerDots); - } - }); + if (!callerDots.empty()) { + // Propagate inlinedDots to nested task references. + beginp->foreachAndNext([&](AstNodeFTaskRef* refp) { + if (refp->inlinedDots().empty()) refp->inlinedDots(callerDots); + }); + } } if (VN_IS(nodep, New)) { // New not legal as while() condition diff --git a/src/verilog.y b/src/verilog.y index 38ae6e802..f4d6d8775 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -4215,15 +4215,17 @@ system_t_stmt_call: // IEEE: part of system_tf_call (as task returni // | yD_DUMPPORTS '(' idDottedSel ',' expr ')' { $$ = new AstDumpCtl{$1, VDumpCtlType::FILE, $5}; DEL($3); $$->addNext(new AstDumpCtl{$1, VDumpCtlType::VARS, - new AstConst{$1, 1}}); } + new AstConst{$1, 0}}); } | yD_DUMPPORTS '(' ',' expr ')' { $$ = new AstDumpCtl{$1, VDumpCtlType::FILE, $4}; $$->addNext(new AstDumpCtl{$1, VDumpCtlType::VARS, - new AstConst{$1, 1}}); } + new AstConst{$1, 0}}); } | yD_DUMPFILE '(' expr ')' { $$ = new AstDumpCtl{$1, VDumpCtlType::FILE, $3}; } | yD_DUMPVARS parenE { $$ = new AstDumpCtl{$1, VDumpCtlType::VARS, new AstConst{$1, 0}}; } | yD_DUMPVARS '(' expr ')' { $$ = new AstDumpCtl{$1, VDumpCtlType::VARS, $3}; } - | yD_DUMPVARS '(' expr ',' exprList ')' { $$ = GRAMMARP->createDumpVarsScoped($1, $3, $5); } + | yD_DUMPVARS '(' expr ',' exprList ')' { AstDumpCtl* const dumpctlp = new AstDumpCtl{$1, VDumpCtlType::VARS, $3}; + dumpctlp->addTargetsp($5); + $$ = dumpctlp; } | yD_DUMPALL parenE { $$ = new AstDumpCtl{$1, VDumpCtlType::ALL}; } | yD_DUMPALL '(' expr ')' { $$ = new AstDumpCtl{$1, VDumpCtlType::ALL}; DEL($3); } | yD_DUMPFLUSH parenE { $$ = new AstDumpCtl{$1, VDumpCtlType::FLUSH}; } diff --git a/test_regress/t/t_trace_dumpvars.out b/test_regress/t/t_trace_dumpvars.out index 652dd879a..6531d5f6a 100644 --- a/test_regress/t/t_trace_dumpvars.out +++ b/test_regress/t/t_trace_dumpvars.out @@ -1,6 +1,7 @@ $version Generated by VerilatedVcd $end $timescale 1ps $end $scope module $rootio $end + $var wire 1 % clk $end $upscope $end $scope module t $end $var wire 1 % clk $end diff --git a/test_regress/t/t_trace_dumpvars_context.out b/test_regress/t/t_trace_dumpvars_context.out new file mode 100644 index 000000000..ddf8ae798 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_context.out @@ -0,0 +1,31 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $var wire 32 ( top [31:0] $end + $scope module sub_a $end + $scope module deep_i $end + $var wire 32 * ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 $ inner [31:0] $end + $upscope $end + $upscope $end + $scope module sub_b $end + $scope module deep_i $end + $var wire 32 , ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 & inner [31:0] $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 " +b00000000000000000000000000001011 $ +b00000000000000000000000000010101 & +b00000000000000000000000000000000 ( +b00000000000000000000000000001011 * +b00000000000000000000000000010101 , diff --git a/test_regress/t/t_trace_dumpvars_context.py b/test_regress/t/t_trace_dumpvars_context.py new file mode 100644 index 000000000..1a77562e4 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_context.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--binary --trace-vcd']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() \ No newline at end of file diff --git a/test_regress/t/t_trace_dumpvars_context.v b/test_regress/t/t_trace_dumpvars_context.v new file mode 100644 index 000000000..25c14eb3a --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_context.v @@ -0,0 +1,57 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + int top; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // First restrict to sub_a.deep_i only, then let deep_i issue $dumpvars(0) + // to confirm the no-target override still expands tracing globally. + $dumpvars(1, t.sub_a.deep_i); + $dumpvars(0, top); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + deep #(ADD + 1) deep_i(.*); +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; + + initial begin + $dumpvars(0); + end +endmodule \ No newline at end of file diff --git a/test_regress/t/t_trace_dumpvars_cpptop.cpp b/test_regress/t/t_trace_dumpvars_cpptop.cpp new file mode 100644 index 000000000..5ae47110a --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop.cpp @@ -0,0 +1,36 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +// +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-License-Identifier: CC0-1.0 + +#include + +#include + +#include VM_PREFIX_INCLUDE + +unsigned long long main_time = 0; +double sc_time_stamp() { return (double)main_time; } + +int main(int argc, char** argv) { + Verilated::debug(0); + Verilated::traceEverOn(true); + Verilated::commandArgs(argc, argv); + + // Name the top module "cpptop" instead of default "TOP" + std::unique_ptr top{new VM_PREFIX{"cpptop"}}; + top->clk = 0; + + while (!Verilated::gotFinish()) { + top->eval(); + ++main_time; + top->clk = !top->clk; + } + top->final(); + top.reset(); + printf("*-* All Finished *-*\n"); + return 0; +} diff --git a/test_regress/t/t_trace_dumpvars_cpptop.out b/test_regress/t/t_trace_dumpvars_cpptop.out new file mode 100644 index 000000000..e80569743 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop.out @@ -0,0 +1,69 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module cpptop $end + $var wire 1 % clk $end + $scope module t $end + $var wire 1 % clk $end + $var wire 32 " cyc [31:0] $end + $scope module sub_a $end + $var wire 32 & ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 # value [31:0] $end + $upscope $end + $scope module sub_b $end + $var wire 32 ' ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 $ value [31:0] $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 " +b00000000000000000000000000001010 # +b00000000000000000000000000010100 $ +0% +b00000000000000000000000000001010 & +b00000000000000000000000000010100 ' +#1 +b00000000000000000000000000000001 " +b00000000000000000000000000001011 # +b00000000000000000000000000010101 $ +1% +#2 +0% +#3 +b00000000000000000000000000000010 " +b00000000000000000000000000001100 # +b00000000000000000000000000010110 $ +1% +#4 +0% +#5 +b00000000000000000000000000000011 " +b00000000000000000000000000001101 # +b00000000000000000000000000010111 $ +1% +#6 +0% +#7 +b00000000000000000000000000000100 " +b00000000000000000000000000001110 # +b00000000000000000000000000011000 $ +1% +#8 +0% +#9 +b00000000000000000000000000000101 " +b00000000000000000000000000001111 # +b00000000000000000000000000011001 $ +1% +#10 +0% +#11 +b00000000000000000000000000000110 " +b00000000000000000000000000010000 # +b00000000000000000000000000011010 $ +1% diff --git a/test_regress/t/t_trace_dumpvars_cpptop.py b/test_regress/t/t_trace_dumpvars_cpptop.py new file mode 100644 index 000000000..86c9329f9 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + make_main=False, + verilator_flags2=[ + '--cc', + '--exe', + '--trace-vcd', + 't/t_trace_dumpvars_cpptop.cpp', + ]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_cpptop.v b/test_regress/t/t_trace_dumpvars_cpptop.v new file mode 100644 index 000000000..36d6717b4 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop.v @@ -0,0 +1,39 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // cpptop is defined in the C++ testbench as the root of the trace hierarchy, so $dumpvars(0, cpptop) should dump everything. + $dumpvars(0, cpptop); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop2.cpp b/test_regress/t/t_trace_dumpvars_cpptop2.cpp new file mode 100644 index 000000000..5ae47110a --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop2.cpp @@ -0,0 +1,36 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +// +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-License-Identifier: CC0-1.0 + +#include + +#include + +#include VM_PREFIX_INCLUDE + +unsigned long long main_time = 0; +double sc_time_stamp() { return (double)main_time; } + +int main(int argc, char** argv) { + Verilated::debug(0); + Verilated::traceEverOn(true); + Verilated::commandArgs(argc, argv); + + // Name the top module "cpptop" instead of default "TOP" + std::unique_ptr top{new VM_PREFIX{"cpptop"}}; + top->clk = 0; + + while (!Verilated::gotFinish()) { + top->eval(); + ++main_time; + top->clk = !top->clk; + } + top->final(); + top.reset(); + printf("*-* All Finished *-*\n"); + return 0; +} diff --git a/test_regress/t/t_trace_dumpvars_cpptop2.out b/test_regress/t/t_trace_dumpvars_cpptop2.out new file mode 100644 index 000000000..a7c3702fa --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop2.out @@ -0,0 +1,2 @@ +%Error: t/t_trace_dumpvars_cpptop2.v:27: $dumpvars target not found: cpptop.notfound +Aborting... diff --git a/test_regress/t/t_trace_dumpvars_cpptop2.py b/test_regress/t/t_trace_dumpvars_cpptop2.py new file mode 100644 index 000000000..01cc8352d --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop2.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + make_main=False, + verilator_flags2=[ + '--cc', + '--exe', + '--trace-vcd', + 't/t_trace_dumpvars_cpptop.cpp', + ]) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_cpptop2.v b/test_regress/t/t_trace_dumpvars_cpptop2.v new file mode 100644 index 000000000..a25586b07 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop2.v @@ -0,0 +1,38 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + $dumpvars(0, cpptop, cpptop.notfound); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_hier_array.out b/test_regress/t/t_trace_dumpvars_hier_array.out new file mode 100644 index 000000000..f05e7add6 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_hier_array.out @@ -0,0 +1,24 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $scope module arr[0] $end + $scope module deep $end + $upscope $end + $upscope $end + $scope module arr[1] $end + $scope module deep $end + $var wire 32 ' ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 $ inner [31:0] $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 " +b00000000000000000000000000001011 $ +b00000000000000000000000000001011 ' diff --git a/test_regress/t/t_trace_dumpvars_hier_array.py b/test_regress/t/t_trace_dumpvars_hier_array.py new file mode 100644 index 000000000..1eaecdb79 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_hier_array.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--binary --trace-vcd']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_hier_array.v b/test_regress/t/t_trace_dumpvars_hier_array.v new file mode 100644 index 000000000..6e211074f --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_hier_array.v @@ -0,0 +1,49 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + + sub #(10) arr[2](.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // Test $dumpvars with an arrayed hierarchical scope path. + $dumpvars(1, t.arr[1].deep); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + deep #(ADD + 1) deep(.*); +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_hier_global.out b/test_regress/t/t_trace_dumpvars_hier_global.out new file mode 100644 index 000000000..546cc253e --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_hier_global.out @@ -0,0 +1,26 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $var wire 1 ' clk $end + $var wire 32 " cyc [31:0] $end + $scope module sub_a $end + $scope module deep_i $end + $var wire 32 * t [31:0] $end + $upscope $end + $upscope $end + $scope module sub_b $end + $scope module deep_i $end + $var wire 32 - t [31:0] $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 " +0' +b00000000000000000000000000000000 * +b00000000000000000000000000000000 - diff --git a/test_regress/t/t_trace_dumpvars_hier_global.py b/test_regress/t/t_trace_dumpvars_hier_global.py new file mode 100644 index 000000000..1eaecdb79 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_hier_global.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--binary --trace-vcd']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_hier_global.v b/test_regress/t/t_trace_dumpvars_hier_global.v new file mode 100644 index 000000000..e7a8ed84c --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_hier_global.v @@ -0,0 +1,56 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + deep #(ADD + 1) deep_i(.*); + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // Test $dumpvars with hierarchical scope: level 1 limits to direct signals of t outside the scope + $dumpvars(1, t); + end +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + int t; + always_comb inner = cyc + ADD; + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + $dumpvars(1, t); + end +endmodule diff --git a/test_regress/t/t_trace_dumpvars_hier_global_task.out b/test_regress/t/t_trace_dumpvars_hier_global_task.out new file mode 100644 index 000000000..934e212b9 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_hier_global_task.out @@ -0,0 +1,26 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $var wire 1 ' clk $end + $var wire 32 " cyc [31:0] $end + $scope module sub_a $end + $scope module deep_i $end + $var wire 32 * t [31:0] $end + $upscope $end + $upscope $end + $scope module sub_b $end + $scope module deep_i $end + $var wire 32 - t [31:0] $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 " +0' +b00000000000000000000000000000000 * +b00000000000000000000000000000000 - diff --git a/test_regress/t/t_trace_dumpvars_hier_global_task.py b/test_regress/t/t_trace_dumpvars_hier_global_task.py new file mode 100644 index 000000000..a58724bfa --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_hier_global_task.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--binary --trace-vcd --fno-inline']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_hier_global_task.v b/test_regress/t/t_trace_dumpvars_hier_global_task.v new file mode 100644 index 000000000..1fb855231 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_hier_global_task.v @@ -0,0 +1,71 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + function void dump_from_func; + $dumpvars(1, t); + endfunction + + task setup_trace; + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + dump_from_func(); + endtask + + deep #(ADD + 1) deep_i(.*); + + initial begin + setup_trace(); + end +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + int t; + always_comb inner = cyc + ADD; + + function void dump_from_func; + $dumpvars(1, t); + endfunction + + task setup_trace; + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + dump_from_func(); + endtask + + initial begin + setup_trace(); + end +endmodule diff --git a/test_regress/t/t_trace_dumpvars_hier_struct.out b/test_regress/t/t_trace_dumpvars_hier_struct.out new file mode 100644 index 000000000..40ed30d89 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_hier_struct.out @@ -0,0 +1,20 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $scope module mystruct $end + $scope module deep $end + $var wire 32 ' add [31:0] $end + $var wire 32 # cyc [31:0] $end + $var wire 32 $ inner [31:0] $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 # +b00000000000000000000000000001011 $ +b00000000000000000000000000001011 ' diff --git a/test_regress/t/t_trace_dumpvars_hier_struct.py b/test_regress/t/t_trace_dumpvars_hier_struct.py new file mode 100644 index 000000000..6c7291a29 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_hier_struct.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--binary --trace-vcd --trace-structs']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() \ No newline at end of file diff --git a/test_regress/t/t_trace_dumpvars_hier_struct.v b/test_regress/t/t_trace_dumpvars_hier_struct.v new file mode 100644 index 000000000..dab0cd207 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_hier_struct.v @@ -0,0 +1,46 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +typedef struct packed { + logic [31:0] add; + logic [31:0] cyc; + logic [31:0] inner; +} deep_t; + +typedef struct packed { + deep_t deep; + logic [31:0] value; +} top_t; + +module t( + input clk +); + int cyc; + top_t mystruct; + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // Test $dumpvars with a traced struct sub-scope. + $dumpvars(1, t.mystruct.deep); + end + + always_comb begin + mystruct.value = cyc + 32'd10; + mystruct.deep.add = 32'd11; + mystruct.deep.cyc = cyc; + mystruct.deep.inner = cyc + mystruct.deep.add; + end +endmodule \ No newline at end of file diff --git a/test_regress/t/t_trace_dumpvars_missing_scope.out b/test_regress/t/t_trace_dumpvars_missing_scope.out index 8bda5d834..52442ede3 100644 --- a/test_regress/t/t_trace_dumpvars_missing_scope.out +++ b/test_regress/t/t_trace_dumpvars_missing_scope.out @@ -1,15 +1,2 @@ -$version Generated by VerilatedVcd $end -$timescale 1ps $end - $scope module $rootio $end - $upscope $end - $scope module t $end - $scope module sub_a $end - $scope module deep_i $end - $upscope $end - $upscope $end - $scope module sub_b $end - $scope module deep_i $end - $upscope $end - $upscope $end - $upscope $end -$enddefinitions $end +%Error: t/t_trace_dumpvars_missing_scope.v:28: $dumpvars target not found: missing_module +Aborting... diff --git a/test_regress/t/t_trace_dumpvars_missing_scope.py b/test_regress/t/t_trace_dumpvars_missing_scope.py index d38577388..84fe07456 100644 --- a/test_regress/t/t_trace_dumpvars_missing_scope.py +++ b/test_regress/t/t_trace_dumpvars_missing_scope.py @@ -13,9 +13,6 @@ test.scenarios('vlt') test.compile(verilator_flags2=['--binary --trace-vcd']) -test.execute() - -test.file_grep(test.trace_filename, r'^\$enddefinitions \$end') -test.file_grep_not(test.trace_filename, r'^\s*\$var\s') +test.execute(fails=True, expect_filename=test.golden_filename) test.passes() diff --git a/test_regress/t/t_trace_dumpvars_override.out b/test_regress/t/t_trace_dumpvars_override.out index 2d2474dc9..cc85ab270 100644 --- a/test_regress/t/t_trace_dumpvars_override.out +++ b/test_regress/t/t_trace_dumpvars_override.out @@ -1,6 +1,7 @@ $version Generated by VerilatedVcd $end $timescale 1ps $end $scope module $rootio $end + $var wire 1 ' clk $end $upscope $end $scope module t $end $var wire 1 ' clk $end diff --git a/test_regress/t/t_trace_dumpvars_struct.out b/test_regress/t/t_trace_dumpvars_struct.out index 48d50a1af..0c114640d 100644 --- a/test_regress/t/t_trace_dumpvars_struct.out +++ b/test_regress/t/t_trace_dumpvars_struct.out @@ -3,22 +3,16 @@ $timescale 1ps $end $scope module $rootio $end $upscope $end $scope module t $end - $var wire 1 * clk $end - $var wire 32 " cyc [31:0] $end - $scope module rect $end - $scope module origin $end - $var wire 8 # x [7:0] $end - $var wire 8 $ y [7:0] $end - $upscope $end - $scope module size $end - $var wire 8 % x [7:0] $end - $var wire 8 & y [7:0] $end - $upscope $end - $upscope $end - $scope module pt $end - $var wire 8 ' x [7:0] $end - $var wire 8 ( y [7:0] $end - $upscope $end + $scope module rect $end + $scope module origin $end + $var wire 8 # x [7:0] $end + $upscope $end + $scope module size $end + $upscope $end + $upscope $end + $scope module pt $end + $var wire 8 ( y [7:0] $end + $upscope $end $scope module sub_a $end $upscope $end $upscope $end @@ -26,11 +20,5 @@ $enddefinitions $end #0 -b00000000000000000000000000000000 " b00000000 # -b00000000 $ -b00000000 % -b00000000 & -b00000000 ' b00000000 ( -0* diff --git a/test_regress/t/t_trace_dumpvars_struct.v b/test_regress/t/t_trace_dumpvars_struct.v index 132e3438f..d2748684c 100644 --- a/test_regress/t/t_trace_dumpvars_struct.v +++ b/test_regress/t/t_trace_dumpvars_struct.v @@ -10,7 +10,7 @@ module t( input clk ); typedef struct packed { - logic [7:0] x; + logic [7:0] \x ; logic [7:0] y; } point_t; @@ -21,17 +21,17 @@ module t( int cyc; rect_t rect; - point_t pt; + point_t \pt ; sub #(10) sub_a(.*); always @(posedge clk) begin cyc <= cyc + 1; - pt.x <= pt.x + 1; - pt.y <= pt.y + 2; - rect.origin.x <= rect.origin.x + 1; + \pt .\x <= \pt .\x + 1; + \pt .y <= \pt .y + 2; + rect.origin.\x <= rect.origin.\x + 1; rect.origin.y <= rect.origin.y + 2; - rect.size.x <= 8'd100; + rect.size.\x <= 8'd100; rect.size.y <= 8'd200; if (cyc == 5) begin $write("*-* All Finished *-*\n"); @@ -41,9 +41,9 @@ module t( initial begin $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Level 1 counts only module nesting, so nested struct members under t - // are dumped, but sub_a's signals are still excluded. - $dumpvars(1); + // Target a single escaped struct member in $dumpvars. + $dumpvars(1, rect.origin.\x ); + $dumpvars(1, \pt .\y ); end endmodule diff --git a/test_regress/t/t_trace_dumpvars_task2_no_inl.out b/test_regress/t/t_trace_dumpvars_task2_no_inl.out new file mode 100644 index 000000000..73b55a8a8 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_task2_no_inl.out @@ -0,0 +1,29 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $scope module sub_a $end + $var wire 32 ( ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 # value [31:0] $end + $scope module deep_i $end + $upscope $end + $upscope $end + $scope module sub_b $end + $var wire 32 * ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 % value [31:0] $end + $scope module deep_i $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 " +b00000000000000000000000000001010 # +b00000000000000000000000000010100 % +b00000000000000000000000000001010 ( +b00000000000000000000000000010100 * diff --git a/test_regress/t/t_trace_dumpvars_task2_no_inl.py b/test_regress/t/t_trace_dumpvars_task2_no_inl.py new file mode 100644 index 000000000..a58724bfa --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_task2_no_inl.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--binary --trace-vcd --fno-inline']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_task2_no_inl.v b/test_regress/t/t_trace_dumpvars_task2_no_inl.v new file mode 100644 index 000000000..6b0fe071e --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_task2_no_inl.v @@ -0,0 +1,65 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +function int get_trace_level; + return 1; +endfunction + +function void varsdump; + $dumpvars(get_trace_level()); +endfunction + +task setup_trace; + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + varsdump(); +endtask + +task setup_trace_nested; + setup_trace(); +endtask + +module t( + input clk +); + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + initial begin + setup_trace_nested; + end + + deep #(ADD + 1) deep_i(.*); +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_task_no_inl.out b/test_regress/t/t_trace_dumpvars_task_no_inl.out new file mode 100644 index 000000000..73b55a8a8 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_task_no_inl.out @@ -0,0 +1,29 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $scope module sub_a $end + $var wire 32 ( ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 # value [31:0] $end + $scope module deep_i $end + $upscope $end + $upscope $end + $scope module sub_b $end + $var wire 32 * ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 % value [31:0] $end + $scope module deep_i $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 " +b00000000000000000000000000001010 # +b00000000000000000000000000010100 % +b00000000000000000000000000001010 ( +b00000000000000000000000000010100 * diff --git a/test_regress/t/t_trace_dumpvars_task_no_inl.py b/test_regress/t/t_trace_dumpvars_task_no_inl.py new file mode 100644 index 000000000..a58724bfa --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_task_no_inl.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--binary --trace-vcd --fno-inline']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_task_no_inl.v b/test_regress/t/t_trace_dumpvars_task_no_inl.v new file mode 100644 index 000000000..74e64feb7 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_task_no_inl.v @@ -0,0 +1,61 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +function int get_trace_level; + return 1; +endfunction + +function void varsdump; + $dumpvars(get_trace_level()); +endfunction + +task setup_trace; + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + varsdump(); +endtask + +module t( + input clk +); + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + initial begin + setup_trace; + end + + deep #(ADD + 1) deep_i(.*); +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_event.v b/test_regress/t/t_trace_event.v index 4837399a8..925e68f7f 100644 --- a/test_regress/t/t_trace_event.v +++ b/test_regress/t/t_trace_event.v @@ -26,7 +26,7 @@ module t; initial begin $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - $dumpvars(0, top); + $dumpvars(0); for (i = 0; i < 10; i++) begin @(posedge clk); diff --git a/test_regress/t/t_trace_two_a.v b/test_regress/t/t_trace_two_a.v index f27143641..ad2ecd3a1 100644 --- a/test_regress/t/t_trace_two_a.v +++ b/test_regress/t/t_trace_two_a.v @@ -26,9 +26,9 @@ module t ( `ifdef TEST_DUMP $dumpfile(filename); - $dumpvars(0); // Intentionally no ", top" for parsing coverage with just (expr) - $dumpvars(1, top); // Intentionally checking parsing coverage - $dumpvars(1, top, top); // Intentionally checking parsing coverage + $dumpvars(0); // Intentionally no ", topa" for parsing coverage with just (expr) + $dumpvars(1, topa); // Intentionally checking parsing coverage + $dumpvars(1, topa, topa); // Intentionally checking parsing coverage $dumplimit(10 * 1024 * 1024); `elsif TEST_DUMPPORTS $dumpports(top, filename); From 2e4fb380e1b3401c0d9b80c43766cfc921d3a59e Mon Sep 17 00:00:00 2001 From: wsxarcher Date: Tue, 24 Mar 2026 00:20:42 +0100 Subject: [PATCH 03/13] Error compile time --- src/V3Dumpvars.h | 4 +--- src/V3EmitCFunc.h | 13 +------------ src/V3LinkDot.cpp | 15 ++++++++++++--- test_regress/t/t_trace_dumpvars_cpptop.v | 2 +- test_regress/t/t_trace_dumpvars_cpptop2.out | 7 +++++-- test_regress/t/t_trace_dumpvars_cpptop2.py | 6 +++--- test_regress/t/t_trace_dumpvars_missing_scope.out | 7 +++++-- test_regress/t/t_trace_dumpvars_missing_scope.py | 5 ++--- 8 files changed, 30 insertions(+), 29 deletions(-) diff --git a/src/V3Dumpvars.h b/src/V3Dumpvars.h index 58b200369..29c7eaf41 100644 --- a/src/V3Dumpvars.h +++ b/src/V3Dumpvars.h @@ -22,10 +22,9 @@ // Tagged $dumpvars target string. During compile-time resolution in V3LinkDot // each target is tagged with a prefix that tells EmitC how to emit the -// corresponding runtime code. The three tag types are: +// corresponding runtime code. The tag types are: // Resolved – fully resolved to a compile-time hierarchy path // RuntimeRoot – first component must match the C++ wrapper root name at runtime -// Missing – proven invalid at compile time; emit VL_FATAL_MT at runtime struct DumpvarsTag final { const char* const prefix; const size_t prefixLen; @@ -42,6 +41,5 @@ struct DumpvarsTag final { constexpr DumpvarsTag kDumpvarsResolved{"@dumpvars:"}; constexpr DumpvarsTag kDumpvarsRuntimeRoot{"@dumpvars_root:"}; -constexpr DumpvarsTag kDumpvarsMissing{"@dumpvars_missing:"}; #endif // Guard diff --git a/src/V3EmitCFunc.h b/src/V3EmitCFunc.h index 0a6d0bd07..f035a867f 100644 --- a/src/V3EmitCFunc.h +++ b/src/V3EmitCFunc.h @@ -951,15 +951,6 @@ public: puts(levelExpr); puts(", __vlDvHier); }\n"); } - void emitDumpVarsTargetMissing(const AstDumpCtl* nodep, const string& target) { - putns(nodep, "VL_FATAL_MT(\""); - puts(V3OutFormatter::quoteNameControls(protect(nodep->fileline()->filename()))); - puts("\", "); - puts(cvtToStr(nodep->fileline()->lineno())); - puts(", \"\", \"$dumpvars target not found: "); - puts(V3OutFormatter::quoteNameControls(target)); - puts("\");\n"); - } // Emit $dumpvars filter logic when scope info is available. void emitDumpVarsWithScope(AstDumpCtl* nodep) { UASSERT_OBJ(nodep->scopeNamep(), nodep, "$dumpvars missing AstScopeName"); @@ -981,9 +972,7 @@ public: if (nodep->targetsp()) { for (AstNode* tp = nodep->targetsp(); tp; tp = tp->nextp()) { const string target = VN_AS(tp, Text)->text(); - if (kDumpvarsMissing.matches(target)) { - emitDumpVarsTargetMissing(nodep, kDumpvarsMissing.strip(target)); - } else if (kDumpvarsRuntimeRoot.matches(target)) { + if (kDumpvarsRuntimeRoot.matches(target)) { emitDumpVarsAddRuntimeRoot(nodep, kDumpvarsRuntimeRoot.strip(target), levelExpr); } else { diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index 281c289d2..200cf76da 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -3272,11 +3272,19 @@ class LinkDotResolveVisitor final : public VNVisitor { if (!resolved.empty()) return kDumpvarsResolved.make(resolved); } - // Step 3: Single-component name — defer to runtime root matching. + // Step 3: Single-component name — defer to runtime root matching + // unless Verilator generates the main (--main/--binary), in which case + // the root name is known at compile time and we can reject mismatches. const string::size_type dotPos = target.find('.'); const string firstComp = (dotPos != string::npos) ? target.substr(0, dotPos) : target; - if (dotPos == string::npos) return kDumpvarsRuntimeRoot.make(target); + if (dotPos == string::npos) { + if (v3Global.opt.main()) { + fl->v3error("$dumpvars target not found: " << target); + return target; + } + return kDumpvarsRuntimeRoot.make(target); + } // Step 4: Multi-component "X.y.z" where X might be the runtime root. const string remaining = target.substr(dotPos + 1); @@ -3287,7 +3295,8 @@ class LinkDotResolveVisitor final : public VNVisitor { runtimeMatchSymp, true)) { return kDumpvarsRuntimeRoot.make(target); } - return kDumpvarsMissing.make(target); + fl->v3error("$dumpvars target not found: " << target); + return target; } UINFO(5, "$dumpvars target '" << target << "' not found in hierarchy" << endl); diff --git a/test_regress/t/t_trace_dumpvars_cpptop.v b/test_regress/t/t_trace_dumpvars_cpptop.v index 36d6717b4..42a8df11c 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop.v +++ b/test_regress/t/t_trace_dumpvars_cpptop.v @@ -25,7 +25,7 @@ module t( initial begin $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); // cpptop is defined in the C++ testbench as the root of the trace hierarchy, so $dumpvars(0, cpptop) should dump everything. - $dumpvars(0, cpptop); + $dumpvars(0, cpptop, cpptop.t); end endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop2.out b/test_regress/t/t_trace_dumpvars_cpptop2.out index a7c3702fa..7660a7232 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop2.out +++ b/test_regress/t/t_trace_dumpvars_cpptop2.out @@ -1,2 +1,5 @@ -%Error: t/t_trace_dumpvars_cpptop2.v:27: $dumpvars target not found: cpptop.notfound -Aborting... +%Error: t/t_trace_dumpvars_cpptop2.v:27:5: $dumpvars target not found: cpptop.notfound + 27 | $dumpvars(0, cpptop, cpptop.notfound); + | ^~~~~~~~~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: Exiting due to diff --git a/test_regress/t/t_trace_dumpvars_cpptop2.py b/test_regress/t/t_trace_dumpvars_cpptop2.py index 01cc8352d..eab934d19 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop2.py +++ b/test_regress/t/t_trace_dumpvars_cpptop2.py @@ -12,14 +12,14 @@ import vltest_bootstrap test.scenarios('vlt') test.compile( + fails=True, make_main=False, verilator_flags2=[ '--cc', '--exe', '--trace-vcd', 't/t_trace_dumpvars_cpptop.cpp', - ]) - -test.execute(fails=True, expect_filename=test.golden_filename) + ], + expect_filename=test.golden_filename) test.passes() diff --git a/test_regress/t/t_trace_dumpvars_missing_scope.out b/test_regress/t/t_trace_dumpvars_missing_scope.out index 52442ede3..7272e6db5 100644 --- a/test_regress/t/t_trace_dumpvars_missing_scope.out +++ b/test_regress/t/t_trace_dumpvars_missing_scope.out @@ -1,2 +1,5 @@ -%Error: t/t_trace_dumpvars_missing_scope.v:28: $dumpvars target not found: missing_module -Aborting... +%Error: t/t_trace_dumpvars_missing_scope.v:28:5: $dumpvars target not found: missing_module + 28 | $dumpvars(0, missing_module); + | ^~~~~~~~~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: Exiting due to diff --git a/test_regress/t/t_trace_dumpvars_missing_scope.py b/test_regress/t/t_trace_dumpvars_missing_scope.py index 84fe07456..c834b7d2a 100644 --- a/test_regress/t/t_trace_dumpvars_missing_scope.py +++ b/test_regress/t/t_trace_dumpvars_missing_scope.py @@ -11,8 +11,7 @@ import vltest_bootstrap test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute(fails=True, expect_filename=test.golden_filename) +test.compile(fails=True, verilator_flags2=['--binary --trace-vcd'], + expect_filename=test.golden_filename) test.passes() From dfa57f8f88d9e25c9bc342feff31bb9fb51ba65d Mon Sep 17 00:00:00 2001 From: wsxarcher Date: Tue, 24 Mar 2026 00:36:39 +0100 Subject: [PATCH 04/13] Cleanup --- src/V3Dumpvars.h | 6 +++--- src/V3LinkDot.cpp | 4 +--- test_regress/t/t_trace_dumpvars.py | 2 +- test_regress/t/t_trace_dumpvars.v | 2 +- test_regress/t/t_trace_dumpvars_abs_scope.py | 2 +- test_regress/t/t_trace_dumpvars_abs_scope.v | 2 +- test_regress/t/t_trace_dumpvars_add_module.py | 2 +- test_regress/t/t_trace_dumpvars_add_module.v | 2 +- test_regress/t/t_trace_dumpvars_context.py | 5 +++-- test_regress/t/t_trace_dumpvars_context.v | 4 ++-- test_regress/t/t_trace_dumpvars_cpptop.cpp | 2 +- test_regress/t/t_trace_dumpvars_cpptop.py | 2 +- test_regress/t/t_trace_dumpvars_cpptop.v | 2 +- test_regress/t/t_trace_dumpvars_cpptop2.cpp | 2 +- test_regress/t/t_trace_dumpvars_cpptop2.py | 2 +- test_regress/t/t_trace_dumpvars_cpptop2.v | 2 +- test_regress/t/t_trace_dumpvars_func.py | 2 +- test_regress/t/t_trace_dumpvars_func.v | 2 +- test_regress/t/t_trace_dumpvars_hier_array.py | 2 +- test_regress/t/t_trace_dumpvars_hier_array.v | 2 +- test_regress/t/t_trace_dumpvars_hier_global.py | 2 +- test_regress/t/t_trace_dumpvars_hier_global.v | 2 +- test_regress/t/t_trace_dumpvars_hier_global_task.py | 2 +- test_regress/t/t_trace_dumpvars_hier_global_task.v | 2 +- test_regress/t/t_trace_dumpvars_hier_scope.py | 2 +- test_regress/t/t_trace_dumpvars_hier_scope.v | 2 +- test_regress/t/t_trace_dumpvars_hier_struct.py | 5 +++-- test_regress/t/t_trace_dumpvars_hier_struct.v | 4 ++-- test_regress/t/t_trace_dumpvars_level.py | 2 +- test_regress/t/t_trace_dumpvars_level.v | 2 +- test_regress/t/t_trace_dumpvars_level_scope.py | 2 +- test_regress/t/t_trace_dumpvars_level_scope.v | 2 +- test_regress/t/t_trace_dumpvars_missing_scope.py | 2 +- test_regress/t/t_trace_dumpvars_missing_scope.v | 2 +- test_regress/t/t_trace_dumpvars_multi_scope.py | 2 +- test_regress/t/t_trace_dumpvars_multi_scope.v | 2 +- test_regress/t/t_trace_dumpvars_nonconst_scope.py | 2 +- test_regress/t/t_trace_dumpvars_nonconst_scope.v | 2 +- test_regress/t/t_trace_dumpvars_override.py | 2 +- test_regress/t/t_trace_dumpvars_override.v | 2 +- test_regress/t/t_trace_dumpvars_scope.py | 2 +- test_regress/t/t_trace_dumpvars_scope.v | 2 +- test_regress/t/t_trace_dumpvars_struct.py | 2 +- test_regress/t/t_trace_dumpvars_struct.v | 2 +- test_regress/t/t_trace_dumpvars_sub.py | 2 +- test_regress/t/t_trace_dumpvars_sub.v | 2 +- test_regress/t/t_trace_dumpvars_sub0.py | 2 +- test_regress/t/t_trace_dumpvars_sub0.v | 2 +- test_regress/t/t_trace_dumpvars_task.py | 2 +- test_regress/t/t_trace_dumpvars_task.v | 2 +- test_regress/t/t_trace_dumpvars_task2.py | 2 +- test_regress/t/t_trace_dumpvars_task2.v | 2 +- test_regress/t/t_trace_dumpvars_task2_no_inl.py | 2 +- test_regress/t/t_trace_dumpvars_task2_no_inl.v | 2 +- test_regress/t/t_trace_dumpvars_task_no_inl.py | 2 +- test_regress/t/t_trace_dumpvars_task_no_inl.v | 2 +- test_regress/t/t_trace_dumpvars_wire.py | 2 +- test_regress/t/t_trace_dumpvars_wire.v | 2 +- 58 files changed, 66 insertions(+), 66 deletions(-) diff --git a/src/V3Dumpvars.h b/src/V3Dumpvars.h index 29c7eaf41..b30f86d77 100644 --- a/src/V3Dumpvars.h +++ b/src/V3Dumpvars.h @@ -22,9 +22,7 @@ // Tagged $dumpvars target string. During compile-time resolution in V3LinkDot // each target is tagged with a prefix that tells EmitC how to emit the -// corresponding runtime code. The tag types are: -// Resolved – fully resolved to a compile-time hierarchy path -// RuntimeRoot – first component must match the C++ wrapper root name at runtime +// corresponding runtime code. struct DumpvarsTag final { const char* const prefix; const size_t prefixLen; @@ -39,7 +37,9 @@ struct DumpvarsTag final { } }; +// Fully resolved to a compile-time hierarchy path constexpr DumpvarsTag kDumpvarsResolved{"@dumpvars:"}; +// First component must match the C++ wrapper root name at runtime constexpr DumpvarsTag kDumpvarsRuntimeRoot{"@dumpvars_root:"}; #endif // Guard diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index 200cf76da..2325d0a1e 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -3272,9 +3272,7 @@ class LinkDotResolveVisitor final : public VNVisitor { if (!resolved.empty()) return kDumpvarsResolved.make(resolved); } - // Step 3: Single-component name — defer to runtime root matching - // unless Verilator generates the main (--main/--binary), in which case - // the root name is known at compile time and we can reject mismatches. + // Step 3: Defer single component to root lookup if available. const string::size_type dotPos = target.find('.'); const string firstComp = (dotPos != string::npos) ? target.substr(0, dotPos) : target; diff --git a/test_regress/t/t_trace_dumpvars.py b/test_regress/t/t_trace_dumpvars.py index 1eaecdb79..d2549038e 100644 --- a/test_regress/t/t_trace_dumpvars.py +++ b/test_regress/t/t_trace_dumpvars.py @@ -4,7 +4,7 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-FileCopyrightText: 2026 Wilson Snyder # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_dumpvars.v b/test_regress/t/t_trace_dumpvars.v index 6a65753e0..5c2063a08 100644 --- a/test_regress/t/t_trace_dumpvars.v +++ b/test_regress/t/t_trace_dumpvars.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_dumpvars_abs_scope.py b/test_regress/t/t_trace_dumpvars_abs_scope.py index 1eaecdb79..e6571964d 100644 --- a/test_regress/t/t_trace_dumpvars_abs_scope.py +++ b/test_regress/t/t_trace_dumpvars_abs_scope.py @@ -4,7 +4,7 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_dumpvars_abs_scope.v b/test_regress/t/t_trace_dumpvars_abs_scope.v index aa9d28fa2..2a225c3cb 100644 --- a/test_regress/t/t_trace_dumpvars_abs_scope.v +++ b/test_regress/t/t_trace_dumpvars_abs_scope.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_dumpvars_add_module.py b/test_regress/t/t_trace_dumpvars_add_module.py index 51c1f9091..006c898da 100644 --- a/test_regress/t/t_trace_dumpvars_add_module.py +++ b/test_regress/t/t_trace_dumpvars_add_module.py @@ -4,7 +4,7 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_dumpvars_add_module.v b/test_regress/t/t_trace_dumpvars_add_module.v index 26f7acbac..bf812302c 100644 --- a/test_regress/t/t_trace_dumpvars_add_module.v +++ b/test_regress/t/t_trace_dumpvars_add_module.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_dumpvars_context.py b/test_regress/t/t_trace_dumpvars_context.py index 1a77562e4..5a79df61f 100644 --- a/test_regress/t/t_trace_dumpvars_context.py +++ b/test_regress/t/t_trace_dumpvars_context.py @@ -4,7 +4,7 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap @@ -17,4 +17,5 @@ test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) -test.passes() \ No newline at end of file +test.passes() + diff --git a/test_regress/t/t_trace_dumpvars_context.v b/test_regress/t/t_trace_dumpvars_context.v index 25c14eb3a..5bc230c54 100644 --- a/test_regress/t/t_trace_dumpvars_context.v +++ b/test_regress/t/t_trace_dumpvars_context.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" @@ -54,4 +54,4 @@ module deep #( initial begin $dumpvars(0); end -endmodule \ No newline at end of file +endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop.cpp b/test_regress/t/t_trace_dumpvars_cpptop.cpp index 5ae47110a..83ccacb87 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop.cpp +++ b/test_regress/t/t_trace_dumpvars_cpptop.cpp @@ -3,7 +3,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_trace_dumpvars_cpptop.py b/test_regress/t/t_trace_dumpvars_cpptop.py index 86c9329f9..e59720885 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop.py +++ b/test_regress/t/t_trace_dumpvars_cpptop.py @@ -4,7 +4,7 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_dumpvars_cpptop.v b/test_regress/t/t_trace_dumpvars_cpptop.v index 42a8df11c..334e709e0 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop.v +++ b/test_regress/t/t_trace_dumpvars_cpptop.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_dumpvars_cpptop2.cpp b/test_regress/t/t_trace_dumpvars_cpptop2.cpp index 5ae47110a..83ccacb87 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop2.cpp +++ b/test_regress/t/t_trace_dumpvars_cpptop2.cpp @@ -3,7 +3,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_trace_dumpvars_cpptop2.py b/test_regress/t/t_trace_dumpvars_cpptop2.py index eab934d19..b942b16fa 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop2.py +++ b/test_regress/t/t_trace_dumpvars_cpptop2.py @@ -4,7 +4,7 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_dumpvars_cpptop2.v b/test_regress/t/t_trace_dumpvars_cpptop2.v index a25586b07..4d3f29d36 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop2.v +++ b/test_regress/t/t_trace_dumpvars_cpptop2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_dumpvars_func.py b/test_regress/t/t_trace_dumpvars_func.py index 1eaecdb79..e6571964d 100644 --- a/test_regress/t/t_trace_dumpvars_func.py +++ b/test_regress/t/t_trace_dumpvars_func.py @@ -4,7 +4,7 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_dumpvars_func.v b/test_regress/t/t_trace_dumpvars_func.v index 1a5def5eb..cf70710da 100644 --- a/test_regress/t/t_trace_dumpvars_func.v +++ b/test_regress/t/t_trace_dumpvars_func.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_dumpvars_hier_array.py b/test_regress/t/t_trace_dumpvars_hier_array.py index 1eaecdb79..e6571964d 100644 --- a/test_regress/t/t_trace_dumpvars_hier_array.py +++ b/test_regress/t/t_trace_dumpvars_hier_array.py @@ -4,7 +4,7 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_dumpvars_hier_array.v b/test_regress/t/t_trace_dumpvars_hier_array.v index 6e211074f..dbe673d73 100644 --- a/test_regress/t/t_trace_dumpvars_hier_array.v +++ b/test_regress/t/t_trace_dumpvars_hier_array.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_dumpvars_hier_global.py b/test_regress/t/t_trace_dumpvars_hier_global.py index 1eaecdb79..e6571964d 100644 --- a/test_regress/t/t_trace_dumpvars_hier_global.py +++ b/test_regress/t/t_trace_dumpvars_hier_global.py @@ -4,7 +4,7 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_dumpvars_hier_global.v b/test_regress/t/t_trace_dumpvars_hier_global.v index e7a8ed84c..37dd5d357 100644 --- a/test_regress/t/t_trace_dumpvars_hier_global.v +++ b/test_regress/t/t_trace_dumpvars_hier_global.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_dumpvars_hier_global_task.py b/test_regress/t/t_trace_dumpvars_hier_global_task.py index a58724bfa..38f138c77 100644 --- a/test_regress/t/t_trace_dumpvars_hier_global_task.py +++ b/test_regress/t/t_trace_dumpvars_hier_global_task.py @@ -4,7 +4,7 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_dumpvars_hier_global_task.v b/test_regress/t/t_trace_dumpvars_hier_global_task.v index 1fb855231..5877a243c 100644 --- a/test_regress/t/t_trace_dumpvars_hier_global_task.v +++ b/test_regress/t/t_trace_dumpvars_hier_global_task.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_dumpvars_hier_scope.py b/test_regress/t/t_trace_dumpvars_hier_scope.py index 1eaecdb79..e6571964d 100644 --- a/test_regress/t/t_trace_dumpvars_hier_scope.py +++ b/test_regress/t/t_trace_dumpvars_hier_scope.py @@ -4,7 +4,7 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_dumpvars_hier_scope.v b/test_regress/t/t_trace_dumpvars_hier_scope.v index 899bbeea9..97c3bfd55 100644 --- a/test_regress/t/t_trace_dumpvars_hier_scope.v +++ b/test_regress/t/t_trace_dumpvars_hier_scope.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_dumpvars_hier_struct.py b/test_regress/t/t_trace_dumpvars_hier_struct.py index 6c7291a29..791c137e1 100644 --- a/test_regress/t/t_trace_dumpvars_hier_struct.py +++ b/test_regress/t/t_trace_dumpvars_hier_struct.py @@ -4,7 +4,7 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap @@ -17,4 +17,5 @@ test.execute() test.vcd_identical(test.trace_filename, test.golden_filename) -test.passes() \ No newline at end of file +test.passes() + diff --git a/test_regress/t/t_trace_dumpvars_hier_struct.v b/test_regress/t/t_trace_dumpvars_hier_struct.v index dab0cd207..82614345a 100644 --- a/test_regress/t/t_trace_dumpvars_hier_struct.v +++ b/test_regress/t/t_trace_dumpvars_hier_struct.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" @@ -43,4 +43,4 @@ module t( mystruct.deep.cyc = cyc; mystruct.deep.inner = cyc + mystruct.deep.add; end -endmodule \ No newline at end of file +endmodule diff --git a/test_regress/t/t_trace_dumpvars_level.py b/test_regress/t/t_trace_dumpvars_level.py index 1eaecdb79..e6571964d 100644 --- a/test_regress/t/t_trace_dumpvars_level.py +++ b/test_regress/t/t_trace_dumpvars_level.py @@ -4,7 +4,7 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_dumpvars_level.v b/test_regress/t/t_trace_dumpvars_level.v index 55c3ccc64..df73db139 100644 --- a/test_regress/t/t_trace_dumpvars_level.v +++ b/test_regress/t/t_trace_dumpvars_level.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_dumpvars_level_scope.py b/test_regress/t/t_trace_dumpvars_level_scope.py index 1eaecdb79..e6571964d 100644 --- a/test_regress/t/t_trace_dumpvars_level_scope.py +++ b/test_regress/t/t_trace_dumpvars_level_scope.py @@ -4,7 +4,7 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_dumpvars_level_scope.v b/test_regress/t/t_trace_dumpvars_level_scope.v index 64c074c27..b7863aee2 100644 --- a/test_regress/t/t_trace_dumpvars_level_scope.v +++ b/test_regress/t/t_trace_dumpvars_level_scope.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_dumpvars_missing_scope.py b/test_regress/t/t_trace_dumpvars_missing_scope.py index c834b7d2a..b00fb4934 100644 --- a/test_regress/t/t_trace_dumpvars_missing_scope.py +++ b/test_regress/t/t_trace_dumpvars_missing_scope.py @@ -4,7 +4,7 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_dumpvars_missing_scope.v b/test_regress/t/t_trace_dumpvars_missing_scope.v index aac875054..f7c24a635 100644 --- a/test_regress/t/t_trace_dumpvars_missing_scope.v +++ b/test_regress/t/t_trace_dumpvars_missing_scope.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_dumpvars_multi_scope.py b/test_regress/t/t_trace_dumpvars_multi_scope.py index 1eaecdb79..e6571964d 100644 --- a/test_regress/t/t_trace_dumpvars_multi_scope.py +++ b/test_regress/t/t_trace_dumpvars_multi_scope.py @@ -4,7 +4,7 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_dumpvars_multi_scope.v b/test_regress/t/t_trace_dumpvars_multi_scope.v index 56a1fdbee..ae673be07 100644 --- a/test_regress/t/t_trace_dumpvars_multi_scope.v +++ b/test_regress/t/t_trace_dumpvars_multi_scope.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_dumpvars_nonconst_scope.py b/test_regress/t/t_trace_dumpvars_nonconst_scope.py index 07e99a967..14865b871 100644 --- a/test_regress/t/t_trace_dumpvars_nonconst_scope.py +++ b/test_regress/t/t_trace_dumpvars_nonconst_scope.py @@ -4,7 +4,7 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_dumpvars_nonconst_scope.v b/test_regress/t/t_trace_dumpvars_nonconst_scope.v index 82310bb9e..3664cc288 100644 --- a/test_regress/t/t_trace_dumpvars_nonconst_scope.v +++ b/test_regress/t/t_trace_dumpvars_nonconst_scope.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_dumpvars_override.py b/test_regress/t/t_trace_dumpvars_override.py index 1eaecdb79..e6571964d 100644 --- a/test_regress/t/t_trace_dumpvars_override.py +++ b/test_regress/t/t_trace_dumpvars_override.py @@ -4,7 +4,7 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_dumpvars_override.v b/test_regress/t/t_trace_dumpvars_override.v index ca4c1fad9..9d45daa56 100644 --- a/test_regress/t/t_trace_dumpvars_override.v +++ b/test_regress/t/t_trace_dumpvars_override.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_dumpvars_scope.py b/test_regress/t/t_trace_dumpvars_scope.py index 1eaecdb79..e6571964d 100644 --- a/test_regress/t/t_trace_dumpvars_scope.py +++ b/test_regress/t/t_trace_dumpvars_scope.py @@ -4,7 +4,7 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_dumpvars_scope.v b/test_regress/t/t_trace_dumpvars_scope.v index fb2155d2e..6b5621bc4 100644 --- a/test_regress/t/t_trace_dumpvars_scope.v +++ b/test_regress/t/t_trace_dumpvars_scope.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_dumpvars_struct.py b/test_regress/t/t_trace_dumpvars_struct.py index 3768a51af..d4c312914 100644 --- a/test_regress/t/t_trace_dumpvars_struct.py +++ b/test_regress/t/t_trace_dumpvars_struct.py @@ -4,7 +4,7 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_dumpvars_struct.v b/test_regress/t/t_trace_dumpvars_struct.v index d2748684c..8f7d3e8e9 100644 --- a/test_regress/t/t_trace_dumpvars_struct.v +++ b/test_regress/t/t_trace_dumpvars_struct.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_dumpvars_sub.py b/test_regress/t/t_trace_dumpvars_sub.py index 1eaecdb79..e6571964d 100644 --- a/test_regress/t/t_trace_dumpvars_sub.py +++ b/test_regress/t/t_trace_dumpvars_sub.py @@ -4,7 +4,7 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_dumpvars_sub.v b/test_regress/t/t_trace_dumpvars_sub.v index dcddf9c90..b79b4012b 100644 --- a/test_regress/t/t_trace_dumpvars_sub.v +++ b/test_regress/t/t_trace_dumpvars_sub.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_dumpvars_sub0.py b/test_regress/t/t_trace_dumpvars_sub0.py index 1eaecdb79..e6571964d 100644 --- a/test_regress/t/t_trace_dumpvars_sub0.py +++ b/test_regress/t/t_trace_dumpvars_sub0.py @@ -4,7 +4,7 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_dumpvars_sub0.v b/test_regress/t/t_trace_dumpvars_sub0.v index ca936cd7e..409aab752 100644 --- a/test_regress/t/t_trace_dumpvars_sub0.v +++ b/test_regress/t/t_trace_dumpvars_sub0.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_dumpvars_task.py b/test_regress/t/t_trace_dumpvars_task.py index 1eaecdb79..e6571964d 100644 --- a/test_regress/t/t_trace_dumpvars_task.py +++ b/test_regress/t/t_trace_dumpvars_task.py @@ -4,7 +4,7 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_dumpvars_task.v b/test_regress/t/t_trace_dumpvars_task.v index 74e64feb7..b8566d9bf 100644 --- a/test_regress/t/t_trace_dumpvars_task.v +++ b/test_regress/t/t_trace_dumpvars_task.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_dumpvars_task2.py b/test_regress/t/t_trace_dumpvars_task2.py index 1eaecdb79..e6571964d 100644 --- a/test_regress/t/t_trace_dumpvars_task2.py +++ b/test_regress/t/t_trace_dumpvars_task2.py @@ -4,7 +4,7 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_dumpvars_task2.v b/test_regress/t/t_trace_dumpvars_task2.v index 6b0fe071e..2c3de1177 100644 --- a/test_regress/t/t_trace_dumpvars_task2.v +++ b/test_regress/t/t_trace_dumpvars_task2.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_dumpvars_task2_no_inl.py b/test_regress/t/t_trace_dumpvars_task2_no_inl.py index a58724bfa..38f138c77 100644 --- a/test_regress/t/t_trace_dumpvars_task2_no_inl.py +++ b/test_regress/t/t_trace_dumpvars_task2_no_inl.py @@ -4,7 +4,7 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_dumpvars_task2_no_inl.v b/test_regress/t/t_trace_dumpvars_task2_no_inl.v index 6b0fe071e..2c3de1177 100644 --- a/test_regress/t/t_trace_dumpvars_task2_no_inl.v +++ b/test_regress/t/t_trace_dumpvars_task2_no_inl.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_dumpvars_task_no_inl.py b/test_regress/t/t_trace_dumpvars_task_no_inl.py index a58724bfa..38f138c77 100644 --- a/test_regress/t/t_trace_dumpvars_task_no_inl.py +++ b/test_regress/t/t_trace_dumpvars_task_no_inl.py @@ -4,7 +4,7 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_dumpvars_task_no_inl.v b/test_regress/t/t_trace_dumpvars_task_no_inl.v index 74e64feb7..b8566d9bf 100644 --- a/test_regress/t/t_trace_dumpvars_task_no_inl.v +++ b/test_regress/t/t_trace_dumpvars_task_no_inl.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_dumpvars_wire.py b/test_regress/t/t_trace_dumpvars_wire.py index 1eaecdb79..e6571964d 100644 --- a/test_regress/t/t_trace_dumpvars_wire.py +++ b/test_regress/t/t_trace_dumpvars_wire.py @@ -4,7 +4,7 @@ # This program is free software; you can redistribute it and/or modify it # under the terms of either the GNU Lesser General Public License Version 3 # or the Perl Artistic License Version 2.0. -# SPDX-FileCopyrightText: 2026 by Marco Bartoli. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap diff --git a/test_regress/t/t_trace_dumpvars_wire.v b/test_regress/t/t_trace_dumpvars_wire.v index 2ec84035c..8a8714ac5 100644 --- a/test_regress/t/t_trace_dumpvars_wire.v +++ b/test_regress/t/t_trace_dumpvars_wire.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Marco Bartoli. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" From 69dc32f16a4c615894b7a227218516f0402c1216 Mon Sep 17 00:00:00 2001 From: wsxarcher Date: Tue, 24 Mar 2026 20:30:19 +0100 Subject: [PATCH 05/13] Fix c++ top module resolution and gen block subscript --- include/verilated_trace_imp.h | 2 +- src/V3LinkDot.cpp | 84 ++++++++++++++++++- .../t/t_trace_dumpvars_cpptop_hier_array.cpp | 36 ++++++++ .../t/t_trace_dumpvars_cpptop_hier_array.out | 42 ++++++++++ .../t/t_trace_dumpvars_cpptop_hier_array.py | 27 ++++++ .../t/t_trace_dumpvars_cpptop_hier_array.v | 49 +++++++++++ ...t_trace_dumpvars_cpptop_hier_array_oob.cpp | 36 ++++++++ ...t_trace_dumpvars_cpptop_hier_array_oob.out | 18 ++++ .../t_trace_dumpvars_cpptop_hier_array_oob.py | 27 ++++++ .../t_trace_dumpvars_cpptop_hier_array_oob.v | 49 +++++++++++ .../t/t_trace_dumpvars_cpptop_hier_global.cpp | 36 ++++++++ .../t/t_trace_dumpvars_cpptop_hier_global.py | 25 ++++++ .../t/t_trace_dumpvars_cpptop_hier_global.v | 56 +++++++++++++ .../t/t_trace_dumpvars_cpptop_hier_struct.cpp | 36 ++++++++ .../t/t_trace_dumpvars_cpptop_hier_struct.out | 38 +++++++++ .../t/t_trace_dumpvars_cpptop_hier_struct.py | 28 +++++++ .../t/t_trace_dumpvars_cpptop_hier_struct.v | 46 ++++++++++ .../t_trace_dumpvars_cpptop_hier_struct2.cpp | 36 ++++++++ .../t/t_trace_dumpvars_cpptop_hier_struct2.py | 26 ++++++ .../t/t_trace_dumpvars_cpptop_hier_struct2.v | 46 ++++++++++ .../t/t_trace_dumpvars_cpptop_missing.cpp | 36 ++++++++ .../t/t_trace_dumpvars_cpptop_missing.out | 2 + .../t/t_trace_dumpvars_cpptop_missing.py | 26 ++++++ .../t/t_trace_dumpvars_cpptop_missing.v | 50 +++++++++++ .../t/t_trace_dumpvars_cpptop_missing2.cpp | 36 ++++++++ .../t/t_trace_dumpvars_cpptop_missing2.out | 5 ++ .../t/t_trace_dumpvars_cpptop_missing2.py | 25 ++++++ .../t/t_trace_dumpvars_cpptop_missing2.v | 50 +++++++++++ .../t/t_trace_dumpvars_cpptop_missing3.cpp | 36 ++++++++ .../t/t_trace_dumpvars_cpptop_missing3.out | 2 + .../t/t_trace_dumpvars_cpptop_missing3.py | 26 ++++++ .../t/t_trace_dumpvars_cpptop_missing3.v | 50 +++++++++++ .../t/t_trace_dumpvars_cpptop_missing4.cpp | 36 ++++++++ .../t/t_trace_dumpvars_cpptop_missing4.out | 2 + .../t/t_trace_dumpvars_cpptop_missing4.py | 26 ++++++ .../t/t_trace_dumpvars_cpptop_missing4.v | 50 +++++++++++ test_regress/t/t_trace_dumpvars_gen.out | 33 ++++++++ test_regress/t/t_trace_dumpvars_gen.py | 20 +++++ test_regress/t/t_trace_dumpvars_gen.v | 55 ++++++++++++ .../t/t_trace_dumpvars_hier_array_oob.py | 18 ++++ .../t/t_trace_dumpvars_hier_array_oob.v | 49 +++++++++++ test_regress/t/t_trace_dumpvars_missing2.out | 5 ++ test_regress/t/t_trace_dumpvars_missing2.py | 17 ++++ test_regress/t/t_trace_dumpvars_missing2.v | 50 +++++++++++ test_regress/t/t_trace_dumpvars_missing3.out | 5 ++ test_regress/t/t_trace_dumpvars_missing3.py | 17 ++++ test_regress/t/t_trace_dumpvars_missing3.v | 50 +++++++++++ test_regress/t/t_trace_dumpvars_missing4.out | 5 ++ test_regress/t/t_trace_dumpvars_missing4.py | 17 ++++ test_regress/t/t_trace_dumpvars_missing4.v | 50 +++++++++++ test_regress/t/t_trace_dumpvars_missing5.out | 5 ++ test_regress/t/t_trace_dumpvars_missing5.py | 17 ++++ test_regress/t/t_trace_dumpvars_missing5.v | 50 +++++++++++ test_regress/t/t_trace_dumpvars_t.out | 5 ++ test_regress/t/t_trace_dumpvars_t.py | 17 ++++ test_regress/t/t_trace_dumpvars_t.v | 50 +++++++++++ test_regress/t/t_trace_dumpvars_top.out | 0 test_regress/t/t_trace_dumpvars_top.py | 0 test_regress/t/t_trace_dumpvars_top.v | 0 59 files changed, 1733 insertions(+), 3 deletions(-) create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_hier_array.cpp create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_hier_array.out create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_hier_array.py create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_hier_array.v create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.cpp create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.out create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.py create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.v create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_hier_global.cpp create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_hier_global.py create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_hier_global.v create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_hier_struct.cpp create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_hier_struct.out create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_hier_struct.py create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_hier_struct.v create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.cpp create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.py create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.v create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_missing.cpp create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_missing.out create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_missing.py create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_missing.v create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_missing2.cpp create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_missing2.out create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_missing2.py create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_missing2.v create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_missing3.cpp create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_missing3.out create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_missing3.py create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_missing3.v create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_missing4.cpp create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_missing4.out create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_missing4.py create mode 100644 test_regress/t/t_trace_dumpvars_cpptop_missing4.v create mode 100644 test_regress/t/t_trace_dumpvars_gen.out create mode 100644 test_regress/t/t_trace_dumpvars_gen.py create mode 100644 test_regress/t/t_trace_dumpvars_gen.v create mode 100644 test_regress/t/t_trace_dumpvars_hier_array_oob.py create mode 100644 test_regress/t/t_trace_dumpvars_hier_array_oob.v create mode 100644 test_regress/t/t_trace_dumpvars_missing2.out create mode 100644 test_regress/t/t_trace_dumpvars_missing2.py create mode 100644 test_regress/t/t_trace_dumpvars_missing2.v create mode 100644 test_regress/t/t_trace_dumpvars_missing3.out create mode 100644 test_regress/t/t_trace_dumpvars_missing3.py create mode 100644 test_regress/t/t_trace_dumpvars_missing3.v create mode 100644 test_regress/t/t_trace_dumpvars_missing4.out create mode 100644 test_regress/t/t_trace_dumpvars_missing4.py create mode 100644 test_regress/t/t_trace_dumpvars_missing4.v create mode 100644 test_regress/t/t_trace_dumpvars_missing5.out create mode 100644 test_regress/t/t_trace_dumpvars_missing5.py create mode 100644 test_regress/t/t_trace_dumpvars_missing5.v create mode 100644 test_regress/t/t_trace_dumpvars_t.out create mode 100644 test_regress/t/t_trace_dumpvars_t.py create mode 100644 test_regress/t/t_trace_dumpvars_t.v create mode 100644 test_regress/t/t_trace_dumpvars_top.out create mode 100644 test_regress/t/t_trace_dumpvars_top.py create mode 100644 test_regress/t/t_trace_dumpvars_top.v diff --git a/include/verilated_trace_imp.h b/include/verilated_trace_imp.h index 603652005..5f4bef453 100644 --- a/include/verilated_trace_imp.h +++ b/include/verilated_trace_imp.h @@ -335,7 +335,7 @@ void VerilatedTrace::traceInit() VL_MT_UNSAFE { // Apply enables if (m_sigs_enabledp) VL_DO_CLEAR(delete[] m_sigs_enabledp, m_sigs_enabledp = nullptr); - if (!m_sigs_enabledVec.empty()) { + if (!m_sigs_enabledVec.empty() || !m_dumpvars.empty()) { // Else if was empty, m_sigs_enabledp = nullptr to short circuit tests // But it isn't, so alloc one bit for each code to indicate enablement // We don't want to still use m_signs_enabledVec as std::vector is not diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index 2325d0a1e..7ccfbd6ce 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -3218,6 +3218,15 @@ class LinkDotResolveVisitor final : public VNVisitor { return false; } + static string dumpvarsBracketToInternal(const string& ident) { + const string::size_type lbr = ident.find('['); + if (lbr == string::npos) return ident; + const string::size_type rbr = ident.find(']', lbr); + if (rbr == string::npos) return ident; + return ident.substr(0, lbr) + "__BRA__" + ident.substr(lbr + 1, rbr - lbr - 1) + + "__KET__" + dumpvarsBracketToInternal(ident.substr(rbr + 1)); + } + VSymEnt* findDumpvarsLocal(FileLine* refLocationp, const string& dotname, string& baddot, VSymEnt*& okSymp) { if (!m_curSymp) return nullptr; @@ -3237,6 +3246,8 @@ class LinkDotResolveVisitor final : public VNVisitor { string altIdent; if (m_statep->forPrearray()) { if ((pos = ident.rfind("__BRA__")) != string::npos) altIdent = ident.substr(0, pos); + if (altIdent.empty() && ident.find('[') != string::npos) + altIdent = ident.substr(0, ident.find('[')); } VSymEnt* symp = nullptr; @@ -3244,6 +3255,8 @@ class LinkDotResolveVisitor final : public VNVisitor { symp = m_curSymp; } else { symp = m_curSymp->findIdFallback(ident); + if (!symp && ident.find('[') != string::npos) + symp = m_curSymp->findIdFallback(dumpvarsBracketToInternal(ident)); if (!symp && !altIdent.empty()) symp = m_curSymp->findIdFallback(altIdent); } if (!symp) return nullptr; @@ -3286,6 +3299,61 @@ class LinkDotResolveVisitor final : public VNVisitor { // Step 4: Multi-component "X.y.z" where X might be the runtime root. const string remaining = target.substr(dotPos + 1); + + // With --main, if the first component matches the local module, + // walk the remaining path through cell scopes to validate it. + if (!dumpvarsHasBareTarget(targetsp, firstComp) && v3Global.opt.main() + && dumpvarsMatchesLocalModule(m_curSymp, firstComp)) { + string walkPath = remaining; + VSymEnt* walkSymp = m_curSymp; + bool errorOut = false; + while (!walkPath.empty() && walkSymp) { + // Extract first identifier (strip dots, brackets, __BRA__) + string ident = walkPath; + { + string::size_type cutPos = string::npos; + const string::size_type dp = ident.find('.'); + if (dp != string::npos && dp < cutPos) cutPos = dp; + const string::size_type bp = ident.find('['); + if (bp != string::npos && (cutPos == string::npos || bp < cutPos)) + cutPos = bp; + const string::size_type brp = ident.find("__BRA__"); + if (brp != string::npos && (cutPos == string::npos || brp < cutPos)) + cutPos = brp; + if (cutPos != string::npos) ident = ident.substr(0, cutPos); + } + VSymEnt* const childSymp = walkSymp->findIdFallback(ident); + if (!childSymp) { + errorOut = true; + break; + } + walkPath = walkPath.substr(ident.size()); + if (!walkPath.empty() && walkPath[0] == '.') walkPath = walkPath.substr(1); + // Skip array subscript if present + if (!walkPath.empty() && walkPath[0] == '[') { + const string::size_type rb = walkPath.find(']'); + if (rb != string::npos) walkPath = walkPath.substr(rb + 1); + if (!walkPath.empty() && walkPath[0] == '.') walkPath = walkPath.substr(1); + } + if (walkPath.substr(0, 7) == "__BRA__") { + const string::size_type ke = walkPath.find("__KET__"); + if (ke != string::npos) walkPath = walkPath.substr(ke + 7); + if (!walkPath.empty() && walkPath[0] == '.') walkPath = walkPath.substr(1); + } + if (!VN_IS(childSymp->nodep(), Cell) + && !VN_IS(childSymp->nodep(), CellInline) + && !VN_IS(childSymp->nodep(), NodeModule)) { + return target; + } + walkSymp = childSymp; + } + if (errorOut) { + fl->v3error("$dumpvars target not found: " << target); + return target; + } + return target; + } + if (dumpvarsHasBareTarget(targetsp, firstComp)) { string runtimeBaddot; VSymEnt* runtimeMatchSymp = nullptr; @@ -3297,8 +3365,20 @@ class LinkDotResolveVisitor final : public VNVisitor { return target; } - UINFO(5, "$dumpvars target '" << target << "' not found in hierarchy" << endl); - return target; + string localBaddot; + VSymEnt* localSymp = nullptr; + if (findDumpvarsLocal(fl, firstComp, localBaddot, localSymp) + && !VN_IS(localSymp->nodep(), Cell) && !VN_IS(localSymp->nodep(), CellInline) + && !VN_IS(localSymp->nodep(), NodeModule)) { + return target; + } + + if (v3Global.opt.main()) { + fl->v3error("$dumpvars target not found: " << target); + return target; + } + // First component may be a runtime root name from C++; defer validation to runtime. + return kDumpvarsRuntimeRoot.make(target); } // METHODS - Variables diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_array.cpp b/test_regress/t/t_trace_dumpvars_cpptop_hier_array.cpp new file mode 100644 index 000000000..83ccacb87 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_array.cpp @@ -0,0 +1,36 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +// +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +#include + +#include + +#include VM_PREFIX_INCLUDE + +unsigned long long main_time = 0; +double sc_time_stamp() { return (double)main_time; } + +int main(int argc, char** argv) { + Verilated::debug(0); + Verilated::traceEverOn(true); + Verilated::commandArgs(argc, argv); + + // Name the top module "cpptop" instead of default "TOP" + std::unique_ptr top{new VM_PREFIX{"cpptop"}}; + top->clk = 0; + + while (!Verilated::gotFinish()) { + top->eval(); + ++main_time; + top->clk = !top->clk; + } + top->final(); + top.reset(); + printf("*-* All Finished *-*\n"); + return 0; +} diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_array.out b/test_regress/t/t_trace_dumpvars_cpptop_hier_array.out new file mode 100644 index 000000000..77cfcfdfa --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_array.out @@ -0,0 +1,42 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module cpptop $end + $scope module t $end + $scope module arr[0] $end + $scope module deep $end + $upscope $end + $upscope $end + $scope module arr[1] $end + $scope module deep $end + $var wire 32 ' ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 $ inner [31:0] $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 " +b00000000000000000000000000001011 $ +b00000000000000000000000000001011 ' +#1 +b00000000000000000000000000000001 " +b00000000000000000000000000001100 $ +#3 +b00000000000000000000000000000010 " +b00000000000000000000000000001101 $ +#5 +b00000000000000000000000000000011 " +b00000000000000000000000000001110 $ +#7 +b00000000000000000000000000000100 " +b00000000000000000000000000001111 $ +#9 +b00000000000000000000000000000101 " +b00000000000000000000000000010000 $ +#11 +b00000000000000000000000000000110 " +b00000000000000000000000000010001 $ diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_array.py b/test_regress/t/t_trace_dumpvars_cpptop_hier_array.py new file mode 100644 index 000000000..4e8341f6c --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_array.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + make_main=False, + verilator_flags2=[ + '--cc', + '--exe', + '--trace-vcd', + 't/t_trace_dumpvars_cpptop_hier_array.cpp', + ]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_array.v b/test_regress/t/t_trace_dumpvars_cpptop_hier_array.v new file mode 100644 index 000000000..a36a7a8d5 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_array.v @@ -0,0 +1,49 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + + sub #(10) arr[2](.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // Test $dumpvars with an arrayed hierarchical scope path via cpptop. + $dumpvars(1, cpptop.t.arr[1].deep); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + deep #(ADD + 1) deep(.*); +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.cpp b/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.cpp new file mode 100644 index 000000000..83ccacb87 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.cpp @@ -0,0 +1,36 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +// +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +#include + +#include + +#include VM_PREFIX_INCLUDE + +unsigned long long main_time = 0; +double sc_time_stamp() { return (double)main_time; } + +int main(int argc, char** argv) { + Verilated::debug(0); + Verilated::traceEverOn(true); + Verilated::commandArgs(argc, argv); + + // Name the top module "cpptop" instead of default "TOP" + std::unique_ptr top{new VM_PREFIX{"cpptop"}}; + top->clk = 0; + + while (!Verilated::gotFinish()) { + top->eval(); + ++main_time; + top->clk = !top->clk; + } + top->final(); + top.reset(); + printf("*-* All Finished *-*\n"); + return 0; +} diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.out b/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.out new file mode 100644 index 000000000..d8b0895ae --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.out @@ -0,0 +1,18 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module cpptop $end + $scope module t $end + $scope module arr[0] $end + $scope module deep $end + $upscope $end + $upscope $end + $scope module arr[1] $end + $scope module deep $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#11 diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.py b/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.py new file mode 100644 index 000000000..976058255 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + make_main=False, + verilator_flags2=[ + '--cc', + '--exe', + '--trace-vcd', + 't/t_trace_dumpvars_cpptop_hier_array_oob.cpp', + ]) + +test.execute() + +test.files_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.v b/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.v new file mode 100644 index 000000000..6a64c812f --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.v @@ -0,0 +1,49 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + + sub #(10) arr[2](.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // Test $dumpvars with an out-of-range array index via cpptop. + $dumpvars(1, cpptop.t.arr[999].deep); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + deep #(ADD + 1) deep(.*); +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_global.cpp b/test_regress/t/t_trace_dumpvars_cpptop_hier_global.cpp new file mode 100644 index 000000000..83ccacb87 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_global.cpp @@ -0,0 +1,36 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +// +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +#include + +#include + +#include VM_PREFIX_INCLUDE + +unsigned long long main_time = 0; +double sc_time_stamp() { return (double)main_time; } + +int main(int argc, char** argv) { + Verilated::debug(0); + Verilated::traceEverOn(true); + Verilated::commandArgs(argc, argv); + + // Name the top module "cpptop" instead of default "TOP" + std::unique_ptr top{new VM_PREFIX{"cpptop"}}; + top->clk = 0; + + while (!Verilated::gotFinish()) { + top->eval(); + ++main_time; + top->clk = !top->clk; + } + top->final(); + top.reset(); + printf("*-* All Finished *-*\n"); + return 0; +} diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_global.py b/test_regress/t/t_trace_dumpvars_cpptop_hier_global.py new file mode 100644 index 000000000..9779f2f74 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_global.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + make_main=False, + verilator_flags2=[ + '--cc', + '--exe', + '--trace-vcd', + 't/t_trace_dumpvars_cpptop_hier_global.cpp', + ]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_global.v b/test_regress/t/t_trace_dumpvars_cpptop_hier_global.v new file mode 100644 index 000000000..37dd5d357 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_global.v @@ -0,0 +1,56 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + deep #(ADD + 1) deep_i(.*); + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // Test $dumpvars with hierarchical scope: level 1 limits to direct signals of t outside the scope + $dumpvars(1, t); + end +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + int t; + always_comb inner = cyc + ADD; + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + $dumpvars(1, t); + end +endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.cpp b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.cpp new file mode 100644 index 000000000..83ccacb87 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.cpp @@ -0,0 +1,36 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +// +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +#include + +#include + +#include VM_PREFIX_INCLUDE + +unsigned long long main_time = 0; +double sc_time_stamp() { return (double)main_time; } + +int main(int argc, char** argv) { + Verilated::debug(0); + Verilated::traceEverOn(true); + Verilated::commandArgs(argc, argv); + + // Name the top module "cpptop" instead of default "TOP" + std::unique_ptr top{new VM_PREFIX{"cpptop"}}; + top->clk = 0; + + while (!Verilated::gotFinish()) { + top->eval(); + ++main_time; + top->clk = !top->clk; + } + top->final(); + top.reset(); + printf("*-* All Finished *-*\n"); + return 0; +} diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.out b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.out new file mode 100644 index 000000000..b65b71fa9 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.out @@ -0,0 +1,38 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module cpptop $end + $scope module t $end + $scope module mystruct $end + $scope module deep $end + $var wire 32 ' add [31:0] $end + $var wire 32 # cyc [31:0] $end + $var wire 32 $ inner [31:0] $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 # +b00000000000000000000000000001011 $ +b00000000000000000000000000001011 ' +#1 +b00000000000000000000000000000001 # +b00000000000000000000000000001100 $ +#3 +b00000000000000000000000000000010 # +b00000000000000000000000000001101 $ +#5 +b00000000000000000000000000000011 # +b00000000000000000000000000001110 $ +#7 +b00000000000000000000000000000100 # +b00000000000000000000000000001111 $ +#9 +b00000000000000000000000000000101 # +b00000000000000000000000000010000 $ +#11 +b00000000000000000000000000000110 # +b00000000000000000000000000010001 $ diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.py b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.py new file mode 100644 index 000000000..8947c16b2 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.py @@ -0,0 +1,28 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + make_main=False, + verilator_flags2=[ + '--cc', + '--exe', + '--trace-vcd', + '--trace-structs', + 't/t_trace_dumpvars_cpptop_hier_struct.cpp', + ]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.v b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.v new file mode 100644 index 000000000..351212317 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.v @@ -0,0 +1,46 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +typedef struct packed { + logic [31:0] add; + logic [31:0] cyc; + logic [31:0] inner; +} deep_t; + +typedef struct packed { + deep_t deep; + logic [31:0] value; +} top_t; + +module t( + input clk +); + int cyc; + top_t mystruct; + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // Test $dumpvars with a traced struct sub-scope via cpptop. + $dumpvars(1, cpptop.t.mystruct.deep); + end + + always_comb begin + mystruct.value = cyc + 32'd10; + mystruct.deep.add = 32'd11; + mystruct.deep.cyc = cyc; + mystruct.deep.inner = cyc + mystruct.deep.add; + end +endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.cpp b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.cpp new file mode 100644 index 000000000..83ccacb87 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.cpp @@ -0,0 +1,36 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +// +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +#include + +#include + +#include VM_PREFIX_INCLUDE + +unsigned long long main_time = 0; +double sc_time_stamp() { return (double)main_time; } + +int main(int argc, char** argv) { + Verilated::debug(0); + Verilated::traceEverOn(true); + Verilated::commandArgs(argc, argv); + + // Name the top module "cpptop" instead of default "TOP" + std::unique_ptr top{new VM_PREFIX{"cpptop"}}; + top->clk = 0; + + while (!Verilated::gotFinish()) { + top->eval(); + ++main_time; + top->clk = !top->clk; + } + top->final(); + top.reset(); + printf("*-* All Finished *-*\n"); + return 0; +} diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.py b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.py new file mode 100644 index 000000000..dce00d975 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + make_main=False, + verilator_flags2=[ + '--cc', + '--exe', + '--trace-vcd', + '--trace-structs', + 't/t_trace_dumpvars_cpptop_hier_struct2.cpp', + ]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.v b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.v new file mode 100644 index 000000000..e15dc0c45 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.v @@ -0,0 +1,46 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +typedef struct packed { + logic [31:0] add; + logic [31:0] cyc; + logic [31:0] inner; +} deep_t; + +typedef struct packed { + deep_t deep; + logic [31:0] value; +} top_t; + +module t( + input clk +); + int cyc; + top_t mystruct; + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // Test $dumpvars with a struct leaf member via cpptop. + $dumpvars(1, cpptop.t.mystruct.deep.inner); + end + + always_comb begin + mystruct.value = cyc + 32'd10; + mystruct.deep.add = 32'd11; + mystruct.deep.cyc = cyc; + mystruct.deep.inner = cyc + mystruct.deep.add; + end +endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing.cpp b/test_regress/t/t_trace_dumpvars_cpptop_missing.cpp new file mode 100644 index 000000000..83ccacb87 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing.cpp @@ -0,0 +1,36 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +// +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +#include + +#include + +#include VM_PREFIX_INCLUDE + +unsigned long long main_time = 0; +double sc_time_stamp() { return (double)main_time; } + +int main(int argc, char** argv) { + Verilated::debug(0); + Verilated::traceEverOn(true); + Verilated::commandArgs(argc, argv); + + // Name the top module "cpptop" instead of default "TOP" + std::unique_ptr top{new VM_PREFIX{"cpptop"}}; + top->clk = 0; + + while (!Verilated::gotFinish()) { + top->eval(); + ++main_time; + top->clk = !top->clk; + } + top->final(); + top.reset(); + printf("*-* All Finished *-*\n"); + return 0; +} diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing.out b/test_regress/t/t_trace_dumpvars_cpptop_missing.out new file mode 100644 index 000000000..1342a7374 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing.out @@ -0,0 +1,2 @@ +%Error: t/t_trace_dumpvars_cpptop_missing.v:28: $dumpvars target not found: missing_module +Aborting... diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing.py b/test_regress/t/t_trace_dumpvars_cpptop_missing.py new file mode 100644 index 000000000..c5f10a6dd --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + make_main=False, + verilator_flags2=[ + '--cc', + '--exe', + '--trace-vcd', + 't/t_trace_dumpvars_cpptop_missing.cpp', + ]) + +test.execute(fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing.v b/test_regress/t/t_trace_dumpvars_cpptop_missing.v new file mode 100644 index 000000000..52816b852 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing.v @@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // Test $dumpvars with a non-existent module scope argument via cpptop. + $dumpvars(0, missing_module); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + deep #(ADD + 1) deep_i(.*); +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing2.cpp b/test_regress/t/t_trace_dumpvars_cpptop_missing2.cpp new file mode 100644 index 000000000..83ccacb87 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing2.cpp @@ -0,0 +1,36 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +// +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +#include + +#include + +#include VM_PREFIX_INCLUDE + +unsigned long long main_time = 0; +double sc_time_stamp() { return (double)main_time; } + +int main(int argc, char** argv) { + Verilated::debug(0); + Verilated::traceEverOn(true); + Verilated::commandArgs(argc, argv); + + // Name the top module "cpptop" instead of default "TOP" + std::unique_ptr top{new VM_PREFIX{"cpptop"}}; + top->clk = 0; + + while (!Verilated::gotFinish()) { + top->eval(); + ++main_time; + top->clk = !top->clk; + } + top->final(); + top.reset(); + printf("*-* All Finished *-*\n"); + return 0; +} diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing2.out b/test_regress/t/t_trace_dumpvars_cpptop_missing2.out new file mode 100644 index 000000000..829ff6e43 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing2.out @@ -0,0 +1,5 @@ +%Error: t/t_trace_dumpvars_cpptop_missing2.v:28:17: Can't find definition of 'missingname' in dotted variable/method: 't.missingname' + 28 | $dumpvars(t.missingname); + | ^~~~~~~~~~~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: Exiting due to diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing2.py b/test_regress/t/t_trace_dumpvars_cpptop_missing2.py new file mode 100644 index 000000000..b0c45db1a --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing2.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + fails=True, + make_main=False, + verilator_flags2=[ + '--cc', + '--exe', + '--trace-vcd', + 't/t_trace_dumpvars_cpptop_missing2.cpp', + ], + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing2.v b/test_regress/t/t_trace_dumpvars_cpptop_missing2.v new file mode 100644 index 000000000..600be2574 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing2.v @@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // Test $dumpvars with a hierarchical non-existent scope argument via cpptop. + $dumpvars(t.missingname); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + deep #(ADD + 1) deep_i(.*); +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing3.cpp b/test_regress/t/t_trace_dumpvars_cpptop_missing3.cpp new file mode 100644 index 000000000..83ccacb87 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing3.cpp @@ -0,0 +1,36 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +// +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +#include + +#include + +#include VM_PREFIX_INCLUDE + +unsigned long long main_time = 0; +double sc_time_stamp() { return (double)main_time; } + +int main(int argc, char** argv) { + Verilated::debug(0); + Verilated::traceEverOn(true); + Verilated::commandArgs(argc, argv); + + // Name the top module "cpptop" instead of default "TOP" + std::unique_ptr top{new VM_PREFIX{"cpptop"}}; + top->clk = 0; + + while (!Verilated::gotFinish()) { + top->eval(); + ++main_time; + top->clk = !top->clk; + } + top->final(); + top.reset(); + printf("*-* All Finished *-*\n"); + return 0; +} diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing3.out b/test_regress/t/t_trace_dumpvars_cpptop_missing3.out new file mode 100644 index 000000000..f7ba9c4e1 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing3.out @@ -0,0 +1,2 @@ +%Error: t/t_trace_dumpvars_cpptop_missing3.v:28: $dumpvars target not found: t.missing +Aborting... diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing3.py b/test_regress/t/t_trace_dumpvars_cpptop_missing3.py new file mode 100644 index 000000000..642a2cb0b --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing3.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + make_main=False, + verilator_flags2=[ + '--cc', + '--exe', + '--trace-vcd', + 't/t_trace_dumpvars_cpptop_missing3.cpp', + ]) + +test.execute(fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing3.v b/test_regress/t/t_trace_dumpvars_cpptop_missing3.v new file mode 100644 index 000000000..e00189d61 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing3.v @@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // Test $dumpvars with level and hierarchical non-existent scope via cpptop. + $dumpvars(0, t.missing); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + deep #(ADD + 1) deep_i(.*); +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing4.cpp b/test_regress/t/t_trace_dumpvars_cpptop_missing4.cpp new file mode 100644 index 000000000..83ccacb87 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing4.cpp @@ -0,0 +1,36 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +// +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +#include + +#include + +#include VM_PREFIX_INCLUDE + +unsigned long long main_time = 0; +double sc_time_stamp() { return (double)main_time; } + +int main(int argc, char** argv) { + Verilated::debug(0); + Verilated::traceEverOn(true); + Verilated::commandArgs(argc, argv); + + // Name the top module "cpptop" instead of default "TOP" + std::unique_ptr top{new VM_PREFIX{"cpptop"}}; + top->clk = 0; + + while (!Verilated::gotFinish()) { + top->eval(); + ++main_time; + top->clk = !top->clk; + } + top->final(); + top.reset(); + printf("*-* All Finished *-*\n"); + return 0; +} diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing4.out b/test_regress/t/t_trace_dumpvars_cpptop_missing4.out new file mode 100644 index 000000000..9c860bd10 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing4.out @@ -0,0 +1,2 @@ +%Error: t/t_trace_dumpvars_cpptop_missing4.v:28: $dumpvars target not found: t.sub_a.missing +Aborting... diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing4.py b/test_regress/t/t_trace_dumpvars_cpptop_missing4.py new file mode 100644 index 000000000..5696a1b7f --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing4.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile( + make_main=False, + verilator_flags2=[ + '--cc', + '--exe', + '--trace-vcd', + 't/t_trace_dumpvars_cpptop_missing4.cpp', + ]) + +test.execute(fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing4.v b/test_regress/t/t_trace_dumpvars_cpptop_missing4.v new file mode 100644 index 000000000..e03a6d18f --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing4.v @@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // Test $dumpvars with a valid sub-scope but missing child via cpptop. + $dumpvars(0, t.sub_a.missing); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + deep #(ADD + 1) deep_i(.*); +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_gen.out b/test_regress/t/t_trace_dumpvars_gen.out new file mode 100644 index 000000000..92d14f65f --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_gen.out @@ -0,0 +1,33 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $scope module gen_sub[0] $end + $scope module sub_i $end + $var wire 32 ( ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 # value [31:0] $end + $scope module deep_i $end + $var wire 32 ) ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var wire 32 $ inner [31:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module gen_sub[1] $end + $scope module sub_i $end + $scope module deep_i $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 " +b00000000000000000000000000001010 # +b00000000000000000000000000001011 $ +b00000000000000000000000000001010 ( +b00000000000000000000000000001011 ) diff --git a/test_regress/t/t_trace_dumpvars_gen.py b/test_regress/t/t_trace_dumpvars_gen.py new file mode 100644 index 000000000..e6571964d --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_gen.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--binary --trace-vcd']) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_gen.v b/test_regress/t/t_trace_dumpvars_gen.v new file mode 100644 index 000000000..1b6b0524b --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_gen.v @@ -0,0 +1,55 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + + // Generate block creates sub instances with named block scope + genvar i; + generate + for (i = 0; i < 2; i = i + 1) begin : gen_sub + sub #(10 * (i + 1)) sub_i(.*); + end + endgenerate + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // Dump only gen_sub[0] and everything below it + $dumpvars(0, gen_sub[0]); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + deep #(ADD + 1) deep_i(.*); +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_hier_array_oob.py b/test_regress/t/t_trace_dumpvars_hier_array_oob.py new file mode 100644 index 000000000..3ead6a6d5 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_hier_array_oob.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--binary --trace-vcd']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_hier_array_oob.v b/test_regress/t/t_trace_dumpvars_hier_array_oob.v new file mode 100644 index 000000000..8da72ff52 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_hier_array_oob.v @@ -0,0 +1,49 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + + sub #(10) arr[2](.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // Test $dumpvars with an out-of-range array index. + $dumpvars(1, t.arr[999].deep); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + deep #(ADD + 1) deep(.*); +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_missing2.out b/test_regress/t/t_trace_dumpvars_missing2.out new file mode 100644 index 000000000..6f63f58e5 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_missing2.out @@ -0,0 +1,5 @@ +%Error: t/t_trace_dumpvars_missing2.v:28:17: Can't find definition of 'missingname' in dotted variable/method: 't.missingname' + 28 | $dumpvars(t.missingname); + | ^~~~~~~~~~~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: Exiting due to diff --git a/test_regress/t/t_trace_dumpvars_missing2.py b/test_regress/t/t_trace_dumpvars_missing2.py new file mode 100644 index 000000000..b00fb4934 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_missing2.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(fails=True, verilator_flags2=['--binary --trace-vcd'], + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_missing2.v b/test_regress/t/t_trace_dumpvars_missing2.v new file mode 100644 index 000000000..0f54a11c6 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_missing2.v @@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // Test $dumpvars with a hierarchical non-existent scope argument + $dumpvars(t.missingname); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + deep #(ADD + 1) deep_i(.*); +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_missing3.out b/test_regress/t/t_trace_dumpvars_missing3.out new file mode 100644 index 000000000..5f9651d7e --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_missing3.out @@ -0,0 +1,5 @@ +%Error: t/t_trace_dumpvars_missing3.v:28:5: $dumpvars target not found: t.missing + 28 | $dumpvars(0, t.missing); + | ^~~~~~~~~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: Exiting due to diff --git a/test_regress/t/t_trace_dumpvars_missing3.py b/test_regress/t/t_trace_dumpvars_missing3.py new file mode 100644 index 000000000..b00fb4934 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_missing3.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(fails=True, verilator_flags2=['--binary --trace-vcd'], + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_missing3.v b/test_regress/t/t_trace_dumpvars_missing3.v new file mode 100644 index 000000000..c00c8687a --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_missing3.v @@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // Test $dumpvars with level and hierarchical non-existent scope + $dumpvars(0, t.missing); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + deep #(ADD + 1) deep_i(.*); +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_missing4.out b/test_regress/t/t_trace_dumpvars_missing4.out new file mode 100644 index 000000000..cb1dfa5fc --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_missing4.out @@ -0,0 +1,5 @@ +%Error: t/t_trace_dumpvars_missing4.v:28:5: $dumpvars target not found: t.sub_a.missing + 28 | $dumpvars(0, t.sub_a.missing); + | ^~~~~~~~~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: Exiting due to diff --git a/test_regress/t/t_trace_dumpvars_missing4.py b/test_regress/t/t_trace_dumpvars_missing4.py new file mode 100644 index 000000000..b00fb4934 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_missing4.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(fails=True, verilator_flags2=['--binary --trace-vcd'], + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_missing4.v b/test_regress/t/t_trace_dumpvars_missing4.v new file mode 100644 index 000000000..288885aaa --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_missing4.v @@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // Test $dumpvars with a valid sub-scope but missing child + $dumpvars(0, t.sub_a.missing); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + deep #(ADD + 1) deep_i(.*); +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_missing5.out b/test_regress/t/t_trace_dumpvars_missing5.out new file mode 100644 index 000000000..a3e49d998 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_missing5.out @@ -0,0 +1,5 @@ +%Error: t/t_trace_dumpvars_missing5.v:28:5: $dumpvars target not found: missing.child + 28 | $dumpvars(0, missing.child); + | ^~~~~~~~~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: Exiting due to diff --git a/test_regress/t/t_trace_dumpvars_missing5.py b/test_regress/t/t_trace_dumpvars_missing5.py new file mode 100644 index 000000000..8a19e71bf --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_missing5.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(fails=True, verilator_flags2=['--binary --trace-vcd'], + expect_filename=test.golden_filename) + +test.passes() \ No newline at end of file diff --git a/test_regress/t/t_trace_dumpvars_missing5.v b/test_regress/t/t_trace_dumpvars_missing5.v new file mode 100644 index 000000000..28eb3e1b8 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_missing5.v @@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // Test $dumpvars with a missing multi-component target under --main. + $dumpvars(0, missing.child); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + deep #(ADD + 1) deep_i(.*); +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; +endmodule \ No newline at end of file diff --git a/test_regress/t/t_trace_dumpvars_t.out b/test_regress/t/t_trace_dumpvars_t.out new file mode 100644 index 000000000..439aa8cfc --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_t.out @@ -0,0 +1,5 @@ +%Error: t/t_trace_dumpvars_t.v:28:15: Can't find definition of variable: 't' + 28 | $dumpvars(t); + | ^ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: Exiting due to diff --git a/test_regress/t/t_trace_dumpvars_t.py b/test_regress/t/t_trace_dumpvars_t.py new file mode 100644 index 000000000..b00fb4934 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_t.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(fails=True, verilator_flags2=['--binary --trace-vcd'], + expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_trace_dumpvars_t.v b/test_regress/t/t_trace_dumpvars_t.v new file mode 100644 index 000000000..29d4138b3 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_t.v @@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module t( + input clk +); + int cyc; + + sub #(10) sub_a(.*); + sub #(20) sub_b(.*); + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + // Test $dumpvars with module type name as argument + $dumpvars(t); + end +endmodule + +module sub #( + parameter int ADD +)( + input int cyc +); + int value; + always_comb value = cyc + ADD; + + deep #(ADD + 1) deep_i(.*); +endmodule + +module deep #( + parameter int ADD +)( + input int cyc +); + int inner; + always_comb inner = cyc + ADD; +endmodule diff --git a/test_regress/t/t_trace_dumpvars_top.out b/test_regress/t/t_trace_dumpvars_top.out new file mode 100644 index 000000000..e69de29bb diff --git a/test_regress/t/t_trace_dumpvars_top.py b/test_regress/t/t_trace_dumpvars_top.py new file mode 100644 index 000000000..e69de29bb diff --git a/test_regress/t/t_trace_dumpvars_top.v b/test_regress/t/t_trace_dumpvars_top.v new file mode 100644 index 000000000..e69de29bb From d4c848e8acb4065684439ff61de09d955d95706b Mon Sep 17 00:00:00 2001 From: wsxarcher Date: Tue, 24 Mar 2026 20:50:19 +0100 Subject: [PATCH 06/13] reset cleanout --- src/V3AstNodeStmt.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/V3AstNodeStmt.h b/src/V3AstNodeStmt.h index d5eb0b884..71bb11e71 100644 --- a/src/V3AstNodeStmt.h +++ b/src/V3AstNodeStmt.h @@ -651,6 +651,7 @@ public: bool isOutputter() override { return true; } bool isPredictOptimizable() const override { return false; } bool isPure() override { return false; } + virtual bool cleanOut() const { return true; } bool sameNode(const AstNode* samep) const override { return ctlType() == VN_DBG_AS(samep, DumpCtl)->ctlType(); } From 400da26f2e96eea76b4142a7986bef2132cc14a3 Mon Sep 17 00:00:00 2001 From: wsxarcher Date: Tue, 24 Mar 2026 22:35:49 +0100 Subject: [PATCH 07/13] Join test cases --- test_regress/t/t_trace_dumpvars.py | 9 +- test_regress/t/t_trace_dumpvars.v | 352 +++++++++++++++++- test_regress/t/t_trace_dumpvars_abs_scope.py | 9 +- test_regress/t/t_trace_dumpvars_abs_scope.v | 50 --- test_regress/t/t_trace_dumpvars_add_module.py | 10 +- test_regress/t/t_trace_dumpvars_add_module.v | 58 --- test_regress/t/t_trace_dumpvars_context.py | 9 +- test_regress/t/t_trace_dumpvars_context.v | 57 --- test_regress/t/t_trace_dumpvars_cpptop.py | 16 +- test_regress/t/t_trace_dumpvars_cpptop.v | 39 -- test_regress/t/t_trace_dumpvars_cpptop2.cpp | 36 -- test_regress/t/t_trace_dumpvars_cpptop2.out | 4 +- test_regress/t/t_trace_dumpvars_cpptop2.py | 14 +- test_regress/t/t_trace_dumpvars_cpptop2.v | 38 -- .../t/t_trace_dumpvars_cpptop_hier_array.cpp | 36 -- .../t/t_trace_dumpvars_cpptop_hier_array.py | 16 +- .../t/t_trace_dumpvars_cpptop_hier_array.v | 49 --- ...t_trace_dumpvars_cpptop_hier_array_oob.cpp | 36 -- .../t_trace_dumpvars_cpptop_hier_array_oob.py | 16 +- .../t_trace_dumpvars_cpptop_hier_array_oob.v | 49 --- .../t/t_trace_dumpvars_cpptop_hier_global.cpp | 36 -- .../t/t_trace_dumpvars_cpptop_hier_global.py | 14 +- .../t/t_trace_dumpvars_cpptop_hier_global.v | 56 --- .../t/t_trace_dumpvars_cpptop_hier_struct.cpp | 36 -- .../t/t_trace_dumpvars_cpptop_hier_struct.py | 17 +- .../t/t_trace_dumpvars_cpptop_hier_struct.v | 46 --- .../t_trace_dumpvars_cpptop_hier_struct2.cpp | 36 -- .../t/t_trace_dumpvars_cpptop_hier_struct2.py | 15 +- .../t/t_trace_dumpvars_cpptop_hier_struct2.v | 46 --- .../t/t_trace_dumpvars_cpptop_missing.cpp | 36 -- .../t/t_trace_dumpvars_cpptop_missing.out | 2 +- .../t/t_trace_dumpvars_cpptop_missing.py | 15 +- .../t/t_trace_dumpvars_cpptop_missing.v | 50 --- .../t/t_trace_dumpvars_cpptop_missing2.cpp | 36 -- .../t/t_trace_dumpvars_cpptop_missing2.out | 4 +- .../t/t_trace_dumpvars_cpptop_missing2.py | 14 +- .../t/t_trace_dumpvars_cpptop_missing2.v | 50 --- .../t/t_trace_dumpvars_cpptop_missing3.cpp | 36 -- .../t/t_trace_dumpvars_cpptop_missing3.out | 2 +- .../t/t_trace_dumpvars_cpptop_missing3.py | 15 +- .../t/t_trace_dumpvars_cpptop_missing3.v | 50 --- .../t/t_trace_dumpvars_cpptop_missing4.cpp | 36 -- .../t/t_trace_dumpvars_cpptop_missing4.out | 2 +- .../t/t_trace_dumpvars_cpptop_missing4.py | 15 +- .../t/t_trace_dumpvars_cpptop_missing4.v | 50 --- test_regress/t/t_trace_dumpvars_func.py | 9 +- test_regress/t/t_trace_dumpvars_func.v | 61 --- test_regress/t/t_trace_dumpvars_gen.py | 9 +- test_regress/t/t_trace_dumpvars_gen.v | 55 --- test_regress/t/t_trace_dumpvars_hier_array.py | 9 +- test_regress/t/t_trace_dumpvars_hier_array.v | 49 --- .../t/t_trace_dumpvars_hier_array_oob.py | 7 +- .../t/t_trace_dumpvars_hier_array_oob.v | 49 --- .../t/t_trace_dumpvars_hier_global.py | 9 +- test_regress/t/t_trace_dumpvars_hier_global.v | 56 --- .../t/t_trace_dumpvars_hier_global_task.py | 9 +- .../t/t_trace_dumpvars_hier_global_task.v | 71 ---- test_regress/t/t_trace_dumpvars_hier_scope.py | 9 +- test_regress/t/t_trace_dumpvars_hier_scope.v | 50 --- .../t/t_trace_dumpvars_hier_struct.py | 9 +- test_regress/t/t_trace_dumpvars_hier_struct.v | 46 --- test_regress/t/t_trace_dumpvars_level.py | 9 +- test_regress/t/t_trace_dumpvars_level.v | 50 --- .../t/t_trace_dumpvars_level_scope.py | 9 +- test_regress/t/t_trace_dumpvars_level_scope.v | 50 --- test_regress/t/t_trace_dumpvars_missing2.out | 4 +- test_regress/t/t_trace_dumpvars_missing2.py | 6 +- test_regress/t/t_trace_dumpvars_missing2.v | 50 --- test_regress/t/t_trace_dumpvars_missing3.out | 4 +- test_regress/t/t_trace_dumpvars_missing3.py | 6 +- test_regress/t/t_trace_dumpvars_missing3.v | 50 --- test_regress/t/t_trace_dumpvars_missing4.out | 4 +- test_regress/t/t_trace_dumpvars_missing4.py | 6 +- test_regress/t/t_trace_dumpvars_missing4.v | 50 --- test_regress/t/t_trace_dumpvars_missing5.out | 4 +- test_regress/t/t_trace_dumpvars_missing5.py | 6 +- test_regress/t/t_trace_dumpvars_missing5.v | 50 --- .../t/t_trace_dumpvars_missing_scope.out | 4 +- .../t/t_trace_dumpvars_missing_scope.py | 6 +- .../t/t_trace_dumpvars_missing_scope.v | 50 --- .../t/t_trace_dumpvars_multi_scope.py | 9 +- test_regress/t/t_trace_dumpvars_multi_scope.v | 50 --- .../t/t_trace_dumpvars_nonconst_scope.py | 9 +- .../t/t_trace_dumpvars_nonconst_scope.v | 52 --- test_regress/t/t_trace_dumpvars_override.py | 9 +- test_regress/t/t_trace_dumpvars_override.v | 51 --- test_regress/t/t_trace_dumpvars_scope.py | 9 +- test_regress/t/t_trace_dumpvars_scope.v | 50 --- test_regress/t/t_trace_dumpvars_struct.py | 9 +- test_regress/t/t_trace_dumpvars_struct.v | 57 --- test_regress/t/t_trace_dumpvars_sub.py | 9 +- test_regress/t/t_trace_dumpvars_sub.v | 54 --- test_regress/t/t_trace_dumpvars_sub0.py | 9 +- test_regress/t/t_trace_dumpvars_sub0.v | 54 --- test_regress/t/t_trace_dumpvars_t.out | 4 +- test_regress/t/t_trace_dumpvars_t.py | 6 +- test_regress/t/t_trace_dumpvars_t.v | 50 --- test_regress/t/t_trace_dumpvars_task.py | 9 +- test_regress/t/t_trace_dumpvars_task.v | 61 --- test_regress/t/t_trace_dumpvars_task2.py | 9 +- test_regress/t/t_trace_dumpvars_task2.v | 65 ---- .../t/t_trace_dumpvars_task2_no_inl.py | 9 +- .../t/t_trace_dumpvars_task2_no_inl.v | 65 ---- .../t/t_trace_dumpvars_task_no_inl.py | 9 +- test_regress/t/t_trace_dumpvars_task_no_inl.v | 61 --- test_regress/t/t_trace_dumpvars_top.py | 15 + test_regress/t/t_trace_dumpvars_top.v | 0 test_regress/t/t_trace_dumpvars_wire.py | 9 +- test_regress/t/t_trace_dumpvars_wire.v | 41 -- test_regress/t/trace_dumpvars_common.py | 148 ++++++++ 110 files changed, 617 insertions(+), 2918 deletions(-) delete mode 100644 test_regress/t/t_trace_dumpvars_abs_scope.v delete mode 100644 test_regress/t/t_trace_dumpvars_add_module.v delete mode 100644 test_regress/t/t_trace_dumpvars_context.v delete mode 100644 test_regress/t/t_trace_dumpvars_cpptop.v delete mode 100644 test_regress/t/t_trace_dumpvars_cpptop2.cpp delete mode 100644 test_regress/t/t_trace_dumpvars_cpptop2.v delete mode 100644 test_regress/t/t_trace_dumpvars_cpptop_hier_array.cpp delete mode 100644 test_regress/t/t_trace_dumpvars_cpptop_hier_array.v delete mode 100644 test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.cpp delete mode 100644 test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.v delete mode 100644 test_regress/t/t_trace_dumpvars_cpptop_hier_global.cpp delete mode 100644 test_regress/t/t_trace_dumpvars_cpptop_hier_global.v delete mode 100644 test_regress/t/t_trace_dumpvars_cpptop_hier_struct.cpp delete mode 100644 test_regress/t/t_trace_dumpvars_cpptop_hier_struct.v delete mode 100644 test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.cpp delete mode 100644 test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.v delete mode 100644 test_regress/t/t_trace_dumpvars_cpptop_missing.cpp delete mode 100644 test_regress/t/t_trace_dumpvars_cpptop_missing.v delete mode 100644 test_regress/t/t_trace_dumpvars_cpptop_missing2.cpp delete mode 100644 test_regress/t/t_trace_dumpvars_cpptop_missing2.v delete mode 100644 test_regress/t/t_trace_dumpvars_cpptop_missing3.cpp delete mode 100644 test_regress/t/t_trace_dumpvars_cpptop_missing3.v delete mode 100644 test_regress/t/t_trace_dumpvars_cpptop_missing4.cpp delete mode 100644 test_regress/t/t_trace_dumpvars_cpptop_missing4.v delete mode 100644 test_regress/t/t_trace_dumpvars_func.v delete mode 100644 test_regress/t/t_trace_dumpvars_gen.v delete mode 100644 test_regress/t/t_trace_dumpvars_hier_array.v delete mode 100644 test_regress/t/t_trace_dumpvars_hier_array_oob.v delete mode 100644 test_regress/t/t_trace_dumpvars_hier_global.v delete mode 100644 test_regress/t/t_trace_dumpvars_hier_global_task.v delete mode 100644 test_regress/t/t_trace_dumpvars_hier_scope.v delete mode 100644 test_regress/t/t_trace_dumpvars_hier_struct.v delete mode 100644 test_regress/t/t_trace_dumpvars_level.v delete mode 100644 test_regress/t/t_trace_dumpvars_level_scope.v delete mode 100644 test_regress/t/t_trace_dumpvars_missing2.v delete mode 100644 test_regress/t/t_trace_dumpvars_missing3.v delete mode 100644 test_regress/t/t_trace_dumpvars_missing4.v delete mode 100644 test_regress/t/t_trace_dumpvars_missing5.v delete mode 100644 test_regress/t/t_trace_dumpvars_missing_scope.v delete mode 100644 test_regress/t/t_trace_dumpvars_multi_scope.v delete mode 100644 test_regress/t/t_trace_dumpvars_nonconst_scope.v delete mode 100644 test_regress/t/t_trace_dumpvars_override.v delete mode 100644 test_regress/t/t_trace_dumpvars_scope.v delete mode 100644 test_regress/t/t_trace_dumpvars_struct.v delete mode 100644 test_regress/t/t_trace_dumpvars_sub.v delete mode 100644 test_regress/t/t_trace_dumpvars_sub0.v delete mode 100644 test_regress/t/t_trace_dumpvars_t.v delete mode 100644 test_regress/t/t_trace_dumpvars_task.v delete mode 100644 test_regress/t/t_trace_dumpvars_task2.v delete mode 100644 test_regress/t/t_trace_dumpvars_task2_no_inl.v delete mode 100644 test_regress/t/t_trace_dumpvars_task_no_inl.v delete mode 100644 test_regress/t/t_trace_dumpvars_top.v delete mode 100644 test_regress/t/t_trace_dumpvars_wire.v create mode 100644 test_regress/t/trace_dumpvars_common.py diff --git a/test_regress/t/t_trace_dumpvars.py b/test_regress/t/t_trace_dumpvars.py index d2549038e..59ddf5500 100644 --- a/test_regress/t/t_trace_dumpvars.py +++ b/test_regress/t/t_trace_dumpvars.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars.v b/test_regress/t/t_trace_dumpvars.v index 5c2063a08..d7758b922 100644 --- a/test_regress/t/t_trace_dumpvars.v +++ b/test_regress/t/t_trace_dumpvars.v @@ -6,33 +6,379 @@ `define STRINGIFY(x) `"x`" -module t( +/* verilator lint_off MULTITOP */ + +`ifdef TRACE_DUMPVARS_CASE_HIER_STRUCT +`define TRACE_DUMPVARS_PACKED_STRUCT_BRANCH +`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_STRUCT +`define TRACE_DUMPVARS_PACKED_STRUCT_BRANCH +`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_STRUCT2 +`define TRACE_DUMPVARS_PACKED_STRUCT_BRANCH +`endif + +`ifdef TRACE_DUMPVARS_CASE_HIER_ARRAY +`define TRACE_DUMPVARS_ARRAY_BRANCH +`elsif TRACE_DUMPVARS_CASE_HIER_ARRAY_OOB +`define TRACE_DUMPVARS_ARRAY_BRANCH +`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_ARRAY +`define TRACE_DUMPVARS_ARRAY_BRANCH +`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_ARRAY_OOB +`define TRACE_DUMPVARS_ARRAY_BRANCH +`endif + +`ifdef TRACE_DUMPVARS_CASE_FUNC +`define TRACE_DUMPVARS_TASK_BRANCH +`elsif TRACE_DUMPVARS_CASE_TASK +`define TRACE_DUMPVARS_TASK_BRANCH +`elsif TRACE_DUMPVARS_CASE_TASK2 +`define TRACE_DUMPVARS_TASK_BRANCH +`endif + +`ifdef TRACE_DUMPVARS_PACKED_STRUCT_BRANCH +typedef struct packed { + logic [31:0] add; + logic [31:0] cyc; + logic [31:0] inner; +} deep_t; + +typedef struct packed { + deep_t deep; + logic [31:0] value; +} top_t; +`endif + +`ifdef TRACE_DUMPVARS_TASK_BRANCH +function int get_trace_level; + return 1; +endfunction + +function void varsdump; + $dumpvars(get_trace_level()); +endfunction + +`ifdef TRACE_DUMPVARS_CASE_FUNC +function void setup_trace; + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + varsdump(); +endfunction +`else +task setup_trace; + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + varsdump(); +endtask +`endif + +`ifdef TRACE_DUMPVARS_CASE_TASK2 +task setup_trace_nested; + setup_trace(); +endtask +`endif +`endif + +module t +`ifdef TRACE_DUMPVARS_CASE_ADD_MODULE +; +`else +( input clk ); +`endif int cyc; +`ifdef TRACE_DUMPVARS_CASE_ADD_MODULE + logic clk; +`endif +`ifdef TRACE_DUMPVARS_CASE_CONTEXT + int top; +`endif +`ifdef TRACE_DUMPVARS_CASE_WIRE + int counter; +`endif +`ifdef TRACE_DUMPVARS_PACKED_STRUCT_BRANCH + top_t mystruct; +`endif +`ifdef TRACE_DUMPVARS_CASE_STRUCT + typedef struct packed { + logic [7:0] \x ; + logic [7:0] y; + } point_t; + typedef struct packed { + point_t origin; + point_t size; + } rect_t; + + rect_t rect; + point_t \pt ; +`endif + +`ifdef TRACE_DUMPVARS_ARRAY_BRANCH + sub #(10) arr[2](.*); +`elsif TRACE_DUMPVARS_CASE_GEN + genvar i; + generate + for (i = 0; i < 2; i = i + 1) begin : gen_sub + sub #(10 * (i + 1)) sub_i(.*); + end + endgenerate +`elsif TRACE_DUMPVARS_PACKED_STRUCT_BRANCH +`elsif TRACE_DUMPVARS_CASE_STRUCT + sub #(10) sub_a(.*); +`else sub #(10) sub_a(.*); sub #(20) sub_b(.*); +`endif + +`ifdef TRACE_DUMPVARS_CASE_ADD_MODULE + initial begin + clk = 0; + forever #1 clk = !clk; + end +`endif always @(posedge clk) begin cyc <= cyc + 1; +`ifdef TRACE_DUMPVARS_CASE_STRUCT + \pt .\x <= \pt .\x + 1; + \pt .y <= \pt .y + 2; + rect.origin.\x <= rect.origin.\x + 1; + rect.origin.y <= rect.origin.y + 2; + rect.size.\x <= 8'd100; + rect.size.y <= 8'd200; +`endif +`ifdef TRACE_DUMPVARS_CASE_WIRE + counter <= counter + 2; +`endif +`ifdef TRACE_DUMPVARS_CASE_ADD_MODULE + if (cyc == 1) begin + $dumpfile({`STRINGIFY(`TEST_OBJ_DIR), "/simx1.vcd"}); + $dumpvars(0, sub_b); + end +`endif if (cyc == 5) begin $write("*-* All Finished *-*\n"); $finish; end end +`ifdef TRACE_DUMPVARS_CASE_ADD_MODULE + initial begin + $dumpfile({`STRINGIFY(`TEST_OBJ_DIR), "/simx0.vcd"}); + $dumpvars(1, sub_a); + end +`elsif TRACE_DUMPVARS_CASE_STRUCT initial begin $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - $dumpvars(0); + $dumpvars(1, rect.origin.\x ); + $dumpvars(1, \pt .\y ); end +`elsif TRACE_DUMPVARS_PACKED_STRUCT_BRANCH + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); +`ifdef TRACE_DUMPVARS_CASE_HIER_STRUCT + $dumpvars(1, t.mystruct.deep); +`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_STRUCT + $dumpvars(1, cpptop.t.mystruct.deep); +`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_STRUCT2 + $dumpvars(1, cpptop.t.mystruct.deep.inner); +`else +`error "Missing packed struct trace_dumpvars case" +`endif + end + + always_comb begin + mystruct.value = cyc + 32'd10; + mystruct.deep.add = 32'd11; + mystruct.deep.cyc = cyc; + mystruct.deep.inner = cyc + mystruct.deep.add; + end +`elsif TRACE_DUMPVARS_ARRAY_BRANCH + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); +`ifdef TRACE_DUMPVARS_CASE_HIER_ARRAY + $dumpvars(1, t.arr[1].deep); +`elsif TRACE_DUMPVARS_CASE_HIER_ARRAY_OOB + $dumpvars(1, t.arr[999].deep); +`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_ARRAY + $dumpvars(1, cpptop.t.arr[1].deep); +`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_ARRAY_OOB + $dumpvars(1, cpptop.t.arr[999].deep); +`else +`error "Missing array trace_dumpvars case" +`endif + end +`elsif TRACE_DUMPVARS_CASE_GEN + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + $dumpvars(0, gen_sub[0]); + end +`elsif TRACE_DUMPVARS_TASK_BRANCH +`elsif TRACE_DUMPVARS_CASE_HIER_GLOBAL +`elsif TRACE_DUMPVARS_CASE_HIER_GLOBAL_TASK +`elsif TRACE_DUMPVARS_CASE_NONCONST_SCOPE + initial begin: dumpblock + int level; + if (!$value$plusargs("LEVEL=%d", level)) level = 0; + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + $dumpvars(level, t.sub_a); + end +`elsif TRACE_DUMPVARS_CASE_SUB + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + end +`elsif TRACE_DUMPVARS_CASE_SUB0 + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + end +`else + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); +`ifdef TRACE_DUMPVARS_CASE_BASE + $dumpvars(0); +`elsif TRACE_DUMPVARS_CASE_SCOPE + $dumpvars(0, sub_a); +`elsif TRACE_DUMPVARS_CASE_MULTI_SCOPE + $dumpvars(0+1, t, t.sub_a.deep_i); +`elsif TRACE_DUMPVARS_CASE_ABS_SCOPE + $dumpvars(0, t.sub_a); +`elsif TRACE_DUMPVARS_CASE_OVERRIDE + $dumpvars(1, t.sub_a.deep_i); + $dumpvars(0); +`elsif TRACE_DUMPVARS_CASE_CONTEXT + $dumpvars(1, t.sub_a.deep_i); + $dumpvars(0, top); +`elsif TRACE_DUMPVARS_CASE_LEVEL + $dumpvars(1); +`elsif TRACE_DUMPVARS_CASE_LEVEL_SCOPE + $dumpvars(1, sub_a); +`elsif TRACE_DUMPVARS_CASE_HIER_SCOPE + $dumpvars(1, sub_a.deep_i); +`elsif TRACE_DUMPVARS_CASE_WIRE + $dumpvars(0, cyc, counter); +`elsif TRACE_DUMPVARS_CASE_T + $dumpvars(t); +`elsif TRACE_DUMPVARS_CASE_MISSING_SCOPE + $dumpvars(0, missing_module); +`elsif TRACE_DUMPVARS_CASE_MISSING2 + $dumpvars(t.missingname); +`elsif TRACE_DUMPVARS_CASE_MISSING3 + $dumpvars(0, t.missing); +`elsif TRACE_DUMPVARS_CASE_MISSING4 + $dumpvars(0, t.sub_a.missing); +`elsif TRACE_DUMPVARS_CASE_MISSING5 + $dumpvars(0, missing.child); +`elsif TRACE_DUMPVARS_CASE_CPPTOP + $dumpvars(0, cpptop, cpptop.t); +`elsif TRACE_DUMPVARS_CASE_CPPTOP2 + $dumpvars(0, cpptop, cpptop.notfound); +`elsif TRACE_DUMPVARS_CASE_CPPTOP_MISSING + $dumpvars(0, missing_module); +`elsif TRACE_DUMPVARS_CASE_CPPTOP_MISSING2 + $dumpvars(t.missingname); +`elsif TRACE_DUMPVARS_CASE_CPPTOP_MISSING3 + $dumpvars(0, t.missing); +`elsif TRACE_DUMPVARS_CASE_CPPTOP_MISSING4 + $dumpvars(0, t.sub_a.missing); +`else +`error "Missing trace_dumpvars case define" +`endif + end +`endif endmodule module sub #( - parameter int ADD + parameter int ADD = 0 )( input int cyc ); int value; always_comb value = cyc + ADD; + +`ifdef TRACE_DUMPVARS_CASE_HIER_GLOBAL_TASK + function void dump_from_func; + $dumpvars(1, t); + endfunction + + task setup_trace; + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + dump_from_func(); + endtask +`endif + +`ifdef TRACE_DUMPVARS_ARRAY_BRANCH + deep #(ADD + 1) deep(.*); +`elsif TRACE_DUMPVARS_CASE_BASE +`elsif TRACE_DUMPVARS_CASE_WIRE +`elsif TRACE_DUMPVARS_CASE_CPPTOP +`elsif TRACE_DUMPVARS_CASE_CPPTOP2 +`elsif TRACE_DUMPVARS_CASE_STRUCT +`else + deep #(ADD + 1) deep_i(.*); +`endif + +`ifdef TRACE_DUMPVARS_CASE_HIER_GLOBAL + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + $dumpvars(1, t); + end +`elsif TRACE_DUMPVARS_CASE_HIER_GLOBAL_TASK + initial begin + setup_trace(); + end +`elsif TRACE_DUMPVARS_CASE_TASK2 + initial begin + setup_trace_nested; + end +`elsif TRACE_DUMPVARS_TASK_BRANCH + initial begin + setup_trace; + end +`elsif TRACE_DUMPVARS_CASE_SUB + initial begin + $dumpvars(1); + end +`elsif TRACE_DUMPVARS_CASE_SUB0 + initial begin + $dumpvars(0); + end +`endif endmodule + +module deep #( + parameter int ADD = 0 +)( + input int cyc +); + int inner; +`ifdef TRACE_DUMPVARS_CASE_HIER_GLOBAL + int t; +`elsif TRACE_DUMPVARS_CASE_HIER_GLOBAL_TASK + int t; +`endif + always_comb inner = cyc + ADD; + +`ifdef TRACE_DUMPVARS_CASE_HIER_GLOBAL_TASK + function void dump_from_func; + $dumpvars(1, t); + endfunction + + task setup_trace; + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + dump_from_func(); + endtask + + initial begin + setup_trace(); + end +`elsif TRACE_DUMPVARS_CASE_HIER_GLOBAL + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + $dumpvars(1, t); + end +`elsif TRACE_DUMPVARS_CASE_CONTEXT + initial begin + $dumpvars(0); + end +`endif +endmodule + +/* verilator lint_on MULTITOP */ diff --git a/test_regress/t/t_trace_dumpvars_abs_scope.py b/test_regress/t/t_trace_dumpvars_abs_scope.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_abs_scope.py +++ b/test_regress/t/t_trace_dumpvars_abs_scope.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_abs_scope.v b/test_regress/t/t_trace_dumpvars_abs_scope.v deleted file mode 100644 index 2a225c3cb..000000000 --- a/test_regress/t/t_trace_dumpvars_abs_scope.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with absolute hierarchical scope path - $dumpvars(0, t.sub_a); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_add_module.py b/test_regress/t/t_trace_dumpvars_add_module.py index 006c898da..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_add_module.py +++ b/test_regress/t/t_trace_dumpvars_add_module.py @@ -8,14 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --timing --trace-vcd']) - -test.execute() - -test.vcd_identical(test.obj_dir + '/simx0.vcd', test.t_dir + '/t_trace_dumpvars_add_module_0.out') -test.vcd_identical(test.obj_dir + '/simx1.vcd', test.t_dir + '/t_trace_dumpvars_add_module_1.out') - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_add_module.v b/test_regress/t/t_trace_dumpvars_add_module.v deleted file mode 100644 index bf812302c..000000000 --- a/test_regress/t/t_trace_dumpvars_add_module.v +++ /dev/null @@ -1,58 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( -); - logic clk; - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - initial begin - clk = 0; - forever #1 clk = !clk; - end - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 1) begin - $dumpfile({`STRINGIFY(`TEST_OBJ_DIR), "/simx1.vcd"}); - $dumpvars(0, sub_b); - end - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile({`STRINGIFY(`TEST_OBJ_DIR), "/simx0.vcd"}); - $dumpvars(1, sub_a); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_context.py b/test_regress/t/t_trace_dumpvars_context.py index 5a79df61f..558d60a06 100644 --- a/test_regress/t/t_trace_dumpvars_context.py +++ b/test_regress/t/t_trace_dumpvars_context.py @@ -8,14 +8,9 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_context.v b/test_regress/t/t_trace_dumpvars_context.v deleted file mode 100644 index 5bc230c54..000000000 --- a/test_regress/t/t_trace_dumpvars_context.v +++ /dev/null @@ -1,57 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - int top; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // First restrict to sub_a.deep_i only, then let deep_i issue $dumpvars(0) - // to confirm the no-target override still expands tracing globally. - $dumpvars(1, t.sub_a.deep_i); - $dumpvars(0, top); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; - - initial begin - $dumpvars(0); - end -endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop.py b/test_regress/t/t_trace_dumpvars_cpptop.py index e59720885..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop.py +++ b/test_regress/t/t_trace_dumpvars_cpptop.py @@ -8,20 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile( - make_main=False, - verilator_flags2=[ - '--cc', - '--exe', - '--trace-vcd', - 't/t_trace_dumpvars_cpptop.cpp', - ]) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_cpptop.v b/test_regress/t/t_trace_dumpvars_cpptop.v deleted file mode 100644 index 334e709e0..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop.v +++ /dev/null @@ -1,39 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // cpptop is defined in the C++ testbench as the root of the trace hierarchy, so $dumpvars(0, cpptop) should dump everything. - $dumpvars(0, cpptop, cpptop.t); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop2.cpp b/test_regress/t/t_trace_dumpvars_cpptop2.cpp deleted file mode 100644 index 83ccacb87..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop2.cpp +++ /dev/null @@ -1,36 +0,0 @@ -// -*- mode: C++; c-file-style: "cc-mode" -*- -// -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -#include - -#include - -#include VM_PREFIX_INCLUDE - -unsigned long long main_time = 0; -double sc_time_stamp() { return (double)main_time; } - -int main(int argc, char** argv) { - Verilated::debug(0); - Verilated::traceEverOn(true); - Verilated::commandArgs(argc, argv); - - // Name the top module "cpptop" instead of default "TOP" - std::unique_ptr top{new VM_PREFIX{"cpptop"}}; - top->clk = 0; - - while (!Verilated::gotFinish()) { - top->eval(); - ++main_time; - top->clk = !top->clk; - } - top->final(); - top.reset(); - printf("*-* All Finished *-*\n"); - return 0; -} diff --git a/test_regress/t/t_trace_dumpvars_cpptop2.out b/test_regress/t/t_trace_dumpvars_cpptop2.out index 7660a7232..a585565b4 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop2.out +++ b/test_regress/t/t_trace_dumpvars_cpptop2.out @@ -1,5 +1,5 @@ -%Error: t/t_trace_dumpvars_cpptop2.v:27:5: $dumpvars target not found: cpptop.notfound - 27 | $dumpvars(0, cpptop, cpptop.notfound); +%Error: t/t_trace_dumpvars.v:272:5: $dumpvars target not found: cpptop.notfound + 272 | $dumpvars(0, cpptop, cpptop.notfound); | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_trace_dumpvars_cpptop2.py b/test_regress/t/t_trace_dumpvars_cpptop2.py index b942b16fa..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop2.py +++ b/test_regress/t/t_trace_dumpvars_cpptop2.py @@ -8,18 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile( - fails=True, - make_main=False, - verilator_flags2=[ - '--cc', - '--exe', - '--trace-vcd', - 't/t_trace_dumpvars_cpptop.cpp', - ], - expect_filename=test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_cpptop2.v b/test_regress/t/t_trace_dumpvars_cpptop2.v deleted file mode 100644 index 4d3f29d36..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop2.v +++ /dev/null @@ -1,38 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - $dumpvars(0, cpptop, cpptop.notfound); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_array.cpp b/test_regress/t/t_trace_dumpvars_cpptop_hier_array.cpp deleted file mode 100644 index 83ccacb87..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_hier_array.cpp +++ /dev/null @@ -1,36 +0,0 @@ -// -*- mode: C++; c-file-style: "cc-mode" -*- -// -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -#include - -#include - -#include VM_PREFIX_INCLUDE - -unsigned long long main_time = 0; -double sc_time_stamp() { return (double)main_time; } - -int main(int argc, char** argv) { - Verilated::debug(0); - Verilated::traceEverOn(true); - Verilated::commandArgs(argc, argv); - - // Name the top module "cpptop" instead of default "TOP" - std::unique_ptr top{new VM_PREFIX{"cpptop"}}; - top->clk = 0; - - while (!Verilated::gotFinish()) { - top->eval(); - ++main_time; - top->clk = !top->clk; - } - top->final(); - top.reset(); - printf("*-* All Finished *-*\n"); - return 0; -} diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_array.py b/test_regress/t/t_trace_dumpvars_cpptop_hier_array.py index 4e8341f6c..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop_hier_array.py +++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_array.py @@ -8,20 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile( - make_main=False, - verilator_flags2=[ - '--cc', - '--exe', - '--trace-vcd', - 't/t_trace_dumpvars_cpptop_hier_array.cpp', - ]) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_array.v b/test_regress/t/t_trace_dumpvars_cpptop_hier_array.v deleted file mode 100644 index a36a7a8d5..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_hier_array.v +++ /dev/null @@ -1,49 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) arr[2](.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with an arrayed hierarchical scope path via cpptop. - $dumpvars(1, cpptop.t.arr[1].deep); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.cpp b/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.cpp deleted file mode 100644 index 83ccacb87..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.cpp +++ /dev/null @@ -1,36 +0,0 @@ -// -*- mode: C++; c-file-style: "cc-mode" -*- -// -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -#include - -#include - -#include VM_PREFIX_INCLUDE - -unsigned long long main_time = 0; -double sc_time_stamp() { return (double)main_time; } - -int main(int argc, char** argv) { - Verilated::debug(0); - Verilated::traceEverOn(true); - Verilated::commandArgs(argc, argv); - - // Name the top module "cpptop" instead of default "TOP" - std::unique_ptr top{new VM_PREFIX{"cpptop"}}; - top->clk = 0; - - while (!Verilated::gotFinish()) { - top->eval(); - ++main_time; - top->clk = !top->clk; - } - top->final(); - top.reset(); - printf("*-* All Finished *-*\n"); - return 0; -} diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.py b/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.py index 976058255..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.py +++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.py @@ -8,20 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile( - make_main=False, - verilator_flags2=[ - '--cc', - '--exe', - '--trace-vcd', - 't/t_trace_dumpvars_cpptop_hier_array_oob.cpp', - ]) - -test.execute() - -test.files_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.v b/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.v deleted file mode 100644 index 6a64c812f..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.v +++ /dev/null @@ -1,49 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) arr[2](.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with an out-of-range array index via cpptop. - $dumpvars(1, cpptop.t.arr[999].deep); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_global.cpp b/test_regress/t/t_trace_dumpvars_cpptop_hier_global.cpp deleted file mode 100644 index 83ccacb87..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_hier_global.cpp +++ /dev/null @@ -1,36 +0,0 @@ -// -*- mode: C++; c-file-style: "cc-mode" -*- -// -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -#include - -#include - -#include VM_PREFIX_INCLUDE - -unsigned long long main_time = 0; -double sc_time_stamp() { return (double)main_time; } - -int main(int argc, char** argv) { - Verilated::debug(0); - Verilated::traceEverOn(true); - Verilated::commandArgs(argc, argv); - - // Name the top module "cpptop" instead of default "TOP" - std::unique_ptr top{new VM_PREFIX{"cpptop"}}; - top->clk = 0; - - while (!Verilated::gotFinish()) { - top->eval(); - ++main_time; - top->clk = !top->clk; - } - top->final(); - top.reset(); - printf("*-* All Finished *-*\n"); - return 0; -} diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_global.py b/test_regress/t/t_trace_dumpvars_cpptop_hier_global.py index 9779f2f74..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop_hier_global.py +++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_global.py @@ -8,18 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile( - make_main=False, - verilator_flags2=[ - '--cc', - '--exe', - '--trace-vcd', - 't/t_trace_dumpvars_cpptop_hier_global.cpp', - ]) - -test.execute() - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_global.v b/test_regress/t/t_trace_dumpvars_cpptop_hier_global.v deleted file mode 100644 index 37dd5d357..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_hier_global.v +++ /dev/null @@ -1,56 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with hierarchical scope: level 1 limits to direct signals of t outside the scope - $dumpvars(1, t); - end -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - int t; - always_comb inner = cyc + ADD; - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - $dumpvars(1, t); - end -endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.cpp b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.cpp deleted file mode 100644 index 83ccacb87..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.cpp +++ /dev/null @@ -1,36 +0,0 @@ -// -*- mode: C++; c-file-style: "cc-mode" -*- -// -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -#include - -#include - -#include VM_PREFIX_INCLUDE - -unsigned long long main_time = 0; -double sc_time_stamp() { return (double)main_time; } - -int main(int argc, char** argv) { - Verilated::debug(0); - Verilated::traceEverOn(true); - Verilated::commandArgs(argc, argv); - - // Name the top module "cpptop" instead of default "TOP" - std::unique_ptr top{new VM_PREFIX{"cpptop"}}; - top->clk = 0; - - while (!Verilated::gotFinish()) { - top->eval(); - ++main_time; - top->clk = !top->clk; - } - top->final(); - top.reset(); - printf("*-* All Finished *-*\n"); - return 0; -} diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.py b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.py index 8947c16b2..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.py +++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.py @@ -8,21 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile( - make_main=False, - verilator_flags2=[ - '--cc', - '--exe', - '--trace-vcd', - '--trace-structs', - 't/t_trace_dumpvars_cpptop_hier_struct.cpp', - ]) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.v b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.v deleted file mode 100644 index 351212317..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.v +++ /dev/null @@ -1,46 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -typedef struct packed { - logic [31:0] add; - logic [31:0] cyc; - logic [31:0] inner; -} deep_t; - -typedef struct packed { - deep_t deep; - logic [31:0] value; -} top_t; - -module t( - input clk -); - int cyc; - top_t mystruct; - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with a traced struct sub-scope via cpptop. - $dumpvars(1, cpptop.t.mystruct.deep); - end - - always_comb begin - mystruct.value = cyc + 32'd10; - mystruct.deep.add = 32'd11; - mystruct.deep.cyc = cyc; - mystruct.deep.inner = cyc + mystruct.deep.add; - end -endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.cpp b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.cpp deleted file mode 100644 index 83ccacb87..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.cpp +++ /dev/null @@ -1,36 +0,0 @@ -// -*- mode: C++; c-file-style: "cc-mode" -*- -// -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -#include - -#include - -#include VM_PREFIX_INCLUDE - -unsigned long long main_time = 0; -double sc_time_stamp() { return (double)main_time; } - -int main(int argc, char** argv) { - Verilated::debug(0); - Verilated::traceEverOn(true); - Verilated::commandArgs(argc, argv); - - // Name the top module "cpptop" instead of default "TOP" - std::unique_ptr top{new VM_PREFIX{"cpptop"}}; - top->clk = 0; - - while (!Verilated::gotFinish()) { - top->eval(); - ++main_time; - top->clk = !top->clk; - } - top->final(); - top.reset(); - printf("*-* All Finished *-*\n"); - return 0; -} diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.py b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.py index dce00d975..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.py +++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.py @@ -8,19 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile( - make_main=False, - verilator_flags2=[ - '--cc', - '--exe', - '--trace-vcd', - '--trace-structs', - 't/t_trace_dumpvars_cpptop_hier_struct2.cpp', - ]) - -test.execute() - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.v b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.v deleted file mode 100644 index e15dc0c45..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.v +++ /dev/null @@ -1,46 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -typedef struct packed { - logic [31:0] add; - logic [31:0] cyc; - logic [31:0] inner; -} deep_t; - -typedef struct packed { - deep_t deep; - logic [31:0] value; -} top_t; - -module t( - input clk -); - int cyc; - top_t mystruct; - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with a struct leaf member via cpptop. - $dumpvars(1, cpptop.t.mystruct.deep.inner); - end - - always_comb begin - mystruct.value = cyc + 32'd10; - mystruct.deep.add = 32'd11; - mystruct.deep.cyc = cyc; - mystruct.deep.inner = cyc + mystruct.deep.add; - end -endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing.cpp b/test_regress/t/t_trace_dumpvars_cpptop_missing.cpp deleted file mode 100644 index 83ccacb87..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing.cpp +++ /dev/null @@ -1,36 +0,0 @@ -// -*- mode: C++; c-file-style: "cc-mode" -*- -// -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -#include - -#include - -#include VM_PREFIX_INCLUDE - -unsigned long long main_time = 0; -double sc_time_stamp() { return (double)main_time; } - -int main(int argc, char** argv) { - Verilated::debug(0); - Verilated::traceEverOn(true); - Verilated::commandArgs(argc, argv); - - // Name the top module "cpptop" instead of default "TOP" - std::unique_ptr top{new VM_PREFIX{"cpptop"}}; - top->clk = 0; - - while (!Verilated::gotFinish()) { - top->eval(); - ++main_time; - top->clk = !top->clk; - } - top->final(); - top.reset(); - printf("*-* All Finished *-*\n"); - return 0; -} diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing.out b/test_regress/t/t_trace_dumpvars_cpptop_missing.out index 1342a7374..def8decb6 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing.out +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing.out @@ -1,2 +1,2 @@ -%Error: t/t_trace_dumpvars_cpptop_missing.v:28: $dumpvars target not found: missing_module +%Error: t/t_trace_dumpvars.v:274: $dumpvars target not found: missing_module Aborting... diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing.py b/test_regress/t/t_trace_dumpvars_cpptop_missing.py index c5f10a6dd..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing.py +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing.py @@ -8,19 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile( - make_main=False, - verilator_flags2=[ - '--cc', - '--exe', - '--trace-vcd', - 't/t_trace_dumpvars_cpptop_missing.cpp', - ]) - -test.execute(fails=True, - expect_filename=test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing.v b/test_regress/t/t_trace_dumpvars_cpptop_missing.v deleted file mode 100644 index 52816b852..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with a non-existent module scope argument via cpptop. - $dumpvars(0, missing_module); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing2.cpp b/test_regress/t/t_trace_dumpvars_cpptop_missing2.cpp deleted file mode 100644 index 83ccacb87..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing2.cpp +++ /dev/null @@ -1,36 +0,0 @@ -// -*- mode: C++; c-file-style: "cc-mode" -*- -// -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -#include - -#include - -#include VM_PREFIX_INCLUDE - -unsigned long long main_time = 0; -double sc_time_stamp() { return (double)main_time; } - -int main(int argc, char** argv) { - Verilated::debug(0); - Verilated::traceEverOn(true); - Verilated::commandArgs(argc, argv); - - // Name the top module "cpptop" instead of default "TOP" - std::unique_ptr top{new VM_PREFIX{"cpptop"}}; - top->clk = 0; - - while (!Verilated::gotFinish()) { - top->eval(); - ++main_time; - top->clk = !top->clk; - } - top->final(); - top.reset(); - printf("*-* All Finished *-*\n"); - return 0; -} diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing2.out b/test_regress/t/t_trace_dumpvars_cpptop_missing2.out index 829ff6e43..a1a1a3e13 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing2.out +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing2.out @@ -1,5 +1,5 @@ -%Error: t/t_trace_dumpvars_cpptop_missing2.v:28:17: Can't find definition of 'missingname' in dotted variable/method: 't.missingname' - 28 | $dumpvars(t.missingname); +%Error: t/t_trace_dumpvars.v:276:17: Can't find definition of 'missingname' in dotted variable/method: 't.missingname' + 276 | $dumpvars(t.missingname); | ^~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing2.py b/test_regress/t/t_trace_dumpvars_cpptop_missing2.py index b0c45db1a..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing2.py +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing2.py @@ -8,18 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile( - fails=True, - make_main=False, - verilator_flags2=[ - '--cc', - '--exe', - '--trace-vcd', - 't/t_trace_dumpvars_cpptop_missing2.cpp', - ], - expect_filename=test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing2.v b/test_regress/t/t_trace_dumpvars_cpptop_missing2.v deleted file mode 100644 index 600be2574..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing2.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with a hierarchical non-existent scope argument via cpptop. - $dumpvars(t.missingname); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing3.cpp b/test_regress/t/t_trace_dumpvars_cpptop_missing3.cpp deleted file mode 100644 index 83ccacb87..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing3.cpp +++ /dev/null @@ -1,36 +0,0 @@ -// -*- mode: C++; c-file-style: "cc-mode" -*- -// -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -#include - -#include - -#include VM_PREFIX_INCLUDE - -unsigned long long main_time = 0; -double sc_time_stamp() { return (double)main_time; } - -int main(int argc, char** argv) { - Verilated::debug(0); - Verilated::traceEverOn(true); - Verilated::commandArgs(argc, argv); - - // Name the top module "cpptop" instead of default "TOP" - std::unique_ptr top{new VM_PREFIX{"cpptop"}}; - top->clk = 0; - - while (!Verilated::gotFinish()) { - top->eval(); - ++main_time; - top->clk = !top->clk; - } - top->final(); - top.reset(); - printf("*-* All Finished *-*\n"); - return 0; -} diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing3.out b/test_regress/t/t_trace_dumpvars_cpptop_missing3.out index f7ba9c4e1..9f778c04b 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing3.out +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing3.out @@ -1,2 +1,2 @@ -%Error: t/t_trace_dumpvars_cpptop_missing3.v:28: $dumpvars target not found: t.missing +%Error: t/t_trace_dumpvars.v:278: $dumpvars target not found: t.missing Aborting... diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing3.py b/test_regress/t/t_trace_dumpvars_cpptop_missing3.py index 642a2cb0b..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing3.py +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing3.py @@ -8,19 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile( - make_main=False, - verilator_flags2=[ - '--cc', - '--exe', - '--trace-vcd', - 't/t_trace_dumpvars_cpptop_missing3.cpp', - ]) - -test.execute(fails=True, - expect_filename=test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing3.v b/test_regress/t/t_trace_dumpvars_cpptop_missing3.v deleted file mode 100644 index e00189d61..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing3.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with level and hierarchical non-existent scope via cpptop. - $dumpvars(0, t.missing); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing4.cpp b/test_regress/t/t_trace_dumpvars_cpptop_missing4.cpp deleted file mode 100644 index 83ccacb87..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing4.cpp +++ /dev/null @@ -1,36 +0,0 @@ -// -*- mode: C++; c-file-style: "cc-mode" -*- -// -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -#include - -#include - -#include VM_PREFIX_INCLUDE - -unsigned long long main_time = 0; -double sc_time_stamp() { return (double)main_time; } - -int main(int argc, char** argv) { - Verilated::debug(0); - Verilated::traceEverOn(true); - Verilated::commandArgs(argc, argv); - - // Name the top module "cpptop" instead of default "TOP" - std::unique_ptr top{new VM_PREFIX{"cpptop"}}; - top->clk = 0; - - while (!Verilated::gotFinish()) { - top->eval(); - ++main_time; - top->clk = !top->clk; - } - top->final(); - top.reset(); - printf("*-* All Finished *-*\n"); - return 0; -} diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing4.out b/test_regress/t/t_trace_dumpvars_cpptop_missing4.out index 9c860bd10..cf0802e31 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing4.out +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing4.out @@ -1,2 +1,2 @@ -%Error: t/t_trace_dumpvars_cpptop_missing4.v:28: $dumpvars target not found: t.sub_a.missing +%Error: t/t_trace_dumpvars.v:280: $dumpvars target not found: t.sub_a.missing Aborting... diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing4.py b/test_regress/t/t_trace_dumpvars_cpptop_missing4.py index 5696a1b7f..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing4.py +++ b/test_regress/t/t_trace_dumpvars_cpptop_missing4.py @@ -8,19 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile( - make_main=False, - verilator_flags2=[ - '--cc', - '--exe', - '--trace-vcd', - 't/t_trace_dumpvars_cpptop_missing4.cpp', - ]) - -test.execute(fails=True, - expect_filename=test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing4.v b/test_regress/t/t_trace_dumpvars_cpptop_missing4.v deleted file mode 100644 index e03a6d18f..000000000 --- a/test_regress/t/t_trace_dumpvars_cpptop_missing4.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with a valid sub-scope but missing child via cpptop. - $dumpvars(0, t.sub_a.missing); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_func.py b/test_regress/t/t_trace_dumpvars_func.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_func.py +++ b/test_regress/t/t_trace_dumpvars_func.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_func.v b/test_regress/t/t_trace_dumpvars_func.v deleted file mode 100644 index cf70710da..000000000 --- a/test_regress/t/t_trace_dumpvars_func.v +++ /dev/null @@ -1,61 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -function int get_trace_level; - return 1; -endfunction - -function void varsdump; - $dumpvars(get_trace_level()); -endfunction - -function void setup_trace; - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - varsdump(); -endfunction - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - initial begin - setup_trace; - end - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_gen.py b/test_regress/t/t_trace_dumpvars_gen.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_gen.py +++ b/test_regress/t/t_trace_dumpvars_gen.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_gen.v b/test_regress/t/t_trace_dumpvars_gen.v deleted file mode 100644 index 1b6b0524b..000000000 --- a/test_regress/t/t_trace_dumpvars_gen.v +++ /dev/null @@ -1,55 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - // Generate block creates sub instances with named block scope - genvar i; - generate - for (i = 0; i < 2; i = i + 1) begin : gen_sub - sub #(10 * (i + 1)) sub_i(.*); - end - endgenerate - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Dump only gen_sub[0] and everything below it - $dumpvars(0, gen_sub[0]); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_hier_array.py b/test_regress/t/t_trace_dumpvars_hier_array.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_hier_array.py +++ b/test_regress/t/t_trace_dumpvars_hier_array.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_hier_array.v b/test_regress/t/t_trace_dumpvars_hier_array.v deleted file mode 100644 index dbe673d73..000000000 --- a/test_regress/t/t_trace_dumpvars_hier_array.v +++ /dev/null @@ -1,49 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) arr[2](.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with an arrayed hierarchical scope path. - $dumpvars(1, t.arr[1].deep); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_hier_array_oob.py b/test_regress/t/t_trace_dumpvars_hier_array_oob.py index 3ead6a6d5..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_hier_array_oob.py +++ b/test_regress/t/t_trace_dumpvars_hier_array_oob.py @@ -8,11 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_hier_array_oob.v b/test_regress/t/t_trace_dumpvars_hier_array_oob.v deleted file mode 100644 index 8da72ff52..000000000 --- a/test_regress/t/t_trace_dumpvars_hier_array_oob.v +++ /dev/null @@ -1,49 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) arr[2](.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with an out-of-range array index. - $dumpvars(1, t.arr[999].deep); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_hier_global.py b/test_regress/t/t_trace_dumpvars_hier_global.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_hier_global.py +++ b/test_regress/t/t_trace_dumpvars_hier_global.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_hier_global.v b/test_regress/t/t_trace_dumpvars_hier_global.v deleted file mode 100644 index 37dd5d357..000000000 --- a/test_regress/t/t_trace_dumpvars_hier_global.v +++ /dev/null @@ -1,56 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with hierarchical scope: level 1 limits to direct signals of t outside the scope - $dumpvars(1, t); - end -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - int t; - always_comb inner = cyc + ADD; - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - $dumpvars(1, t); - end -endmodule diff --git a/test_regress/t/t_trace_dumpvars_hier_global_task.py b/test_regress/t/t_trace_dumpvars_hier_global_task.py index 38f138c77..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_hier_global_task.py +++ b/test_regress/t/t_trace_dumpvars_hier_global_task.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd --fno-inline']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_hier_global_task.v b/test_regress/t/t_trace_dumpvars_hier_global_task.v deleted file mode 100644 index 5877a243c..000000000 --- a/test_regress/t/t_trace_dumpvars_hier_global_task.v +++ /dev/null @@ -1,71 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - function void dump_from_func; - $dumpvars(1, t); - endfunction - - task setup_trace; - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - dump_from_func(); - endtask - - deep #(ADD + 1) deep_i(.*); - - initial begin - setup_trace(); - end -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - int t; - always_comb inner = cyc + ADD; - - function void dump_from_func; - $dumpvars(1, t); - endfunction - - task setup_trace; - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - dump_from_func(); - endtask - - initial begin - setup_trace(); - end -endmodule diff --git a/test_regress/t/t_trace_dumpvars_hier_scope.py b/test_regress/t/t_trace_dumpvars_hier_scope.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_hier_scope.py +++ b/test_regress/t/t_trace_dumpvars_hier_scope.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_hier_scope.v b/test_regress/t/t_trace_dumpvars_hier_scope.v deleted file mode 100644 index 97c3bfd55..000000000 --- a/test_regress/t/t_trace_dumpvars_hier_scope.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with hierarchical scope: level 1 limits to direct signals of sub_a.deep_i - $dumpvars(1, sub_a.deep_i); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_hier_struct.py b/test_regress/t/t_trace_dumpvars_hier_struct.py index 791c137e1..558d60a06 100644 --- a/test_regress/t/t_trace_dumpvars_hier_struct.py +++ b/test_regress/t/t_trace_dumpvars_hier_struct.py @@ -8,14 +8,9 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd --trace-structs']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_hier_struct.v b/test_regress/t/t_trace_dumpvars_hier_struct.v deleted file mode 100644 index 82614345a..000000000 --- a/test_regress/t/t_trace_dumpvars_hier_struct.v +++ /dev/null @@ -1,46 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -typedef struct packed { - logic [31:0] add; - logic [31:0] cyc; - logic [31:0] inner; -} deep_t; - -typedef struct packed { - deep_t deep; - logic [31:0] value; -} top_t; - -module t( - input clk -); - int cyc; - top_t mystruct; - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with a traced struct sub-scope. - $dumpvars(1, t.mystruct.deep); - end - - always_comb begin - mystruct.value = cyc + 32'd10; - mystruct.deep.add = 32'd11; - mystruct.deep.cyc = cyc; - mystruct.deep.inner = cyc + mystruct.deep.add; - end -endmodule diff --git a/test_regress/t/t_trace_dumpvars_level.py b/test_regress/t/t_trace_dumpvars_level.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_level.py +++ b/test_regress/t/t_trace_dumpvars_level.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_level.v b/test_regress/t/t_trace_dumpvars_level.v deleted file mode 100644 index df73db139..000000000 --- a/test_regress/t/t_trace_dumpvars_level.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with level argument (level 1 = top-level signals only) - $dumpvars(1); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_level_scope.py b/test_regress/t/t_trace_dumpvars_level_scope.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_level_scope.py +++ b/test_regress/t/t_trace_dumpvars_level_scope.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_level_scope.v b/test_regress/t/t_trace_dumpvars_level_scope.v deleted file mode 100644 index b7863aee2..000000000 --- a/test_regress/t/t_trace_dumpvars_level_scope.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with level AND scope: level 1 limits to sub_a direct signals only - $dumpvars(1, sub_a); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_missing2.out b/test_regress/t/t_trace_dumpvars_missing2.out index 6f63f58e5..34d4cf6c8 100644 --- a/test_regress/t/t_trace_dumpvars_missing2.out +++ b/test_regress/t/t_trace_dumpvars_missing2.out @@ -1,5 +1,5 @@ -%Error: t/t_trace_dumpvars_missing2.v:28:17: Can't find definition of 'missingname' in dotted variable/method: 't.missingname' - 28 | $dumpvars(t.missingname); +%Error: t/t_trace_dumpvars.v:262:17: Can't find definition of 'missingname' in dotted variable/method: 't.missingname' + 262 | $dumpvars(t.missingname); | ^~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_trace_dumpvars_missing2.py b/test_regress/t/t_trace_dumpvars_missing2.py index b00fb4934..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_missing2.py +++ b/test_regress/t/t_trace_dumpvars_missing2.py @@ -8,10 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(fails=True, verilator_flags2=['--binary --trace-vcd'], - expect_filename=test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_missing2.v b/test_regress/t/t_trace_dumpvars_missing2.v deleted file mode 100644 index 0f54a11c6..000000000 --- a/test_regress/t/t_trace_dumpvars_missing2.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with a hierarchical non-existent scope argument - $dumpvars(t.missingname); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_missing3.out b/test_regress/t/t_trace_dumpvars_missing3.out index 5f9651d7e..ff13ccdd2 100644 --- a/test_regress/t/t_trace_dumpvars_missing3.out +++ b/test_regress/t/t_trace_dumpvars_missing3.out @@ -1,5 +1,5 @@ -%Error: t/t_trace_dumpvars_missing3.v:28:5: $dumpvars target not found: t.missing - 28 | $dumpvars(0, t.missing); +%Error: t/t_trace_dumpvars.v:264:5: $dumpvars target not found: t.missing + 264 | $dumpvars(0, t.missing); | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_trace_dumpvars_missing3.py b/test_regress/t/t_trace_dumpvars_missing3.py index b00fb4934..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_missing3.py +++ b/test_regress/t/t_trace_dumpvars_missing3.py @@ -8,10 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(fails=True, verilator_flags2=['--binary --trace-vcd'], - expect_filename=test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_missing3.v b/test_regress/t/t_trace_dumpvars_missing3.v deleted file mode 100644 index c00c8687a..000000000 --- a/test_regress/t/t_trace_dumpvars_missing3.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with level and hierarchical non-existent scope - $dumpvars(0, t.missing); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_missing4.out b/test_regress/t/t_trace_dumpvars_missing4.out index cb1dfa5fc..692c591c2 100644 --- a/test_regress/t/t_trace_dumpvars_missing4.out +++ b/test_regress/t/t_trace_dumpvars_missing4.out @@ -1,5 +1,5 @@ -%Error: t/t_trace_dumpvars_missing4.v:28:5: $dumpvars target not found: t.sub_a.missing - 28 | $dumpvars(0, t.sub_a.missing); +%Error: t/t_trace_dumpvars.v:266:5: $dumpvars target not found: t.sub_a.missing + 266 | $dumpvars(0, t.sub_a.missing); | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_trace_dumpvars_missing4.py b/test_regress/t/t_trace_dumpvars_missing4.py index b00fb4934..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_missing4.py +++ b/test_regress/t/t_trace_dumpvars_missing4.py @@ -8,10 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(fails=True, verilator_flags2=['--binary --trace-vcd'], - expect_filename=test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_missing4.v b/test_regress/t/t_trace_dumpvars_missing4.v deleted file mode 100644 index 288885aaa..000000000 --- a/test_regress/t/t_trace_dumpvars_missing4.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with a valid sub-scope but missing child - $dumpvars(0, t.sub_a.missing); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_missing5.out b/test_regress/t/t_trace_dumpvars_missing5.out index a3e49d998..1301b5faf 100644 --- a/test_regress/t/t_trace_dumpvars_missing5.out +++ b/test_regress/t/t_trace_dumpvars_missing5.out @@ -1,5 +1,5 @@ -%Error: t/t_trace_dumpvars_missing5.v:28:5: $dumpvars target not found: missing.child - 28 | $dumpvars(0, missing.child); +%Error: t/t_trace_dumpvars.v:268:5: $dumpvars target not found: missing.child + 268 | $dumpvars(0, missing.child); | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_trace_dumpvars_missing5.py b/test_regress/t/t_trace_dumpvars_missing5.py index 8a19e71bf..5d72fbb34 100644 --- a/test_regress/t/t_trace_dumpvars_missing5.py +++ b/test_regress/t/t_trace_dumpvars_missing5.py @@ -8,10 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(fails=True, verilator_flags2=['--binary --trace-vcd'], - expect_filename=test.golden_filename) - -test.passes() \ No newline at end of file +trace_dumpvars_common.run(test) \ No newline at end of file diff --git a/test_regress/t/t_trace_dumpvars_missing5.v b/test_regress/t/t_trace_dumpvars_missing5.v deleted file mode 100644 index 28eb3e1b8..000000000 --- a/test_regress/t/t_trace_dumpvars_missing5.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with a missing multi-component target under --main. - $dumpvars(0, missing.child); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule \ No newline at end of file diff --git a/test_regress/t/t_trace_dumpvars_missing_scope.out b/test_regress/t/t_trace_dumpvars_missing_scope.out index 7272e6db5..dfaa1f61a 100644 --- a/test_regress/t/t_trace_dumpvars_missing_scope.out +++ b/test_regress/t/t_trace_dumpvars_missing_scope.out @@ -1,5 +1,5 @@ -%Error: t/t_trace_dumpvars_missing_scope.v:28:5: $dumpvars target not found: missing_module - 28 | $dumpvars(0, missing_module); +%Error: t/t_trace_dumpvars.v:260:5: $dumpvars target not found: missing_module + 260 | $dumpvars(0, missing_module); | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_trace_dumpvars_missing_scope.py b/test_regress/t/t_trace_dumpvars_missing_scope.py index b00fb4934..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_missing_scope.py +++ b/test_regress/t/t_trace_dumpvars_missing_scope.py @@ -8,10 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(fails=True, verilator_flags2=['--binary --trace-vcd'], - expect_filename=test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_missing_scope.v b/test_regress/t/t_trace_dumpvars_missing_scope.v deleted file mode 100644 index f7c24a635..000000000 --- a/test_regress/t/t_trace_dumpvars_missing_scope.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with a non-existent module scope argument - $dumpvars(0, missing_module); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_multi_scope.py b/test_regress/t/t_trace_dumpvars_multi_scope.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_multi_scope.py +++ b/test_regress/t/t_trace_dumpvars_multi_scope.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_multi_scope.v b/test_regress/t/t_trace_dumpvars_multi_scope.v deleted file mode 100644 index ae673be07..000000000 --- a/test_regress/t/t_trace_dumpvars_multi_scope.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test multiple scopes with non-constant level expression - $dumpvars(0+1, t, t.sub_a.deep_i); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_nonconst_scope.py b/test_regress/t/t_trace_dumpvars_nonconst_scope.py index 14865b871..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_nonconst_scope.py +++ b/test_regress/t/t_trace_dumpvars_nonconst_scope.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute(all_run_flags=['+LEVEL=0']) - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_nonconst_scope.v b/test_regress/t/t_trace_dumpvars_nonconst_scope.v deleted file mode 100644 index 3664cc288..000000000 --- a/test_regress/t/t_trace_dumpvars_nonconst_scope.v +++ /dev/null @@ -1,52 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin: dumpblock - int level; - if (!$value$plusargs("LEVEL=%d", level)) level = 0; - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with non-constant level expression and scope argument - $dumpvars(level, t.sub_a); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_override.py b/test_regress/t/t_trace_dumpvars_override.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_override.py +++ b/test_regress/t/t_trace_dumpvars_override.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_override.v b/test_regress/t/t_trace_dumpvars_override.v deleted file mode 100644 index 9d45daa56..000000000 --- a/test_regress/t/t_trace_dumpvars_override.v +++ /dev/null @@ -1,51 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // First restrict to deep_i only, then override with $dumpvars(0) to dump all - $dumpvars(1, t.sub_a.deep_i); - $dumpvars(0); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_scope.py b/test_regress/t/t_trace_dumpvars_scope.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_scope.py +++ b/test_regress/t/t_trace_dumpvars_scope.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_scope.v b/test_regress/t/t_trace_dumpvars_scope.v deleted file mode 100644 index 6b5621bc4..000000000 --- a/test_regress/t/t_trace_dumpvars_scope.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with module scope argument - $dumpvars(0, sub_a); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_struct.py b/test_regress/t/t_trace_dumpvars_struct.py index d4c312914..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_struct.py +++ b/test_regress/t/t_trace_dumpvars_struct.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd --trace-structs']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_struct.v b/test_regress/t/t_trace_dumpvars_struct.v deleted file mode 100644 index 8f7d3e8e9..000000000 --- a/test_regress/t/t_trace_dumpvars_struct.v +++ /dev/null @@ -1,57 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - typedef struct packed { - logic [7:0] \x ; - logic [7:0] y; - } point_t; - - typedef struct packed { - point_t origin; - point_t size; - } rect_t; - - int cyc; - rect_t rect; - point_t \pt ; - - sub #(10) sub_a(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - \pt .\x <= \pt .\x + 1; - \pt .y <= \pt .y + 2; - rect.origin.\x <= rect.origin.\x + 1; - rect.origin.y <= rect.origin.y + 2; - rect.size.\x <= 8'd100; - rect.size.y <= 8'd200; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Target a single escaped struct member in $dumpvars. - $dumpvars(1, rect.origin.\x ); - $dumpvars(1, \pt .\y ); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_sub.py b/test_regress/t/t_trace_dumpvars_sub.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_sub.py +++ b/test_regress/t/t_trace_dumpvars_sub.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_sub.v b/test_regress/t/t_trace_dumpvars_sub.v deleted file mode 100644 index b79b4012b..000000000 --- a/test_regress/t/t_trace_dumpvars_sub.v +++ /dev/null @@ -1,54 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); - - // $dumpvars called from sub module scope with level 1 - // Should dump only this sub module's direct signals, not deep_i's - initial begin - $dumpvars(1); - end -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_sub0.py b/test_regress/t/t_trace_dumpvars_sub0.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_sub0.py +++ b/test_regress/t/t_trace_dumpvars_sub0.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_sub0.v b/test_regress/t/t_trace_dumpvars_sub0.v deleted file mode 100644 index 409aab752..000000000 --- a/test_regress/t/t_trace_dumpvars_sub0.v +++ /dev/null @@ -1,54 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); - - // $dumpvars called from sub module scope with level 0 - // Should dump all signals in this sub module and below (including deep_i) - initial begin - $dumpvars(0); - end -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_t.out b/test_regress/t/t_trace_dumpvars_t.out index 439aa8cfc..564660194 100644 --- a/test_regress/t/t_trace_dumpvars_t.out +++ b/test_regress/t/t_trace_dumpvars_t.out @@ -1,5 +1,5 @@ -%Error: t/t_trace_dumpvars_t.v:28:15: Can't find definition of variable: 't' - 28 | $dumpvars(t); +%Error: t/t_trace_dumpvars.v:258:15: Can't find definition of variable: 't' + 258 | $dumpvars(t); | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_trace_dumpvars_t.py b/test_regress/t/t_trace_dumpvars_t.py index b00fb4934..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_t.py +++ b/test_regress/t/t_trace_dumpvars_t.py @@ -8,10 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(fails=True, verilator_flags2=['--binary --trace-vcd'], - expect_filename=test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_t.v b/test_regress/t/t_trace_dumpvars_t.v deleted file mode 100644 index 29d4138b3..000000000 --- a/test_regress/t/t_trace_dumpvars_t.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with module type name as argument - $dumpvars(t); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_task.py b/test_regress/t/t_trace_dumpvars_task.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_task.py +++ b/test_regress/t/t_trace_dumpvars_task.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_task.v b/test_regress/t/t_trace_dumpvars_task.v deleted file mode 100644 index b8566d9bf..000000000 --- a/test_regress/t/t_trace_dumpvars_task.v +++ /dev/null @@ -1,61 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -function int get_trace_level; - return 1; -endfunction - -function void varsdump; - $dumpvars(get_trace_level()); -endfunction - -task setup_trace; - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - varsdump(); -endtask - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - initial begin - setup_trace; - end - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_task2.py b/test_regress/t/t_trace_dumpvars_task2.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_task2.py +++ b/test_regress/t/t_trace_dumpvars_task2.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_task2.v b/test_regress/t/t_trace_dumpvars_task2.v deleted file mode 100644 index 2c3de1177..000000000 --- a/test_regress/t/t_trace_dumpvars_task2.v +++ /dev/null @@ -1,65 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -function int get_trace_level; - return 1; -endfunction - -function void varsdump; - $dumpvars(get_trace_level()); -endfunction - -task setup_trace; - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - varsdump(); -endtask - -task setup_trace_nested; - setup_trace(); -endtask - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - initial begin - setup_trace_nested; - end - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_task2_no_inl.py b/test_regress/t/t_trace_dumpvars_task2_no_inl.py index 38f138c77..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_task2_no_inl.py +++ b/test_regress/t/t_trace_dumpvars_task2_no_inl.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd --fno-inline']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_task2_no_inl.v b/test_regress/t/t_trace_dumpvars_task2_no_inl.v deleted file mode 100644 index 2c3de1177..000000000 --- a/test_regress/t/t_trace_dumpvars_task2_no_inl.v +++ /dev/null @@ -1,65 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -function int get_trace_level; - return 1; -endfunction - -function void varsdump; - $dumpvars(get_trace_level()); -endfunction - -task setup_trace; - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - varsdump(); -endtask - -task setup_trace_nested; - setup_trace(); -endtask - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - initial begin - setup_trace_nested; - end - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_task_no_inl.py b/test_regress/t/t_trace_dumpvars_task_no_inl.py index 38f138c77..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_task_no_inl.py +++ b/test_regress/t/t_trace_dumpvars_task_no_inl.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd --fno-inline']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_task_no_inl.v b/test_regress/t/t_trace_dumpvars_task_no_inl.v deleted file mode 100644 index b8566d9bf..000000000 --- a/test_regress/t/t_trace_dumpvars_task_no_inl.v +++ /dev/null @@ -1,61 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -function int get_trace_level; - return 1; -endfunction - -function void varsdump; - $dumpvars(get_trace_level()); -endfunction - -task setup_trace; - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - varsdump(); -endtask - -module t( - input clk -); - int cyc; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; - - initial begin - setup_trace; - end - - deep #(ADD + 1) deep_i(.*); -endmodule - -module deep #( - parameter int ADD -)( - input int cyc -); - int inner; - always_comb inner = cyc + ADD; -endmodule diff --git a/test_regress/t/t_trace_dumpvars_top.py b/test_regress/t/t_trace_dumpvars_top.py index e69de29bb..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_top.py +++ b/test_regress/t/t_trace_dumpvars_top.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_dumpvars_common + +test.scenarios('vlt') + +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_top.v b/test_regress/t/t_trace_dumpvars_top.v deleted file mode 100644 index e69de29bb..000000000 diff --git a/test_regress/t/t_trace_dumpvars_wire.py b/test_regress/t/t_trace_dumpvars_wire.py index e6571964d..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_wire.py +++ b/test_regress/t/t_trace_dumpvars_wire.py @@ -8,13 +8,8 @@ # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap +import trace_dumpvars_common test.scenarios('vlt') -test.compile(verilator_flags2=['--binary --trace-vcd']) - -test.execute() - -test.vcd_identical(test.trace_filename, test.golden_filename) - -test.passes() +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_wire.v b/test_regress/t/t_trace_dumpvars_wire.v deleted file mode 100644 index 8a8714ac5..000000000 --- a/test_regress/t/t_trace_dumpvars_wire.v +++ /dev/null @@ -1,41 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain. -// SPDX-FileCopyrightText: 2026 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define STRINGIFY(x) `"x`" - -module t( - input clk -); - int cyc; - int counter; - - sub #(10) sub_a(.*); - sub #(20) sub_b(.*); - - always @(posedge clk) begin - cyc <= cyc + 1; - counter <= counter + 2; - if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - - initial begin - $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); - // Test $dumpvars with specific wire names - $dumpvars(0, cyc, counter); - end -endmodule - -module sub #( - parameter int ADD -)( - input int cyc -); - int value; - always_comb value = cyc + ADD; -endmodule diff --git a/test_regress/t/trace_dumpvars_common.py b/test_regress/t/trace_dumpvars_common.py new file mode 100644 index 000000000..164b81538 --- /dev/null +++ b/test_regress/t/trace_dumpvars_common.py @@ -0,0 +1,148 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import os +import re + + +_SHARED_TOP = "t/t_trace_dumpvars.v" +_SHARED_CPPTOP = "t/t_trace_dumpvars_cpptop.cpp" + +_COMPILE_FAIL_CASES = { + "cpptop2", + "cpptop_missing2", + "missing_scope", + "missing2", + "missing3", + "missing4", + "missing5", + "t", +} + +_EXECUTE_FAIL_CASES = { + "cpptop_missing", + "cpptop_missing3", + "cpptop_missing4", +} + +_CPPTOP_CASES = { + "cpptop", + "cpptop2", + "cpptop_hier_array", + "cpptop_hier_array_oob", + "cpptop_hier_global", + "cpptop_hier_struct", + "cpptop_hier_struct2", + "cpptop_missing", + "cpptop_missing2", + "cpptop_missing3", + "cpptop_missing4", +} + +_STRUCT_TRACE_CASES = { + "struct", + "hier_struct", + "cpptop_hier_struct", + "cpptop_hier_struct2", +} + +_NO_INLINE_CASES = { + "hier_global_task", + "task_no_inl", + "task2_no_inl", +} + +_FILE_COMPARE_CASES = { + "cpptop_hier_array_oob", +} + +_DEFINE_ALIASES = { + "cpptop_hier_global": "hier_global", + "task_no_inl": "task", + "task2_no_inl": "task2", +} + + +def _case_name(test): + name = os.path.splitext(os.path.basename(test.py_filename))[0] + prefix = "t_trace_dumpvars" + if name == prefix: + return "base" + if not name.startswith(prefix + "_"): + test.error(f"Invalid trace dumpvars test file '{name}'") + return name[len(prefix) + 1:] + + +def _define_name(case): + define_case = _DEFINE_ALIASES.get(case, case) + token = re.sub(r"[^0-9A-Za-z]+", "_", define_case).upper() + return f"+define+TRACE_DUMPVARS_CASE_{token}" + + +def _compile_flags(case): + flags = ["--top-module", "t", _define_name(case)] + if case == "add_module": + flags = ["--binary", "--timing", "--trace-vcd", *flags] + elif case in _CPPTOP_CASES: + flags = ["--cc", "--exe", "--trace-vcd", *flags, _SHARED_CPPTOP] + else: + flags = ["--binary", "--trace-vcd", *flags] + + if case in _STRUCT_TRACE_CASES: + flags.append("--trace-structs") + if case in _NO_INLINE_CASES: + flags.append("--fno-inline") + return flags + + +def _has_golden_trace(test): + return os.path.exists(test.golden_filename) and os.path.getsize(test.golden_filename) > 0 + + +def run(test): + case = _case_name(test) + if case == "top": + test.passes() + return + + test.top_filename = _SHARED_TOP + compile_kwargs = {"verilator_flags2": _compile_flags(case)} + if case in _CPPTOP_CASES: + compile_kwargs["make_main"] = False + + if case in _COMPILE_FAIL_CASES: + test.compile(fails=True, expect_filename=test.golden_filename, **compile_kwargs) + test.passes() + return + + test.compile(**compile_kwargs) + + if case in _EXECUTE_FAIL_CASES: + test.execute(fails=True, expect_filename=test.golden_filename) + test.passes() + return + + execute_kwargs = {} + if case == "nonconst_scope": + execute_kwargs["all_run_flags"] = ['+LEVEL=0'] + + test.execute(**execute_kwargs) + + if case == "add_module": + test.vcd_identical(test.obj_dir + "/simx0.vcd", + test.t_dir + "/t_trace_dumpvars_add_module_0.out") + test.vcd_identical(test.obj_dir + "/simx1.vcd", + test.t_dir + "/t_trace_dumpvars_add_module_1.out") + elif _has_golden_trace(test): + if case in _FILE_COMPARE_CASES: + test.files_identical(test.trace_filename, test.golden_filename) + else: + test.vcd_identical(test.trace_filename, test.golden_filename) + + test.passes() \ No newline at end of file From 1cbf95ad3a2e7ab459ba5f5065781d8cf879c8d2 Mon Sep 17 00:00:00 2001 From: wsxarcher Date: Tue, 24 Mar 2026 23:01:26 +0100 Subject: [PATCH 08/13] Fix linter --- test_regress/t/t_trace_dumpvars_context.py | 1 - test_regress/t/t_trace_dumpvars_hier_struct.py | 1 - test_regress/t/t_trace_dumpvars_missing5.py | 2 +- test_regress/t/trace_dumpvars_common.py | 2 +- 4 files changed, 2 insertions(+), 4 deletions(-) diff --git a/test_regress/t/t_trace_dumpvars_context.py b/test_regress/t/t_trace_dumpvars_context.py index 558d60a06..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_context.py +++ b/test_regress/t/t_trace_dumpvars_context.py @@ -13,4 +13,3 @@ import trace_dumpvars_common test.scenarios('vlt') trace_dumpvars_common.run(test) - diff --git a/test_regress/t/t_trace_dumpvars_hier_struct.py b/test_regress/t/t_trace_dumpvars_hier_struct.py index 558d60a06..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_hier_struct.py +++ b/test_regress/t/t_trace_dumpvars_hier_struct.py @@ -13,4 +13,3 @@ import trace_dumpvars_common test.scenarios('vlt') trace_dumpvars_common.run(test) - diff --git a/test_regress/t/t_trace_dumpvars_missing5.py b/test_regress/t/t_trace_dumpvars_missing5.py index 5d72fbb34..96746adc4 100644 --- a/test_regress/t/t_trace_dumpvars_missing5.py +++ b/test_regress/t/t_trace_dumpvars_missing5.py @@ -12,4 +12,4 @@ import trace_dumpvars_common test.scenarios('vlt') -trace_dumpvars_common.run(test) \ No newline at end of file +trace_dumpvars_common.run(test) diff --git a/test_regress/t/trace_dumpvars_common.py b/test_regress/t/trace_dumpvars_common.py index 164b81538..6bb3782ad 100644 --- a/test_regress/t/trace_dumpvars_common.py +++ b/test_regress/t/trace_dumpvars_common.py @@ -145,4 +145,4 @@ def run(test): else: test.vcd_identical(test.trace_filename, test.golden_filename) - test.passes() \ No newline at end of file + test.passes() From 947683ba2a1f3ee1f40fea6cd193d38764112b08 Mon Sep 17 00:00:00 2001 From: wsxarcher Date: Tue, 24 Mar 2026 23:22:24 +0100 Subject: [PATCH 09/13] Add fst/saif test --- .../t/t_trace_dumpvars_level_scope_fst.out | 31 +++++ .../t/t_trace_dumpvars_level_scope_fst.py | 15 +++ .../t/t_trace_dumpvars_level_scope_saif.out | 119 ++++++++++++++++++ .../t/t_trace_dumpvars_level_scope_saif.py | 15 +++ test_regress/t/trace_dumpvars_common.py | 45 +++++-- 5 files changed, 212 insertions(+), 13 deletions(-) create mode 100644 test_regress/t/t_trace_dumpvars_level_scope_fst.out create mode 100644 test_regress/t/t_trace_dumpvars_level_scope_fst.py create mode 100644 test_regress/t/t_trace_dumpvars_level_scope_saif.out create mode 100644 test_regress/t/t_trace_dumpvars_level_scope_saif.py diff --git a/test_regress/t/t_trace_dumpvars_level_scope_fst.out b/test_regress/t/t_trace_dumpvars_level_scope_fst.out new file mode 100644 index 000000000..f74d6bd3e --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_level_scope_fst.out @@ -0,0 +1,31 @@ +$date +Tue Mar 24 23:18:44 2026 + +$end +$version +Generated by VerilatedFst +$end +$timescale +1ps +$end + $scope module $rootio $end + $upscope $end + $scope module t $end + $scope module sub_a $end + $var parameter 32 ! ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var int 32 # value [31:0] $end + $scope module deep_i $end + $upscope $end + $upscope $end + $scope module sub_b $end + $scope module deep_i $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end +#0 +$dumpvars +b00000000000000000000000000001010 # +b00000000000000000000000000000000 " +b00000000000000000000000000001010 ! diff --git a/test_regress/t/t_trace_dumpvars_level_scope_fst.py b/test_regress/t/t_trace_dumpvars_level_scope_fst.py new file mode 100644 index 000000000..96746adc4 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_level_scope_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_dumpvars_common + +test.scenarios('vlt') + +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_level_scope_saif.out b/test_regress/t/t_trace_dumpvars_level_scope_saif.out new file mode 100644 index 000000000..c7d8c321b --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_level_scope_saif.out @@ -0,0 +1,119 @@ +// Generated by verilated_saif +(SAIFILE +(SAIFVERSION "2.0") +(DIRECTION "backward") +(PROGRAM_NAME "Verilator") +(DIVIDER / ) +(TIMESCALE 1ps) +(DURATION 0) + (INSTANCE $rootio + ) + (INSTANCE t + (INSTANCE sub_a + (NET + (ADD\[0\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[1\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) + (ADD\[2\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[3\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) + (ADD\[4\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[5\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[6\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[7\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[8\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[9\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[10\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[11\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[12\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[13\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[14\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[15\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[16\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[17\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[18\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[19\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[20\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[21\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[22\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[23\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[24\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[25\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[26\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[27\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[28\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[29\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[30\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[31\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[0\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[1\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[2\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[3\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[4\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[5\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[6\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[7\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[8\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[9\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[10\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[11\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[12\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[13\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[14\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[15\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[16\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[17\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[18\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[19\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[20\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[21\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[22\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[23\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[24\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[25\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[26\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[27\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[28\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[29\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[30\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[31\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[0\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[1\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) + (value\[2\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[3\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) + (value\[4\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[5\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[6\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[7\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[8\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[9\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[10\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[11\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[12\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[13\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[14\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[15\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[16\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[17\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[18\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[19\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[20\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[21\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[22\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[23\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[24\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[25\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[26\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[27\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[28\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[29\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[30\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[31\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + (INSTANCE deep_i + ) + ) + (INSTANCE sub_b + (INSTANCE deep_i + ) + ) + ) +) diff --git a/test_regress/t/t_trace_dumpvars_level_scope_saif.py b/test_regress/t/t_trace_dumpvars_level_scope_saif.py new file mode 100644 index 000000000..96746adc4 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_level_scope_saif.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_dumpvars_common + +test.scenarios('vlt') + +trace_dumpvars_common.run(test) diff --git a/test_regress/t/trace_dumpvars_common.py b/test_regress/t/trace_dumpvars_common.py index 6bb3782ad..fe4bf2587 100644 --- a/test_regress/t/trace_dumpvars_common.py +++ b/test_regress/t/trace_dumpvars_common.py @@ -68,6 +68,16 @@ _DEFINE_ALIASES = { "task2_no_inl": "task2", } +_ALT_TRACE_FORMATS = {"fst", "saif"} + + +def _split_format(case): + """Split case into (base_case, trace_format).""" + for fmt in _ALT_TRACE_FORMATS: + if case.endswith("_" + fmt): + return case[:-(len(fmt) + 1)], fmt + return case, "vcd" + def _case_name(test): name = os.path.splitext(os.path.basename(test.py_filename))[0] @@ -85,14 +95,15 @@ def _define_name(case): return f"+define+TRACE_DUMPVARS_CASE_{token}" -def _compile_flags(case): +def _compile_flags(case, fmt="vcd"): + trace_flag = f"--trace-{fmt}" flags = ["--top-module", "t", _define_name(case)] if case == "add_module": - flags = ["--binary", "--timing", "--trace-vcd", *flags] + flags = ["--binary", "--timing", trace_flag, *flags] elif case in _CPPTOP_CASES: - flags = ["--cc", "--exe", "--trace-vcd", *flags, _SHARED_CPPTOP] + flags = ["--cc", "--exe", trace_flag, *flags, _SHARED_CPPTOP] else: - flags = ["--binary", "--trace-vcd", *flags] + flags = ["--binary", trace_flag, *flags] if case in _STRUCT_TRACE_CASES: flags.append("--trace-structs") @@ -107,42 +118,50 @@ def _has_golden_trace(test): def run(test): case = _case_name(test) - if case == "top": + base_case, fmt = _split_format(case) + + if base_case == "top": test.passes() return test.top_filename = _SHARED_TOP - compile_kwargs = {"verilator_flags2": _compile_flags(case)} - if case in _CPPTOP_CASES: + compile_kwargs = {"verilator_flags2": _compile_flags(base_case, fmt)} + if base_case in _CPPTOP_CASES: compile_kwargs["make_main"] = False - if case in _COMPILE_FAIL_CASES: + if base_case in _COMPILE_FAIL_CASES: test.compile(fails=True, expect_filename=test.golden_filename, **compile_kwargs) test.passes() return test.compile(**compile_kwargs) - if case in _EXECUTE_FAIL_CASES: + if base_case in _EXECUTE_FAIL_CASES: test.execute(fails=True, expect_filename=test.golden_filename) test.passes() return execute_kwargs = {} - if case == "nonconst_scope": + if base_case == "nonconst_scope": execute_kwargs["all_run_flags"] = ['+LEVEL=0'] test.execute(**execute_kwargs) - if case == "add_module": + # For format variants, fall back to the base case's golden file + if fmt != "vcd" and not _has_golden_trace(test): + base_golden = os.path.join(test.t_dir, f"t_trace_dumpvars_{base_case}.out") + if os.path.exists(base_golden) and os.path.getsize(base_golden) > 0: + test.golden_filename = base_golden + + if base_case == "add_module": test.vcd_identical(test.obj_dir + "/simx0.vcd", test.t_dir + "/t_trace_dumpvars_add_module_0.out") test.vcd_identical(test.obj_dir + "/simx1.vcd", test.t_dir + "/t_trace_dumpvars_add_module_1.out") elif _has_golden_trace(test): - if case in _FILE_COMPARE_CASES: + if base_case in _FILE_COMPARE_CASES: test.files_identical(test.trace_filename, test.golden_filename) else: - test.vcd_identical(test.trace_filename, test.golden_filename) + test.trace_identical(test.trace_filename, test.golden_filename) test.passes() From 9f42078adaf7b81149ea1253760d551bd784c165 Mon Sep 17 00:00:00 2001 From: wsxarcher Date: Wed, 25 Mar 2026 00:22:56 +0100 Subject: [PATCH 10/13] Fix comments --- include/verilated_trace.h | 1 - src/CMakeLists.txt | 2 +- src/{V3Dumpvars.h => V3DumpVars.h} | 8 ++++---- src/V3EmitCFunc.h | 2 +- src/V3LinkDot.h | 2 +- 5 files changed, 7 insertions(+), 8 deletions(-) rename src/{V3Dumpvars.h => V3DumpVars.h} (88%) diff --git a/include/verilated_trace.h b/include/verilated_trace.h index 9b6756695..e4a2f687c 100644 --- a/include/verilated_trace.h +++ b/include/verilated_trace.h @@ -380,7 +380,6 @@ protected: || type == VerilatedTracePrefixType::SCOPE_INTERFACE || type == VerilatedTracePrefixType::ROOTIO_WRAPPER; } - static char separator(VerilatedTracePrefixType type) { return (type == VerilatedTracePrefixType::ARRAY_PACKED || type == VerilatedTracePrefixType::ARRAY_UNPACKED) diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index d8416bd1c..c2837afa5 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -86,7 +86,7 @@ set(HEADERS V3DfgPeepholePatterns.h V3DfgVertices.h V3DiagSarif.h - V3Dumpvars.h + V3DumpVars.h V3DupFinder.h V3EmitC.h V3EmitCBase.h diff --git a/src/V3Dumpvars.h b/src/V3DumpVars.h similarity index 88% rename from src/V3Dumpvars.h rename to src/V3DumpVars.h index b30f86d77..a5d2c706a 100644 --- a/src/V3Dumpvars.h +++ b/src/V3DumpVars.h @@ -23,11 +23,11 @@ // Tagged $dumpvars target string. During compile-time resolution in V3LinkDot // each target is tagged with a prefix that tells EmitC how to emit the // corresponding runtime code. -struct DumpvarsTag final { +struct VDumpVarsTag final { const char* const prefix; const size_t prefixLen; template - constexpr DumpvarsTag(const char (&s)[N]) + constexpr VDumpVarsTag(const char (&s)[N]) : prefix{s} , prefixLen{N - 1} {} bool matches(const string& target) const { return target.compare(0, prefixLen, prefix) == 0; } @@ -38,8 +38,8 @@ struct DumpvarsTag final { }; // Fully resolved to a compile-time hierarchy path -constexpr DumpvarsTag kDumpvarsResolved{"@dumpvars:"}; +constexpr VDumpVarsTag kDumpvarsResolved{"@dumpvars:"}; // First component must match the C++ wrapper root name at runtime -constexpr DumpvarsTag kDumpvarsRuntimeRoot{"@dumpvars_root:"}; +constexpr VDumpVarsTag kDumpvarsRuntimeRoot{"@dumpvars_root:"}; #endif // Guard diff --git a/src/V3EmitCFunc.h b/src/V3EmitCFunc.h index f035a867f..96c6bb89d 100644 --- a/src/V3EmitCFunc.h +++ b/src/V3EmitCFunc.h @@ -21,7 +21,7 @@ #include "verilatedos.h" #include "V3EmitCConstInit.h" -#include "V3Dumpvars.h" +#include "V3DumpVars.h" #include "V3Global.h" #include "V3MemberMap.h" diff --git a/src/V3LinkDot.h b/src/V3LinkDot.h index e873dcef3..78cdd64d0 100644 --- a/src/V3LinkDot.h +++ b/src/V3LinkDot.h @@ -21,7 +21,7 @@ #include "verilatedos.h" #include "V3Ast.h" -#include "V3Dumpvars.h" +#include "V3DumpVars.h" #include "V3Error.h" //============================================================================ From ec8cf87d7697f776aefb82eb06f51ed69d2a030b Mon Sep 17 00:00:00 2001 From: wsxarcher Date: Wed, 25 Mar 2026 00:30:41 +0100 Subject: [PATCH 11/13] Entries alias --- include/verilated.cpp | 2 +- include/verilated.h | 13 +++++++------ include/verilated_fst_c.h | 2 +- include/verilated_saif_c.h | 2 +- include/verilated_trace.h | 8 ++++---- include/verilated_vcd_c.h | 2 +- 6 files changed, 15 insertions(+), 14 deletions(-) diff --git a/include/verilated.cpp b/include/verilated.cpp index dbd5cdf24..e2c81cd7e 100644 --- a/include/verilated.cpp +++ b/include/verilated.cpp @@ -2932,7 +2932,7 @@ void VerilatedContext::dumpvarsAdd(int level, if (level == 0 && hier.empty()) m_dumpvars.clear(); m_dumpvars.emplace_back(level, hier); } -std::vector +VerilatedTraceDumpVarsEntries VerilatedContext::dumpvars() const VL_MT_SAFE_EXCLUDES(m_timeDumpMutex) { const VerilatedLockGuard lock{m_timeDumpMutex}; return m_dumpvars; diff --git a/include/verilated.h b/include/verilated.h index c605a98f8..49ad009f6 100644 --- a/include/verilated.h +++ b/include/verilated.h @@ -111,16 +111,17 @@ class VerilatedVcdC; class VerilatedVcdSc; // Internal: One $dumpvars call. -struct VerilatedTraceDumpvarsEntry final { +struct VerilatedTraceDumpVarsEntry final { /// Maximum hierarchy depth to dump modules. - int m_level; + const int m_level; /// Hierarchy root to dump. - std::string m_hier; + const std::string m_hier; - VerilatedTraceDumpvarsEntry(int level, const std::string& hier) + VerilatedTraceDumpVarsEntry(int level, const std::string& hier) : m_level{level} , m_hier{hier} {} }; +using VerilatedTraceDumpVarsEntries = std::vector; //========================================================================= // Basic types @@ -416,7 +417,7 @@ protected: mutable VerilatedMutex m_timeDumpMutex; // Protect misc slow strings std::string m_timeFormatSuffix VL_GUARDED_BY(m_timeDumpMutex); // $timeformat printf format std::string m_dumpfile VL_GUARDED_BY(m_timeDumpMutex); // $dumpfile setting - std::vector + VerilatedTraceDumpVarsEntries m_dumpvars VL_GUARDED_BY(m_timeDumpMutex); // $dumpvars settings struct NonSerialized final { // Non-serialized information @@ -672,7 +673,7 @@ public: // Internal: $dumpvars void dumpvarsAdd(int level, const std::string& hier) VL_MT_SAFE_EXCLUDES(m_timeDumpMutex); - std::vector dumpvars() const + VerilatedTraceDumpVarsEntries dumpvars() const VL_MT_SAFE_EXCLUDES(m_timeDumpMutex); // Internal: --prof-exec related settings diff --git a/include/verilated_fst_c.h b/include/verilated_fst_c.h index 5de5f9a85..bb5871662 100644 --- a/include/verilated_fst_c.h +++ b/include/verilated_fst_c.h @@ -300,7 +300,7 @@ public: void dumpvars(int level, const std::string& hier) VL_MT_SAFE { m_sptrace.dumpvars(level, hier); } - void dumpvars(const std::vector& entries) VL_MT_SAFE { + void dumpvars(const VerilatedTraceDumpVarsEntries& entries) VL_MT_SAFE { m_sptrace.dumpvars(entries); } diff --git a/include/verilated_saif_c.h b/include/verilated_saif_c.h index adbdd6f00..2cdb2a6ef 100644 --- a/include/verilated_saif_c.h +++ b/include/verilated_saif_c.h @@ -318,7 +318,7 @@ public: void dumpvars(int level, const std::string& hier) VL_MT_SAFE { m_sptrace.dumpvars(level, hier); } - void dumpvars(const std::vector& entries) VL_MT_SAFE { + void dumpvars(const VerilatedTraceDumpVarsEntries& entries) VL_MT_SAFE { m_sptrace.dumpvars(entries); } diff --git a/include/verilated_trace.h b/include/verilated_trace.h index e4a2f687c..1f7680cb3 100644 --- a/include/verilated_trace.h +++ b/include/verilated_trace.h @@ -313,7 +313,7 @@ private: uint32_t m_maxBits = 0; // Number of bits in the widest signal void* m_initUserp = nullptr; // The callback userp of the instance currently being initialized // TODO: Should keep this as a Trie, that is how it's accessed all the time. - std::vector m_dumpvars; // dumpvar() entries + VerilatedTraceDumpVarsEntries m_dumpvars; // dumpvar() entries double m_timeRes = 1e-9; // Time resolution (ns/ms etc) double m_timeUnit = 1e-0; // Time units (ns/ms etc) uint64_t m_timeLastDump = 0; // Last time we did a dump @@ -417,7 +417,7 @@ protected: return levels; } - bool matches(const VerilatedTraceDumpvarsEntry& entry) const { + bool matches(const VerilatedTraceDumpVarsEntry& entry) const { if (!matchesPrefix(entry.m_hier)) return false; return entry.m_level <= 0 || scopeLevelsBelow(entry.m_hier.size()) < entry.m_level; } @@ -508,8 +508,8 @@ public: // Set variables to dump, using $dumpvars format // If level = 0, dump everything and hier is then ignored void dumpvars(int level, const std::string& hier) VL_MT_SAFE; - void dumpvars(const std::vector& entries) VL_MT_SAFE { - for (const VerilatedTraceDumpvarsEntry& entry : entries) { + void dumpvars(const VerilatedTraceDumpVarsEntries& entries) VL_MT_SAFE { + for (const VerilatedTraceDumpVarsEntry& entry : entries) { dumpvars(entry.m_level, entry.m_hier); } } diff --git a/include/verilated_vcd_c.h b/include/verilated_vcd_c.h index b328a298d..6ff35c85a 100644 --- a/include/verilated_vcd_c.h +++ b/include/verilated_vcd_c.h @@ -351,7 +351,7 @@ public: void dumpvars(int level, const std::string& hier) VL_MT_SAFE { m_sptrace.dumpvars(level, hier); } - void dumpvars(const std::vector& entries) VL_MT_SAFE { + void dumpvars(const VerilatedTraceDumpVarsEntries& entries) VL_MT_SAFE { m_sptrace.dumpvars(entries); } From a28732ccf96487d1401daae0f9ab4033322d0f44 Mon Sep 17 00:00:00 2001 From: wsxarcher Date: Wed, 25 Mar 2026 01:41:50 +0100 Subject: [PATCH 12/13] Simplify V3LinkDot --- src/V3LinkDot.cpp | 220 +++++++++++++++------------------------------- 1 file changed, 70 insertions(+), 150 deletions(-) diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index 7ccfbd6ce..e94bcc3f5 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -92,7 +92,8 @@ static string dumpvarsTargetText(const AstNode* nodep) { } if (const AstCellArrayRef* const refp = VN_CAST(nodep, CellArrayRef)) { string out = refp->name(); - for (const AstNodeExpr* selp = refp->selp(); selp; selp = VN_CAST(selp->nextp(), NodeExpr)) { + for (const AstNodeExpr* selp = refp->selp(); selp; + selp = VN_CAST(selp->nextp(), NodeExpr)) { out += "[" + dumpvarsTargetText(selp) + "]"; } return out; @@ -3173,95 +3174,74 @@ class LinkDotResolveVisitor final : public VNVisitor { } } m_ds; // State to preserve across recursions - static string dumpvarsSymPathPiece(const AstNode* nodep) { - if (!nodep) return ""; - if (const AstNodeModule* const modp = VN_CAST(nodep, NodeModule)) return modp->origName(); - if (const AstCell* const cellp = VN_CAST(nodep, Cell)) return cellp->origName(); - if (const AstCellInline* const inlinep = VN_CAST(nodep, CellInline)) return inlinep->name(); - if (const AstVarScope* const vscp = VN_CAST(nodep, VarScope)) return vscp->varp()->name(); - return nodep->name(); - } - static bool dumpvarsMatchesLocalModule(const VSymEnt* symp, const string& ident) { if (!symp) return false; if (const AstCell* const cellp = VN_CAST(symp->nodep(), Cell)) { return cellp->modp() && cellp->modp()->origName() == ident; } - if (const AstCellInline* const inlinep = VN_CAST(symp->nodep(), CellInline)) { + if (const AstCellInline* const inlinep = VN_CAST(symp->nodep(), CellInline)) return inlinep->origModName() == ident; - } - if (const AstNodeModule* const modp = VN_CAST(symp->nodep(), NodeModule)) { + if (const AstNodeModule* const modp = VN_CAST(symp->nodep(), NodeModule)) return modp->origName() == ident; - } return false; } static string dumpvarsResolvedPath(VSymEnt* symp) { - std::vector pieces; - for (VSymEnt* walkp = symp; walkp && walkp->parentp(); walkp = walkp->parentp()) { - const string piece = dumpvarsSymPathPiece(walkp->nodep()); - if (!piece.empty()) pieces.push_back(piece); - } - std::reverse(pieces.begin(), pieces.end()); string path; - for (const string& piece : pieces) { - if (!path.empty()) path += '.'; - path += piece; + for (VSymEnt* walkp = symp; walkp && walkp->parentp(); walkp = walkp->parentp()) { + const AstNode* const np = walkp->nodep(); + const string piece = !np ? "" + : VN_IS(np, NodeModule) ? VN_AS(np, NodeModule)->origName() + : VN_IS(np, Cell) ? VN_AS(np, Cell)->origName() + : VN_IS(np, VarScope) ? VN_AS(np, VarScope)->varp()->name() + : np->name(); + if (piece.empty()) continue; + path = path.empty() ? piece : piece + "." + path; } return path; } - static bool dumpvarsHasBareTarget(AstNode* targetsp, const string& name) { - for (AstNode* tp = targetsp; tp; tp = tp->nextp()) { - if (dumpvarsTargetText(tp) == name) return true; - } - return false; - } - static string dumpvarsBracketToInternal(const string& ident) { const string::size_type lbr = ident.find('['); if (lbr == string::npos) return ident; const string::size_type rbr = ident.find(']', lbr); if (rbr == string::npos) return ident; - return ident.substr(0, lbr) + "__BRA__" + ident.substr(lbr + 1, rbr - lbr - 1) - + "__KET__" + dumpvarsBracketToInternal(ident.substr(rbr + 1)); + return ident.substr(0, lbr) + "__BRA__" + ident.substr(lbr + 1, rbr - lbr - 1) + "__KET__" + + dumpvarsBracketToInternal(ident.substr(rbr + 1)); } VSymEnt* findDumpvarsLocal(FileLine* refLocationp, const string& dotname, string& baddot, VSymEnt*& okSymp) { if (!m_curSymp) return nullptr; - string leftname = dotname; - string::size_type pos; - string ident; - if ((pos = leftname.find('.')) != string::npos) { - ident = leftname.substr(0, pos); - leftname = leftname.substr(pos + 1); - } else { - ident = leftname; - leftname = ""; - } - + const string::size_type dotPos = dotname.find('.'); + const string ident = dotPos == string::npos ? dotname : dotname.substr(0, dotPos); + const string leftname = dotPos == string::npos ? "" : dotname.substr(dotPos + 1); baddot = ident; okSymp = m_curSymp; - string altIdent; - if (m_statep->forPrearray()) { - if ((pos = ident.rfind("__BRA__")) != string::npos) altIdent = ident.substr(0, pos); - if (altIdent.empty() && ident.find('[') != string::npos) - altIdent = ident.substr(0, ident.find('[')); - } - VSymEnt* symp = nullptr; - if (dumpvarsMatchesLocalModule(m_curSymp, ident)) { - symp = m_curSymp; - } else { - symp = m_curSymp->findIdFallback(ident); - if (!symp && ident.find('[') != string::npos) - symp = m_curSymp->findIdFallback(dumpvarsBracketToInternal(ident)); - if (!symp && !altIdent.empty()) symp = m_curSymp->findIdFallback(altIdent); - } + const auto findLocal = [&](const string& name) -> VSymEnt* { + if (dumpvarsMatchesLocalModule(m_curSymp, name)) return m_curSymp; + if (VSymEnt* const symp = m_curSymp->findIdFallback(name)) return symp; + const string internal = dumpvarsBracketToInternal(name); + if (internal != name) { + if (VSymEnt* const symp = m_curSymp->findIdFallback(internal)) return symp; + } + if (!m_statep->forPrearray()) return nullptr; + auto pos = name.rfind("__BRA__"); + if (pos == string::npos) pos = name.find('['); + return (pos != string::npos && pos > 0) + ? m_curSymp->findIdFallback(name.substr(0, pos)) + : nullptr; + }; + + VSymEnt* const symp = findLocal(ident); if (!symp) return nullptr; - if (leftname.empty()) { - okSymp = symp; + okSymp = symp; + if (leftname.empty()) return symp; + // Non-scope nodes (e.g. struct variables) don't have sub-symbols, + // accept the path without resolving further. + if (!(VN_IS(symp->nodep(), Cell) || VN_IS(symp->nodep(), CellInline) + || VN_IS(symp->nodep(), NodeModule))) { return symp; } return m_statep->findDotted(refLocationp, symp, leftname, baddot, okSymp, false); @@ -3273,112 +3253,52 @@ class LinkDotResolveVisitor final : public VNVisitor { if (target.empty() || !m_curSymp) return target; string baddot; - VSymEnt* matchSymp = nullptr; + VSymEnt* okSymp = nullptr; + const auto fail = [&]() { + fl->v3error("$dumpvars target not found: " << target); + return target; + }; + const auto findFromRoot = [&](const string& path) { + return m_statep->findDotted(fl, m_statep->rootEntp(), path, baddot, okSymp, true); + }; - // Step 1: Try local scope lookup. - if (findDumpvarsLocal(fl, target, baddot, matchSymp)) return target; + if (findDumpvarsLocal(fl, target, baddot, okSymp)) return target; - // Step 2: Try global lookup from $root. - if (VSymEnt* const rootSymp = m_statep->findDotted( - fl, m_statep->rootEntp(), target, baddot, matchSymp, true)) { + if (VSymEnt* const rootSymp = findFromRoot(target)) { const string resolved = dumpvarsResolvedPath(rootSymp); if (!resolved.empty()) return kDumpvarsResolved.make(resolved); } - // Step 3: Defer single component to root lookup if available. const string::size_type dotPos = target.find('.'); - const string firstComp = (dotPos != string::npos) ? target.substr(0, dotPos) : target; + if (dotPos == string::npos) + return v3Global.opt.main() ? fail() : kDumpvarsRuntimeRoot.make(target); - if (dotPos == string::npos) { - if (v3Global.opt.main()) { - fl->v3error("$dumpvars target not found: " << target); - return target; - } - return kDumpvarsRuntimeRoot.make(target); - } - - // Step 4: Multi-component "X.y.z" where X might be the runtime root. + const string firstComp = target.substr(0, dotPos); const string remaining = target.substr(dotPos + 1); - - // With --main, if the first component matches the local module, - // walk the remaining path through cell scopes to validate it. - if (!dumpvarsHasBareTarget(targetsp, firstComp) && v3Global.opt.main() - && dumpvarsMatchesLocalModule(m_curSymp, firstComp)) { - string walkPath = remaining; - VSymEnt* walkSymp = m_curSymp; - bool errorOut = false; - while (!walkPath.empty() && walkSymp) { - // Extract first identifier (strip dots, brackets, __BRA__) - string ident = walkPath; - { - string::size_type cutPos = string::npos; - const string::size_type dp = ident.find('.'); - if (dp != string::npos && dp < cutPos) cutPos = dp; - const string::size_type bp = ident.find('['); - if (bp != string::npos && (cutPos == string::npos || bp < cutPos)) - cutPos = bp; - const string::size_type brp = ident.find("__BRA__"); - if (brp != string::npos && (cutPos == string::npos || brp < cutPos)) - cutPos = brp; - if (cutPos != string::npos) ident = ident.substr(0, cutPos); - } - VSymEnt* const childSymp = walkSymp->findIdFallback(ident); - if (!childSymp) { - errorOut = true; - break; - } - walkPath = walkPath.substr(ident.size()); - if (!walkPath.empty() && walkPath[0] == '.') walkPath = walkPath.substr(1); - // Skip array subscript if present - if (!walkPath.empty() && walkPath[0] == '[') { - const string::size_type rb = walkPath.find(']'); - if (rb != string::npos) walkPath = walkPath.substr(rb + 1); - if (!walkPath.empty() && walkPath[0] == '.') walkPath = walkPath.substr(1); - } - if (walkPath.substr(0, 7) == "__BRA__") { - const string::size_type ke = walkPath.find("__KET__"); - if (ke != string::npos) walkPath = walkPath.substr(ke + 7); - if (!walkPath.empty() && walkPath[0] == '.') walkPath = walkPath.substr(1); - } - if (!VN_IS(childSymp->nodep(), Cell) - && !VN_IS(childSymp->nodep(), CellInline) - && !VN_IS(childSymp->nodep(), NodeModule)) { - return target; - } - walkSymp = childSymp; - } - if (errorOut) { - fl->v3error("$dumpvars target not found: " << target); - return target; + bool hasBareFirstComp = false; + for (AstNode* tp = targetsp; tp; tp = tp->nextp()) { + if (dumpvarsTargetText(tp) == firstComp) { + hasBareFirstComp = true; + break; } + } + + if (hasBareFirstComp) { + return findFromRoot(remaining) ? kDumpvarsRuntimeRoot.make(target) : fail(); + } + + if (v3Global.opt.main() && dumpvarsMatchesLocalModule(m_curSymp, firstComp)) { + if (!findDumpvarsLocal(fl, remaining, baddot, okSymp)) fail(); return target; } - if (dumpvarsHasBareTarget(targetsp, firstComp)) { - string runtimeBaddot; - VSymEnt* runtimeMatchSymp = nullptr; - if (m_statep->findDotted(fl, m_statep->rootEntp(), remaining, runtimeBaddot, - runtimeMatchSymp, true)) { - return kDumpvarsRuntimeRoot.make(target); - } - fl->v3error("$dumpvars target not found: " << target); + if (findDumpvarsLocal(fl, firstComp, baddot, okSymp) + && !(VN_IS(okSymp->nodep(), Cell) || VN_IS(okSymp->nodep(), CellInline) + || VN_IS(okSymp->nodep(), NodeModule))) { return target; } - string localBaddot; - VSymEnt* localSymp = nullptr; - if (findDumpvarsLocal(fl, firstComp, localBaddot, localSymp) - && !VN_IS(localSymp->nodep(), Cell) && !VN_IS(localSymp->nodep(), CellInline) - && !VN_IS(localSymp->nodep(), NodeModule)) { - return target; - } - - if (v3Global.opt.main()) { - fl->v3error("$dumpvars target not found: " << target); - return target; - } - // First component may be a runtime root name from C++; defer validation to runtime. - return kDumpvarsRuntimeRoot.make(target); + return v3Global.opt.main() ? fail() : kDumpvarsRuntimeRoot.make(target); } // METHODS - Variables From 2d4073999afa5ba962e4174fbece628565844ec7 Mon Sep 17 00:00:00 2001 From: wsxarcher Date: Wed, 25 Mar 2026 02:11:00 +0100 Subject: [PATCH 13/13] Fix ub --- include/verilated_trace_imp.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/verilated_trace_imp.h b/include/verilated_trace_imp.h index 5f4bef453..20f7332df 100644 --- a/include/verilated_trace_imp.h +++ b/include/verilated_trace_imp.h @@ -342,7 +342,8 @@ void VerilatedTrace::traceInit() VL_MT_UNSAFE { // guaranteed to be fast m_sigs_enabledp = new uint32_t[1 + VL_WORDS_I(nextCode())]{0}; m_sigs_enabledVec.reserve(nextCode()); - for (size_t code = 0; code < nextCode(); ++code) { + size_t iter = nextCode() > m_sigs_enabledVec.size() ? m_sigs_enabledVec.size() : nextCode(); + for (size_t code = 0; code < iter; ++code) { if (m_sigs_enabledVec[code]) { m_sigs_enabledp[VL_BITWORD_I(code)] |= 1U << VL_BITBIT_I(code); }