diff --git a/include/verilated.cpp b/include/verilated.cpp
index 922385126..8c464622a 100644
--- a/include/verilated.cpp
+++ b/include/verilated.cpp
@@ -2941,6 +2941,17 @@ std::string VerilatedContext::dumpfileCheck() const VL_MT_SAFE_EXCLUDES(m_timeDu
     }
     return out;
 }
+void VerilatedContext::dumpvarsAdd(int level,
+                                   const std::string& hier) VL_MT_SAFE_EXCLUDES(m_timeDumpMutex) {
+    const VerilatedLockGuard lock{m_timeDumpMutex};
+    if (level == 0 && hier.empty()) m_dumpvars.clear();
+    m_dumpvars.emplace_back(level, hier);
+}
+VerilatedTraceDumpVarsEntries
+VerilatedContext::dumpvars() const VL_MT_SAFE_EXCLUDES(m_timeDumpMutex) {
+    const VerilatedLockGuard lock{m_timeDumpMutex};
+    return m_dumpvars;
+}
 void VerilatedContext::errorCount(int val) VL_MT_SAFE {
     const VerilatedLockGuard lock{m_mutex};
     m_s.m_errorCount = val;
diff --git a/include/verilated.h b/include/verilated.h
index b7f70bda7..2862d9106 100644
--- a/include/verilated.h
+++ b/include/verilated.h
@@ -110,6 +110,19 @@ class VerilatedVcd;
 class VerilatedVcdC;
 class VerilatedVcdSc;
 
+// Internal: One $dumpvars call.
+struct VerilatedTraceDumpVarsEntry final {
+    /// Maximum hierarchy depth to dump modules.
+    const int m_level;
+    /// Hierarchy root to dump.
+    const std::string m_hier;
+
+    VerilatedTraceDumpVarsEntry(int level, const std::string& hier)
+        : m_level{level}
+        , m_hier{hier} {}
+};
+using VerilatedTraceDumpVarsEntries = std::vector<VerilatedTraceDumpVarsEntry>;
+
 //=========================================================================
 // Basic types
 
@@ -404,6 +417,8 @@ protected:
     mutable VerilatedMutex m_timeDumpMutex;  // Protect misc slow strings
     std::string m_timeFormatSuffix VL_GUARDED_BY(m_timeDumpMutex);  // $timeformat printf format
     std::string m_dumpfile VL_GUARDED_BY(m_timeDumpMutex);  // $dumpfile setting
+    VerilatedTraceDumpVarsEntries
+        m_dumpvars VL_GUARDED_BY(m_timeDumpMutex);  // $dumpvars settings
 
     struct NonSerialized final {  // Non-serialized information
         // These are reloaded from on command-line settings, so do not need to persist
@@ -656,6 +671,11 @@ public:
     void dumpfile(const std::string& flag) VL_MT_SAFE_EXCLUDES(m_timeDumpMutex);
     std::string dumpfileCheck() const VL_MT_SAFE_EXCLUDES(m_timeDumpMutex);
 
+    // Internal: $dumpvars
+    void dumpvarsAdd(int level, const std::string& hier) VL_MT_SAFE_EXCLUDES(m_timeDumpMutex);
+    VerilatedTraceDumpVarsEntries dumpvars() const
+        VL_MT_SAFE_EXCLUDES(m_timeDumpMutex);
+
     // Internal: --prof-exec related settings
     uint64_t profExecStart() const VL_MT_SAFE { return m_ns.m_profExecStart; }
     void profExecStart(uint64_t flag) VL_MT_SAFE;
diff --git a/include/verilated_fst_c.cpp b/include/verilated_fst_c.cpp
index 3096765a5..965365ac2 100644
--- a/include/verilated_fst_c.cpp
+++ b/include/verilated_fst_c.cpp
@@ -221,8 +221,9 @@ void VerilatedFst::declare(uint32_t code, const char* name, int dtypenum,
     const int bits = ((msb > lsb) ? (msb - lsb) : (lsb - msb)) + 1;
 
     const std::string hierarchicalName = m_prefixStack.back().first + name;
+    const auto dumpvarsPath = Super::dumpvarsPath(m_prefixStack, name);
 
-    const bool enabled = Super::declCode(code, hierarchicalName, bits);
+    const bool enabled = Super::declCode(code, dumpvarsPath, bits);
     if (!enabled) return;
 
     assert(hierarchicalName.rfind(' ') != std::string::npos);
diff --git a/include/verilated_fst_c.h b/include/verilated_fst_c.h
index beab35565..bb5871662 100644
--- a/include/verilated_fst_c.h
+++ b/include/verilated_fst_c.h
@@ -300,6 +300,9 @@ public:
     void dumpvars(int level, const std::string& hier) VL_MT_SAFE {
         m_sptrace.dumpvars(level, hier);
     }
+    void dumpvars(const VerilatedTraceDumpVarsEntries& entries) VL_MT_SAFE {
+        m_sptrace.dumpvars(entries);
+    }
 
     // Internal class access
     VerilatedFst* spTrace() { return &m_sptrace; }
diff --git a/include/verilated_saif_c.cpp b/include/verilated_saif_c.cpp
index d6632dca7..3fa6b9d02 100644
--- a/include/verilated_saif_c.cpp
+++ b/include/verilated_saif_c.cpp
@@ -539,8 +539,9 @@ void VerilatedSaif::declare(const uint32_t code, uint32_t fidx, const char* name
     const int bits = ((msb > lsb) ? (msb - lsb) : (lsb - msb)) + 1;
 
     const std::string hierarchicalName = m_prefixStack.back().first + name;
+    const auto dumpvarsPath = Super::dumpvarsPath(m_prefixStack, name);
 
-    if (!Super::declCode(code, hierarchicalName, bits)) return;
+    if (!Super::declCode(code, dumpvarsPath, bits)) return;
 
     std::string variableName = lastWord(hierarchicalName);
     m_currentScope->addActivityVar(code, variableName);
diff --git a/include/verilated_saif_c.h b/include/verilated_saif_c.h
index 11637d925..326fca155 100644
--- a/include/verilated_saif_c.h
+++ b/include/verilated_saif_c.h
@@ -318,6 +318,9 @@ public:
     void dumpvars(int level, const std::string& hier) VL_MT_SAFE {
         m_sptrace.dumpvars(level, hier);
     }
+    void dumpvars(const VerilatedTraceDumpVarsEntries& entries) VL_MT_SAFE {
+        m_sptrace.dumpvars(entries);
+    }
 
     // Internal class access
     VerilatedSaif* spTrace() { return &m_sptrace; }
diff --git a/include/verilated_trace.h b/include/verilated_trace.h
index 15e3cd964..1f7680cb3 100644
--- a/include/verilated_trace.h
+++ b/include/verilated_trace.h
@@ -313,7 +313,7 @@ private:
     uint32_t m_maxBits = 0;  // Number of bits in the widest signal
     void* m_initUserp = nullptr;  // The callback userp of the instance currently being initialized
     // TODO: Should keep this as a Trie, that is how it's accessed all the time.
-    std::vector<std::pair<int, std::string>> m_dumpvars;  // dumpvar() entries
+    VerilatedTraceDumpVarsEntries m_dumpvars;  // dumpvar() entries
     double m_timeRes = 1e-9;  // Time resolution (ns/ms etc)
     double m_timeUnit = 1e-0;  // Time units (ns/ms etc)
     uint64_t m_timeLastDump = 0;  // Last time we did a dump
@@ -371,6 +371,58 @@ private:
     VL_UNCOPYABLE(VerilatedTrace);
 
 protected:
+    struct DumpvarsPath final {
+        std::string m_name;
+        std::vector<size_t> m_scopeEndps;
+
+        static bool countsAsScopeLevel(VerilatedTracePrefixType type) {
+            return type == VerilatedTracePrefixType::SCOPE_MODULE
+                   || type == VerilatedTracePrefixType::SCOPE_INTERFACE
+                   || type == VerilatedTracePrefixType::ROOTIO_WRAPPER;
+        }
+        static char separator(VerilatedTracePrefixType type) {
+            return (type == VerilatedTracePrefixType::ARRAY_PACKED
+                    || type == VerilatedTracePrefixType::ARRAY_UNPACKED)
+                       ? '\0'
+                       : '.';
+        }
+
+        static std::string trimPrefix(const std::string& prefix) {
+            if (!prefix.empty() && prefix.back() == ' ') {
+                return prefix.substr(0, prefix.size() - 1);
+            }
+            return prefix;
+        }
+
+        void append(const std::string& piece, VerilatedTracePrefixType type,
+                    bool countLevel = true) {
+            if (piece.empty()) return;
+            const char sep = separator(type);
+            if (sep && !m_name.empty()) m_name += sep;
+            m_name += piece;
+            if (countLevel && countsAsScopeLevel(type)) m_scopeEndps.push_back(m_name.size());
+        }
+
+        bool matchesPrefix(const std::string& prefix) const {
+            if (prefix.empty()) return true;
+            if (m_name.compare(0, prefix.size(), prefix) != 0) return false;
+            return prefix.size() >= m_name.size() || m_name[prefix.size()] == '.';
+        }
+
+        int scopeLevelsBelow(size_t prefixLen) const {
+            int levels = 0;
+            for (const size_t endp : m_scopeEndps) {
+                if (endp > prefixLen) ++levels;
+            }
+            return levels;
+        }
+
+        bool matches(const VerilatedTraceDumpVarsEntry& entry) const {
+            if (!matchesPrefix(entry.m_hier)) return false;
+            return entry.m_level <= 0 || scopeLevelsBelow(entry.m_hier.size()) < entry.m_level;
+        }
+    };
+
     //=========================================================================
     // Internals available to format-specific implementations
 
@@ -390,7 +442,7 @@ protected:
     void traceInit() VL_MT_UNSAFE;
 
     // Declare new signal and return true if enabled
-    bool declCode(uint32_t code, const std::string& declName, uint32_t bits);
+    bool declCode(uint32_t code, const DumpvarsPath& path, uint32_t bits);
 
     void closeBase();
     void flushBase();
@@ -405,6 +457,23 @@ protected:
         return str.substr(idx + 1);
     }
 
+    static DumpvarsPath dumpvarsPath(
+        const std::vector<std::pair<std::string, VerilatedTracePrefixType>>& prefixStack,
+        const char* namep) {
+        DumpvarsPath out;
+        std::string prev;
+        for (size_t i = 1; i < prefixStack.size(); ++i) {
+            const std::string curr = DumpvarsPath::trimPrefix(prefixStack[i].first);
+            if (curr.size() < prev.size()) continue;
+            std::string piece = curr.substr(prev.size());
+            if (!piece.empty() && piece.front() == ' ') piece.erase(0, 1);
+            out.append(piece, prefixStack[i].second);
+            prev = curr;
+        }
+        out.append(namep ? namep : "", prefixStack.back().second, false);
+        return out;
+    }
+
     //=========================================================================
     // Virtual functions to be provided by the format-specific implementation
 
@@ -439,6 +508,11 @@ public:
     // Set variables to dump, using $dumpvars format
     // If level = 0, dump everything and hier is then ignored
     void dumpvars(int level, const std::string& hier) VL_MT_SAFE;
+    void dumpvars(const VerilatedTraceDumpVarsEntries& entries) VL_MT_SAFE {
+        for (const VerilatedTraceDumpVarsEntry& entry : entries) {
+            dumpvars(entry.m_level, entry.m_hier);
+        }
+    }
 
     // Call
     void dump(uint64_t timeui) VL_MT_SAFE_EXCLUDES(m_mutex);
diff --git a/include/verilated_trace_imp.h b/include/verilated_trace_imp.h
index 635e3e897..20f7332df 100644
--- a/include/verilated_trace_imp.h
+++ b/include/verilated_trace_imp.h
@@ -335,14 +335,15 @@ void VerilatedTrace<VL_SUB_T, VL_BUF_T>::traceInit() VL_MT_UNSAFE {
 
     // Apply enables
     if (m_sigs_enabledp) VL_DO_CLEAR(delete[] m_sigs_enabledp, m_sigs_enabledp = nullptr);
-    if (!m_sigs_enabledVec.empty()) {
+    if (!m_sigs_enabledVec.empty() || !m_dumpvars.empty()) {
         // Else if was empty, m_sigs_enabledp = nullptr to short circuit tests
         // But it isn't, so alloc one bit for each code to indicate enablement
         // We don't want to still use m_signs_enabledVec as std::vector<bool> is not
         // guaranteed to be fast
         m_sigs_enabledp = new uint32_t[1 + VL_WORDS_I(nextCode())]{0};
         m_sigs_enabledVec.reserve(nextCode());
-        for (size_t code = 0; code < nextCode(); ++code) {
+        size_t iter = nextCode() > m_sigs_enabledVec.size() ? m_sigs_enabledVec.size() : nextCode();
+        for (size_t code = 0; code < iter; ++code) {
             if (m_sigs_enabledVec[code]) {
                 m_sigs_enabledp[VL_BITWORD_I(code)] |= 1U << VL_BITBIT_I(code);
             }
@@ -369,7 +370,8 @@ void VerilatedTrace<VL_SUB_T, VL_BUF_T>::traceInit() VL_MT_UNSAFE {
 }
 
 template <>
-bool VerilatedTrace<VL_SUB_T, VL_BUF_T>::declCode(uint32_t code, const std::string& declName,
+bool VerilatedTrace<VL_SUB_T, VL_BUF_T>::declCode(uint32_t code,
+                                                  const DumpvarsPath& path,
                                                   uint32_t bits) {
     if (VL_UNCOVERABLE(!code)) {
         VL_FATAL_MT(__FILE__, __LINE__, "", "Internal: internal trace problem, code 0 is illegal");
@@ -377,21 +379,8 @@ bool VerilatedTrace<VL_SUB_T, VL_BUF_T>::declCode(uint32_t code, const std::stri
     // To keep it simple, this is O(enables * signals), but we expect few enables
     bool enabled = false;
     if (m_dumpvars.empty()) enabled = true;
-    for (const auto& item : m_dumpvars) {
-        const int dumpvarsLevel = item.first;
-        const char* dvp = item.second.c_str();
-        const char* np = declName.c_str();
-        while (*dvp && *dvp == *np) {
-            ++dvp;
-            ++np;
-        }
-        if (*dvp) continue;  // Didn't match dumpvar item
-        if (*np && *np != ' ') continue;  // e.g. "t" isn't a match for "top"
-        int levels = 0;
-        while (*np) {
-            if (*np++ == ' ') ++levels;
-        }
-        if (levels > dumpvarsLevel) continue;  // Too deep
+    for (const auto& entry : m_dumpvars) {
+        if (!path.matches(entry)) continue;
         // We only need to set first code word if it's a multicode signal
         // as that's all we'll check for later
         if (m_sigs_enabledVec.size() <= code) m_sigs_enabledVec.resize((code + 1024) * 2);
@@ -434,16 +423,8 @@ void VerilatedTrace<VL_SUB_T, VL_BUF_T>::set_time_resolution(const std::string&
 }
 template <>
 void VerilatedTrace<VL_SUB_T, VL_BUF_T>::dumpvars(int level, const std::string& hier) VL_MT_SAFE {
-    if (level == 0) {
-        m_dumpvars.clear();  // empty = everything on
-    } else {
-        // Convert Verilog . separators to trace space separators
-        std::string hierSpaced = hier;
-        for (auto& i : hierSpaced) {
-            if (i == '.') i = ' ';
-        }
-        m_dumpvars.emplace_back(level, hierSpaced);
-    }
+    if (level == 0 && hier.empty()) m_dumpvars.clear();
+    m_dumpvars.emplace_back(level, hier);
 }
 
 template <>
diff --git a/include/verilated_vcd_c.cpp b/include/verilated_vcd_c.cpp
index 3e0552752..596596c78 100644
--- a/include/verilated_vcd_c.cpp
+++ b/include/verilated_vcd_c.cpp
@@ -384,8 +384,9 @@ void VerilatedVcd::declare(uint32_t code, const char* name, const char* wirep, b
     const int bits = ((msb > lsb) ? (msb - lsb) : (lsb - msb)) + 1;
 
     const std::string hierarchicalName = m_prefixStack.back().first + name;
+    const auto dumpvarsPath = Super::dumpvarsPath(m_prefixStack, name);
 
-    const bool enabled = Super::declCode(code, hierarchicalName, bits);
+    const bool enabled = Super::declCode(code, dumpvarsPath, bits);
 
     if (m_suffixes.size() <= nextCode() * VL_TRACE_SUFFIX_ENTRY_SIZE) {
         m_suffixes.resize(nextCode() * VL_TRACE_SUFFIX_ENTRY_SIZE * 2, 0);
diff --git a/include/verilated_vcd_c.h b/include/verilated_vcd_c.h
index 4731facfe..6ff35c85a 100644
--- a/include/verilated_vcd_c.h
+++ b/include/verilated_vcd_c.h
@@ -351,6 +351,9 @@ public:
     void dumpvars(int level, const std::string& hier) VL_MT_SAFE {
         m_sptrace.dumpvars(level, hier);
     }
+    void dumpvars(const VerilatedTraceDumpVarsEntries& entries) VL_MT_SAFE {
+        m_sptrace.dumpvars(entries);
+    }
 
     // Internal class access
     VerilatedVcd* spTrace() { return &m_sptrace; }
diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
index d03324eed..c2837afa5 100644
--- a/src/CMakeLists.txt
+++ b/src/CMakeLists.txt
@@ -86,6 +86,7 @@ set(HEADERS
     V3DfgPeepholePatterns.h
     V3DfgVertices.h
     V3DiagSarif.h
+    V3DumpVars.h
     V3DupFinder.h
     V3EmitC.h
     V3EmitCBase.h
diff --git a/src/V3AstNodeStmt.h b/src/V3AstNodeStmt.h
index 5a332599c..03c1d3d58 100644
--- a/src/V3AstNodeStmt.h
+++ b/src/V3AstNodeStmt.h
@@ -638,6 +638,8 @@ class AstDumpCtl final : public AstNodeStmt {
     // $dumpon etc
     // Parents: expr
     // @astgen op1 := exprp : Optional[AstNodeExpr] // Expression based on type of statement
+    // @astgen op2 := scopeNamep : Optional[AstScopeName] // Scope of the $dumpvars call site
+    // @astgen op3 := targetsp : List[AstNode] // Optional scope/signal targets for $dumpvars
     const VDumpCtlType m_ctlType;  // Type of operation
 public:
     AstDumpCtl(FileLine* fl, VDumpCtlType ctlType, AstNodeExpr* exprp = nullptr)
@@ -652,7 +654,9 @@ public:
     bool isPredictOptimizable() const override { return false; }
     bool isPure() override { return false; }
     virtual bool cleanOut() const { return true; }
-    bool sameNode(const AstNode* /*samep*/) const override { return true; }
+    bool sameNode(const AstNode* samep) const override {
+        return ctlType() == VN_DBG_AS(samep, DumpCtl)->ctlType();
+    }
     VDumpCtlType ctlType() const { return m_ctlType; }
 };
 class AstEventControl final : public AstNodeStmt {
diff --git a/src/V3Begin.cpp b/src/V3Begin.cpp
index fdfe2abe7..6507de0e0 100644
--- a/src/V3Begin.cpp
+++ b/src/V3Begin.cpp
@@ -377,6 +377,12 @@ class BeginVisitor final : public VNVisitor {
         // If there's a %m in the display text, we add a special node that will contain the name()
         // Similar code in V3Inline
         if (nodep->user1SetOnce()) return;  // Don't double-add text's
+        // $dumpvars scope names resolve relative to the enclosing module,
+        // not the block, so don't add block scope components for them.
+        if (VN_IS(nodep->backp(), DumpCtl)) {
+            iterateChildren(nodep);
+            return;
+        }
         // DPI svGetScope doesn't include function name, but %m does
         const std::string scname = nodep->forFormat() ? m_displayScope : m_namedScope;
         // To keep correct visual order, must add before exising
diff --git a/src/V3DumpVars.h b/src/V3DumpVars.h
new file mode 100644
index 000000000..a5d2c706a
--- /dev/null
+++ b/src/V3DumpVars.h
@@ -0,0 +1,45 @@
+// -*- mode: C++; c-file-style: "cc-mode" -*-
+//*************************************************************************
+// DESCRIPTION: Verilator: Dumpvars helpers
+//
+// Code available from: https://verilator.org
+//
+//*************************************************************************
+//
+// This program is free software; you can redistribute it and/or modify it
+// under the terms of either the GNU Lesser General Public License Version 3
+// or the Perl Artistic License Version 2.0.
+// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+//
+//*************************************************************************
+
+#ifndef VERILATOR_V3DUMPVARS_H_
+#define VERILATOR_V3DUMPVARS_H_
+
+#include "config_build.h"
+#include "verilatedos.h"
+
+// Tagged $dumpvars target string.  During compile-time resolution in V3LinkDot
+// each target is tagged with a prefix that tells EmitC how to emit the
+// corresponding runtime code.
+struct VDumpVarsTag final {
+    const char* const prefix;
+    const size_t prefixLen;
+    template <size_t N>
+    constexpr VDumpVarsTag(const char (&s)[N])
+        : prefix{s}
+        , prefixLen{N - 1} {}
+    bool matches(const string& target) const { return target.compare(0, prefixLen, prefix) == 0; }
+    string make(const string& target) const { return string{prefix, prefixLen} + target; }
+    string strip(const string& target) const {
+        return matches(target) ? target.substr(prefixLen) : target;
+    }
+};
+
+// Fully resolved to a compile-time hierarchy path
+constexpr VDumpVarsTag kDumpvarsResolved{"@dumpvars:"};
+// First component must match the C++ wrapper root name at runtime
+constexpr VDumpVarsTag kDumpvarsRuntimeRoot{"@dumpvars_root:"};
+
+#endif  // Guard
diff --git a/src/V3EmitCFunc.h b/src/V3EmitCFunc.h
index 465b6b585..6d0cb6790 100644
--- a/src/V3EmitCFunc.h
+++ b/src/V3EmitCFunc.h
@@ -21,6 +21,7 @@
 #include "verilatedos.h"
 
 #include "V3EmitCConstInit.h"
+#include "V3DumpVars.h"
 #include "V3Global.h"
 #include "V3MemberMap.h"
 
@@ -898,6 +899,102 @@ public:
         if (nodep->addNewline()) text += "\n";
         displayNode(nodep, nodep->fmtp(), text, nodep->fmtp()->exprsp(), false);
     }
+    static bool dumpvarsHasScopePrefix(const string& target, const string& scope) {
+        return target == scope
+               || (target.length() > scope.length() && target.compare(0, scope.length(), scope) == 0
+                   && target[scope.length()] == '.');
+    }
+
+    static string dumpvarsHierPath(const string& scope, const string& target) {
+        if (target.empty()) return scope;
+        if (kDumpvarsResolved.matches(target)) return kDumpvarsResolved.strip(target);
+        if (scope.empty() || dumpvarsHasScopePrefix(target, scope)) return target;
+        return VString::dot(scope, ".", target);
+    }
+
+    // Emit C++ code that registers a $dumpvars filter at runtime.
+    // Builds the full hierarchy path from vlSymsp->name() and the given suffix,
+    // then calls dumpvarsAdd with the specified level expression.
+    void emitDumpVarsAdd(const AstDumpCtl* nodep, const string& hierPath,
+                         const string& levelExpr) {
+        putns(nodep, "{ std::string __vlDvHier{vlSymsp->name()};\n");
+        if (!hierPath.empty()) {
+            puts("if (!__vlDvHier.empty()) __vlDvHier += '.';\n");
+            puts("__vlDvHier += \"");
+            puts(V3OutFormatter::quoteNameControls(hierPath));
+            puts("\";\n");
+        }
+        puts("vlSymsp->_vm_contextp__->dumpvarsAdd(");
+        puts(levelExpr);
+        puts(", __vlDvHier); }\n");
+    }
+    void emitDumpVarsAddRuntimeRoot(const AstDumpCtl* nodep, const string& target,
+                                    const string& levelExpr) {
+        const string::size_type dotPos = target.find('.');
+        const string rootName = dotPos == string::npos ? target : target.substr(0, dotPos);
+        const string suffix = dotPos == string::npos ? "" : target.substr(dotPos + 1);
+        putns(nodep, "{ const std::string __vlDvRoot{vlSymsp->name()};\n");
+        puts("if (__vlDvRoot != \"");
+        puts(V3OutFormatter::quoteNameControls(rootName));
+        puts("\") VL_FATAL_MT(\"");
+        puts(V3OutFormatter::quoteNameControls(protect(nodep->fileline()->filename())));
+        puts("\", ");
+        puts(cvtToStr(nodep->fileline()->lineno()));
+        puts(", \"\", \"$dumpvars target not found: ");
+        puts(V3OutFormatter::quoteNameControls(target));
+        puts("\");\n");
+        puts("std::string __vlDvHier{__vlDvRoot};\n");
+        if (!suffix.empty()) {
+            puts("__vlDvHier += '.';\n");
+            puts("__vlDvHier += \"");
+            puts(V3OutFormatter::quoteNameControls(suffix));
+            puts("\";\n");
+        }
+        puts("vlSymsp->_vm_contextp__->dumpvarsAdd(");
+        puts(levelExpr);
+        puts(", __vlDvHier); }\n");
+    }
+    // Emit $dumpvars filter logic when scope info is available.
+    void emitDumpVarsWithScope(AstDumpCtl* nodep) {
+        UASSERT_OBJ(nodep->scopeNamep(), nodep, "$dumpvars missing AstScopeName");
+        const string scope = nodep->scopeNamep()->scopePrettySymName();
+        // Resolve the level expression (constant or runtime)
+        const AstConst* const levelp = VN_CAST(nodep->exprp(), Const);
+        string levelExpr;
+        if (levelp) {
+            levelExpr = cvtToStr(levelp->toUInt());
+        } else {
+            putns(nodep, "{ const int __vlDvLevel = ");
+            iterateConst(nodep->exprp());
+            puts(";\n");
+            levelExpr = "__vlDvLevel";
+        }
+        // Emit one dumpvarsAdd call per target, or one for the scope itself.
+        // The no-target $dumpvars(0) form is design-global and should not be
+        // narrowed to the lexical scope where it appears.
+        if (nodep->targetsp()) {
+            for (AstNode* tp = nodep->targetsp(); tp; tp = tp->nextp()) {
+                const string target = VN_AS(tp, Text)->text();
+                if (kDumpvarsRuntimeRoot.matches(target)) {
+                    emitDumpVarsAddRuntimeRoot(nodep, kDumpvarsRuntimeRoot.strip(target),
+                                               levelExpr);
+                } else {
+                    emitDumpVarsAdd(nodep, dumpvarsHierPath(scope, target), levelExpr);
+                }
+            }
+        } else {
+            if (levelp && levelp->toUInt() == 0 && scope.find('.') == string::npos) {
+                putns(nodep, "vlSymsp->_vm_contextp__->dumpvarsAdd(");
+                puts(levelExpr);
+                puts(", \"\"s);\n");
+            } else {
+                emitDumpVarsAdd(nodep, scope, levelExpr);
+            }
+        }
+        if (!levelp) puts("}\n");
+        putns(nodep, "vlSymsp->_traceDumpClose();\n");
+        putns(nodep, "vlSymsp->_traceDumpOpen();\n");
+    }
     void visit(AstDumpCtl* nodep) override {
         switch (nodep->ctlType()) {
         case VDumpCtlType::FILE:
@@ -906,9 +1003,8 @@ public:
             puts(");\n");
             break;
         case VDumpCtlType::VARS:
-            // We ignore number of levels to dump in exprp()
             if (v3Global.opt.trace()) {
-                putns(nodep, "vlSymsp->_traceDumpOpen();\n");
+                emitDumpVarsWithScope(nodep);
             } else {
                 putns(nodep, "VL_PRINTF_MT(\"-Info: ");
                 puts(V3OutFormatter::quoteNameControls(protect(nodep->fileline()->filename())));
diff --git a/src/V3EmitCSyms.cpp b/src/V3EmitCSyms.cpp
index 31a125414..44aed1e21 100644
--- a/src/V3EmitCSyms.cpp
+++ b/src/V3EmitCSyms.cpp
@@ -1215,7 +1215,8 @@ void EmitCSyms::emitSymImp(const AstNetlist* netlistp) {
         puts("const VerilatedLockGuard lock{__Vm_dumperMutex};\n");
         puts("if (VL_UNLIKELY(!__Vm_dumperp)) {\n");
         puts("__Vm_dumperp = new " + v3Global.opt.traceClassLang() + "();\n");
-        puts("__Vm_modelp->trace(__Vm_dumperp, 0, 0);\n");
+        puts("__Vm_dumperp->dumpvars(_vm_contextp__->dumpvars());\n");
+        puts("_vm_contextp__->trace(__Vm_dumperp, 0, 0);\n");
         puts("const std::string dumpfile = _vm_contextp__->dumpfileCheck();\n");
         puts("__Vm_dumperp->open(dumpfile.c_str());\n");
         puts("__Vm_dumping = true;\n");
diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index 5d368024d..a99e86df6 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -80,6 +80,38 @@
 
 VL_DEFINE_DEBUG_FUNCTIONS;
 
+static string dumpvarsTargetText(const AstNode* nodep) {
+    if (!nodep) return "";
+    if (const AstText* const textp = VN_CAST(nodep, Text)) return textp->text();
+    if (const AstCellRef* const refp = VN_CAST(nodep, CellRef)) return refp->name();
+    if (const AstSelBit* const selp = VN_CAST(nodep, SelBit)) {
+        const string from = dumpvarsTargetText(selp->fromp());
+        const string bit = dumpvarsTargetText(selp->bitp());
+        if (from.empty()) return "";
+        return from + "[" + bit + "]";
+    }
+    if (const AstCellArrayRef* const refp = VN_CAST(nodep, CellArrayRef)) {
+        string out = refp->name();
+        for (const AstNodeExpr* selp = refp->selp(); selp;
+             selp = VN_CAST(selp->nextp(), NodeExpr)) {
+            out += "[" + dumpvarsTargetText(selp) + "]";
+        }
+        return out;
+    }
+    if (const AstConst* const constp = VN_CAST(nodep, Const)) return cvtToStr(constp->toSInt());
+    if (const AstParseRef* const refp = VN_CAST(nodep, ParseRef)) return refp->prettyName();
+    if (const AstVarRef* const refp = VN_CAST(nodep, VarRef)) return refp->name();
+    if (const AstVarXRef* const refp = VN_CAST(nodep, VarXRef)) {
+        return VString::dot(refp->dotted(), ".", refp->name());
+    }
+    if (const AstDot* const dotp = VN_CAST(nodep, Dot)) {
+        const string lhs = dumpvarsTargetText(dotp->lhsp());
+        const string rhs = dumpvarsTargetText(dotp->rhsp());
+        return VString::dot(lhs, ".", rhs);
+    }
+    return nodep->prettyName();
+}
+
 static string extractDottedPath(AstNode* nodep, bool& hasPartSelect) {
     if (AstParseRef* const refp = VN_CAST(nodep, ParseRef)) {
         return refp->name();
@@ -3141,6 +3173,133 @@ class LinkDotResolveVisitor final : public VNVisitor {
         }
     } m_ds;  // State to preserve across recursions
 
+    static bool dumpvarsMatchesLocalModule(const VSymEnt* symp, const string& ident) {
+        if (!symp) return false;
+        if (const AstCell* const cellp = VN_CAST(symp->nodep(), Cell)) {
+            return cellp->modp() && cellp->modp()->origName() == ident;
+        }
+        if (const AstCellInline* const inlinep = VN_CAST(symp->nodep(), CellInline))
+            return inlinep->origModName() == ident;
+        if (const AstNodeModule* const modp = VN_CAST(symp->nodep(), NodeModule))
+            return modp->origName() == ident;
+        return false;
+    }
+
+    static string dumpvarsResolvedPath(VSymEnt* symp) {
+        string path;
+        for (VSymEnt* walkp = symp; walkp && walkp->parentp(); walkp = walkp->parentp()) {
+            const AstNode* const np = walkp->nodep();
+            const string piece = !np                     ? ""
+                                 : VN_IS(np, NodeModule) ? VN_AS(np, NodeModule)->origName()
+                                 : VN_IS(np, Cell)       ? VN_AS(np, Cell)->origName()
+                                 : VN_IS(np, VarScope)   ? VN_AS(np, VarScope)->varp()->name()
+                                                         : np->name();
+            if (piece.empty()) continue;
+            path = path.empty() ? piece : piece + "." + path;
+        }
+        return path;
+    }
+
+    static string dumpvarsBracketToInternal(const string& ident) {
+        const string::size_type lbr = ident.find('[');
+        if (lbr == string::npos) return ident;
+        const string::size_type rbr = ident.find(']', lbr);
+        if (rbr == string::npos) return ident;
+        return ident.substr(0, lbr) + "__BRA__" + ident.substr(lbr + 1, rbr - lbr - 1) + "__KET__"
+               + dumpvarsBracketToInternal(ident.substr(rbr + 1));
+    }
+
+    VSymEnt* findDumpvarsLocal(FileLine* refLocationp, const string& dotname, string& baddot,
+                               VSymEnt*& okSymp) {
+        if (!m_curSymp) return nullptr;
+        const string::size_type dotPos = dotname.find('.');
+        const string ident = dotPos == string::npos ? dotname : dotname.substr(0, dotPos);
+        const string leftname = dotPos == string::npos ? "" : dotname.substr(dotPos + 1);
+        baddot = ident;
+        okSymp = m_curSymp;
+
+        const auto findLocal = [&](const string& name) -> VSymEnt* {
+            if (dumpvarsMatchesLocalModule(m_curSymp, name)) return m_curSymp;
+            if (VSymEnt* const symp = m_curSymp->findIdFallback(name)) return symp;
+            const string internal = dumpvarsBracketToInternal(name);
+            if (internal != name) {
+                if (VSymEnt* const symp = m_curSymp->findIdFallback(internal)) return symp;
+            }
+            if (!m_statep->forPrearray()) return nullptr;
+            auto pos = name.rfind("__BRA__");
+            if (pos == string::npos) pos = name.find('[');
+            return (pos != string::npos && pos > 0)
+                       ? m_curSymp->findIdFallback(name.substr(0, pos))
+                       : nullptr;
+        };
+
+        VSymEnt* const symp = findLocal(ident);
+        if (!symp) return nullptr;
+        okSymp = symp;
+        if (leftname.empty()) return symp;
+        // Non-scope nodes (e.g. struct variables) don't have sub-symbols,
+        // accept the path without resolving further.
+        if (!(VN_IS(symp->nodep(), Cell) || VN_IS(symp->nodep(), CellInline)
+              || VN_IS(symp->nodep(), NodeModule))) {
+            return symp;
+        }
+        return m_statep->findDotted(refLocationp, symp, leftname, baddot, okSymp, false);
+    }
+
+    // Resolve a single $dumpvars target string against the symbol table.
+    // Returns a tagged string that tells EmitC how to generate the runtime code.
+    string resolveDumpvarsTarget(FileLine* fl, const string& target, AstNode* targetsp) {
+        if (target.empty() || !m_curSymp) return target;
+
+        string baddot;
+        VSymEnt* okSymp = nullptr;
+        const auto fail = [&]() {
+            fl->v3error("$dumpvars target not found: " << target);
+            return target;
+        };
+        const auto findFromRoot = [&](const string& path) {
+            return m_statep->findDotted(fl, m_statep->rootEntp(), path, baddot, okSymp, true);
+        };
+
+        if (findDumpvarsLocal(fl, target, baddot, okSymp)) return target;
+
+        if (VSymEnt* const rootSymp = findFromRoot(target)) {
+            const string resolved = dumpvarsResolvedPath(rootSymp);
+            if (!resolved.empty()) return kDumpvarsResolved.make(resolved);
+        }
+
+        const string::size_type dotPos = target.find('.');
+        if (dotPos == string::npos)
+            return v3Global.opt.main() ? fail() : kDumpvarsRuntimeRoot.make(target);
+
+        const string firstComp = target.substr(0, dotPos);
+        const string remaining = target.substr(dotPos + 1);
+        bool hasBareFirstComp = false;
+        for (AstNode* tp = targetsp; tp; tp = tp->nextp()) {
+            if (dumpvarsTargetText(tp) == firstComp) {
+                hasBareFirstComp = true;
+                break;
+            }
+        }
+
+        if (hasBareFirstComp) {
+            return findFromRoot(remaining) ? kDumpvarsRuntimeRoot.make(target) : fail();
+        }
+
+        if (v3Global.opt.main() && dumpvarsMatchesLocalModule(m_curSymp, firstComp)) {
+            if (!findDumpvarsLocal(fl, remaining, baddot, okSymp)) fail();
+            return target;
+        }
+
+        if (findDumpvarsLocal(fl, firstComp, baddot, okSymp)
+            && !(VN_IS(okSymp->nodep(), Cell) || VN_IS(okSymp->nodep(), CellInline)
+                 || VN_IS(okSymp->nodep(), NodeModule))) {
+            return target;
+        }
+
+        return v3Global.opt.main() ? fail() : kDumpvarsRuntimeRoot.make(target);
+    }
+
     // METHODS - Variables
     AstVar* createImplicitVar(VSymEnt* /*lookupSymp*/, AstParseRef* nodep, AstNodeModule* modp,
                               VSymEnt* moduleSymp, bool noWarn) {
@@ -6034,6 +6193,35 @@ class LinkDotResolveVisitor final : public VNVisitor {
         UINFO(5, indent() << "visit " << nodep);
         iterateChildren(nodep);
     }
+    void visit(AstDumpCtl* nodep) override {
+        LINKDOT_VISIT_START();
+        UINFO(5, indent() << "visit " << nodep);
+        if (nodep->exprp()) iterateAndNextNull(nodep->exprp());
+        AstNode* targetsp = nodep->targetsp();
+        if (!targetsp) return;
+        // Resolve each target from its parse-tree form (AstParseRef/AstDot)
+        // into a plain text name, validating it against the symbol table.
+        VNRelinker relinker;
+        targetsp->unlinkFrBackWithNext(&relinker);
+        AstNode* newTargetsp = nullptr;
+        for (AstNode* targetp = targetsp; targetp;) {
+            AstNode* const nextp = targetp->nextp();
+            if (nextp) nextp->unlinkFrBackWithNext();
+            // Skip if already resolved to text.
+            if (VN_IS(targetp, Text)) {
+                newTargetsp = AstNode::addNextNull(newTargetsp, targetp);
+                targetp = nextp;
+                continue;
+            }
+            const string target = dumpvarsTargetText(targetp);
+            const string linkedTarget = resolveDumpvarsTarget(nodep->fileline(), target, targetsp);
+            VL_DO_DANGLING(pushDeletep(targetp), targetp);
+            newTargetsp
+                = AstNode::addNextNull(newTargetsp, new AstText{nodep->fileline(), linkedTarget});
+            targetp = nextp;
+        }
+        relinker.relink(newTargetsp);
+    }
     void visit(AstCellArrayRef* nodep) override {
         LINKDOT_VISIT_START();
         UINFO(5, indent() << "visit " << nodep);
diff --git a/src/V3LinkDot.h b/src/V3LinkDot.h
index 257d522c3..78cdd64d0 100644
--- a/src/V3LinkDot.h
+++ b/src/V3LinkDot.h
@@ -21,6 +21,7 @@
 #include "verilatedos.h"
 
 #include "V3Ast.h"
+#include "V3DumpVars.h"
 #include "V3Error.h"
 
 //============================================================================
diff --git a/src/V3LinkResolve.cpp b/src/V3LinkResolve.cpp
index 3690fdb39..09c5475eb 100644
--- a/src/V3LinkResolve.cpp
+++ b/src/V3LinkResolve.cpp
@@ -461,6 +461,14 @@ class LinkResolveVisitor final : public VNVisitor {
         }
     }
 
+    void visit(AstDumpCtl* nodep) override {
+        if (nodep->ctlType() == VDumpCtlType::VARS && !nodep->scopeNamep()) {
+            // Attach AstScopeName so V3Scope/V3Inline build the call-site scope path
+            nodep->scopeNamep(new AstScopeName{nodep->fileline(), false});
+        }
+        iterateChildren(nodep);
+    }
+
     void visit(AstUdpTable* nodep) override {
         UINFO(5, "UDPTABLE  " << nodep);
         if (!v3Global.opt.bboxUnsup()) {
diff --git a/src/V3Task.cpp b/src/V3Task.cpp
index d05e44254..95fce46be 100644
--- a/src/V3Task.cpp
+++ b/src/V3Task.cpp
@@ -1599,6 +1599,34 @@ class TaskVisitor final : public VNVisitor {
             beginp = createInlinedFTask(nodep, namePrefix, outvscp);
             ++m_statInlines;
         }
+        // Propagate the caller scope into the cloned task body so scope-sensitive
+        // operations such as $dumpvars reflect the call site even when the task
+        // was defined at $unit. When V3Inline added extra hierarchy, include it.
+        // This applies to:
+        // 1. Any AstDumpCtl/AstScopeName in the inlined body (direct $dumpvars)
+        // 2. Any nested AstNodeFTaskRef in the inlined body (indirect $dumpvars)
+        {
+            const string& callerDots = nodep->inlinedDots();
+            string scopePath = "__DOT__"s + m_scopep->name();
+            if (!callerDots.empty()) {
+                string dots = callerDots;
+                string::size_type pos;
+                while ((pos = dots.find('.')) != string::npos) dots.replace(pos, 1, "__DOT__");
+                scopePath += "__DOT__" + dots;
+            }
+            beginp->foreachAndNext([&](AstDumpCtl* dcp) {
+                if (AstScopeName* const snp = dcp->scopeNamep()) {
+                    snp->scopeAttr(scopePath);
+                    snp->scopeEntr(scopePath);
+                }
+            });
+            if (!callerDots.empty()) {
+                // Propagate inlinedDots to nested task references.
+                beginp->foreachAndNext([&](AstNodeFTaskRef* refp) {
+                    if (refp->inlinedDots().empty()) refp->inlinedDots(callerDots);
+                });
+            }
+        }
 
         if (VN_IS(nodep, New)) {  // New not legal as while() condition
             insertBeforeStmt(nodep, beginp);
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index c0b25f1c8..54269e8e6 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -6266,7 +6266,14 @@ class WidthVisitor final : public VNVisitor {
     }
     void visit(AstDumpCtl* nodep) override {
         assertAtStatement(nodep);
-        if (nodep->exprp()) iterateCheckString(nodep, "LHS", nodep->exprp(), BOTH);
+        if (nodep->exprp()) {
+            if (nodep->ctlType() == VDumpCtlType::VARS) {
+                // $dumpvars level argument is an integer
+                userIterateAndNext(nodep->exprp(), WidthVP{SELF, BOTH}.p());
+            } else {
+                iterateCheckString(nodep, "LHS", nodep->exprp(), BOTH);
+            }
+        }
     }
     void visit(AstFOpen* nodep) override {
         // Although a system function in IEEE, here a statement which sets the file pointer (MCD)
diff --git a/src/verilog.y b/src/verilog.y
index 2585fdc11..bbb0d285d 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -4215,15 +4215,17 @@ system_t_stmt_call<nodeStmtp>:  // IEEE: part of system_tf_call (as task returni
         //
         |       yD_DUMPPORTS '(' idDottedSel ',' expr ')'  { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::FILE, $5}; DEL($3);
                                                           $$->addNext(new AstDumpCtl{$<fl>1, VDumpCtlType::VARS,
-                                                                                     new AstConst{$<fl>1, 1}}); }
+                                                                                     new AstConst{$<fl>1, 0}}); }
         |       yD_DUMPPORTS '(' ',' expr ')'           { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::FILE, $4};
                                                           $$->addNext(new AstDumpCtl{$<fl>1, VDumpCtlType::VARS,
-                                                                                     new AstConst{$<fl>1, 1}}); }
+                                                                                     new AstConst{$<fl>1, 0}}); }
         |       yD_DUMPFILE '(' expr ')'                { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::FILE, $3}; }
         |       yD_DUMPVARS parenE                      { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::VARS,
                                                                               new AstConst{$<fl>1, 0}}; }
         |       yD_DUMPVARS '(' expr ')'                { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::VARS, $3}; }
-        |       yD_DUMPVARS '(' expr ',' exprList ')'   { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::VARS, $3}; DEL($5); }
+        |       yD_DUMPVARS '(' expr ',' exprList ')'   { AstDumpCtl* const dumpctlp = new AstDumpCtl{$<fl>1, VDumpCtlType::VARS, $3};
+                                                          dumpctlp->addTargetsp($5);
+                                                          $$ = dumpctlp; }
         |       yD_DUMPALL parenE                       { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::ALL}; }
         |       yD_DUMPALL '(' expr ')'                 { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::ALL}; DEL($3); }
         |       yD_DUMPFLUSH parenE                     { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::FLUSH}; }
diff --git a/test_regress/t/t_trace_dumpvars.out b/test_regress/t/t_trace_dumpvars.out
new file mode 100644
index 000000000..6531d5f6a
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars.out
@@ -0,0 +1,29 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module $rootio $end
+    $var wire 1 % clk $end
+ $upscope $end
+ $scope module t $end
+  $var wire 1 % clk $end
+  $var wire 32 " cyc [31:0] $end
+  $scope module sub_a $end
+   $var wire 32 & ADD [31:0] $end
+   $var wire 32 " cyc [31:0] $end
+   $var wire 32 # value [31:0] $end
+  $upscope $end
+  $scope module sub_b $end
+   $var wire 32 ' ADD [31:0] $end
+   $var wire 32 " cyc [31:0] $end
+   $var wire 32 $ value [31:0] $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 "
+b00000000000000000000000000001010 #
+b00000000000000000000000000010100 $
+0%
+b00000000000000000000000000001010 &
+b00000000000000000000000000010100 '
diff --git a/test_regress/t/t_trace_dumpvars.py b/test_regress/t/t_trace_dumpvars.py
new file mode 100644
index 000000000..59ddf5500
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars.v b/test_regress/t/t_trace_dumpvars.v
new file mode 100644
index 000000000..d7758b922
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars.v
@@ -0,0 +1,384 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define STRINGIFY(x) `"x`"
+
+/* verilator lint_off MULTITOP */
+
+`ifdef TRACE_DUMPVARS_CASE_HIER_STRUCT
+`define TRACE_DUMPVARS_PACKED_STRUCT_BRANCH
+`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_STRUCT
+`define TRACE_DUMPVARS_PACKED_STRUCT_BRANCH
+`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_STRUCT2
+`define TRACE_DUMPVARS_PACKED_STRUCT_BRANCH
+`endif
+
+`ifdef TRACE_DUMPVARS_CASE_HIER_ARRAY
+`define TRACE_DUMPVARS_ARRAY_BRANCH
+`elsif TRACE_DUMPVARS_CASE_HIER_ARRAY_OOB
+`define TRACE_DUMPVARS_ARRAY_BRANCH
+`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_ARRAY
+`define TRACE_DUMPVARS_ARRAY_BRANCH
+`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_ARRAY_OOB
+`define TRACE_DUMPVARS_ARRAY_BRANCH
+`endif
+
+`ifdef TRACE_DUMPVARS_CASE_FUNC
+`define TRACE_DUMPVARS_TASK_BRANCH
+`elsif TRACE_DUMPVARS_CASE_TASK
+`define TRACE_DUMPVARS_TASK_BRANCH
+`elsif TRACE_DUMPVARS_CASE_TASK2
+`define TRACE_DUMPVARS_TASK_BRANCH
+`endif
+
+`ifdef TRACE_DUMPVARS_PACKED_STRUCT_BRANCH
+typedef struct packed {
+  logic [31:0] add;
+  logic [31:0] cyc;
+  logic [31:0] inner;
+} deep_t;
+
+typedef struct packed {
+  deep_t deep;
+  logic [31:0] value;
+} top_t;
+`endif
+
+`ifdef TRACE_DUMPVARS_TASK_BRANCH
+function int get_trace_level;
+  return 1;
+endfunction
+
+function void varsdump;
+  $dumpvars(get_trace_level());
+endfunction
+
+`ifdef TRACE_DUMPVARS_CASE_FUNC
+function void setup_trace;
+  $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
+  varsdump();
+endfunction
+`else
+task setup_trace;
+  $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
+  varsdump();
+endtask
+`endif
+
+`ifdef TRACE_DUMPVARS_CASE_TASK2
+task setup_trace_nested;
+  setup_trace();
+endtask
+`endif
+`endif
+
+module t
+`ifdef TRACE_DUMPVARS_CASE_ADD_MODULE
+;
+`else
+(
+    input clk
+);
+`endif
+  int cyc;
+`ifdef TRACE_DUMPVARS_CASE_ADD_MODULE
+  logic clk;
+`endif
+`ifdef TRACE_DUMPVARS_CASE_CONTEXT
+  int top;
+`endif
+`ifdef TRACE_DUMPVARS_CASE_WIRE
+  int counter;
+`endif
+`ifdef TRACE_DUMPVARS_PACKED_STRUCT_BRANCH
+  top_t mystruct;
+`endif
+`ifdef TRACE_DUMPVARS_CASE_STRUCT
+  typedef struct packed {
+    logic [7:0] \x ;
+    logic [7:0] y;
+  } point_t;
+
+  typedef struct packed {
+    point_t origin;
+    point_t size;
+  } rect_t;
+
+  rect_t rect;
+  point_t \pt ;
+`endif
+
+`ifdef TRACE_DUMPVARS_ARRAY_BRANCH
+  sub #(10) arr[2](.*);
+`elsif TRACE_DUMPVARS_CASE_GEN
+  genvar i;
+  generate
+    for (i = 0; i < 2; i = i + 1) begin : gen_sub
+      sub #(10 * (i + 1)) sub_i(.*);
+    end
+  endgenerate
+`elsif TRACE_DUMPVARS_PACKED_STRUCT_BRANCH
+`elsif TRACE_DUMPVARS_CASE_STRUCT
+  sub #(10) sub_a(.*);
+`else
+  sub #(10) sub_a(.*);
+  sub #(20) sub_b(.*);
+`endif
+
+`ifdef TRACE_DUMPVARS_CASE_ADD_MODULE
+  initial begin
+    clk = 0;
+    forever #1 clk = !clk;
+  end
+`endif
+
+  always @(posedge clk) begin
+    cyc <= cyc + 1;
+`ifdef TRACE_DUMPVARS_CASE_STRUCT
+    \pt .\x  <= \pt .\x  + 1;
+    \pt .y <= \pt .y + 2;
+    rect.origin.\x  <= rect.origin.\x  + 1;
+    rect.origin.y <= rect.origin.y + 2;
+    rect.size.\x  <= 8'd100;
+    rect.size.y <= 8'd200;
+`endif
+`ifdef TRACE_DUMPVARS_CASE_WIRE
+    counter <= counter + 2;
+`endif
+`ifdef TRACE_DUMPVARS_CASE_ADD_MODULE
+    if (cyc == 1) begin
+      $dumpfile({`STRINGIFY(`TEST_OBJ_DIR), "/simx1.vcd"});
+      $dumpvars(0, sub_b);
+    end
+`endif
+    if (cyc == 5) begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+    end
+  end
+
+`ifdef TRACE_DUMPVARS_CASE_ADD_MODULE
+  initial begin
+    $dumpfile({`STRINGIFY(`TEST_OBJ_DIR), "/simx0.vcd"});
+    $dumpvars(1, sub_a);
+  end
+`elsif TRACE_DUMPVARS_CASE_STRUCT
+  initial begin
+    $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
+    $dumpvars(1, rect.origin.\x );
+    $dumpvars(1, \pt .\y );
+  end
+`elsif TRACE_DUMPVARS_PACKED_STRUCT_BRANCH
+  initial begin
+    $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
+`ifdef TRACE_DUMPVARS_CASE_HIER_STRUCT
+    $dumpvars(1, t.mystruct.deep);
+`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_STRUCT
+    $dumpvars(1, cpptop.t.mystruct.deep);
+`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_STRUCT2
+    $dumpvars(1, cpptop.t.mystruct.deep.inner);
+`else
+`error "Missing packed struct trace_dumpvars case"
+`endif
+  end
+
+  always_comb begin
+    mystruct.value = cyc + 32'd10;
+    mystruct.deep.add = 32'd11;
+    mystruct.deep.cyc = cyc;
+    mystruct.deep.inner = cyc + mystruct.deep.add;
+  end
+`elsif TRACE_DUMPVARS_ARRAY_BRANCH
+  initial begin
+    $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
+`ifdef TRACE_DUMPVARS_CASE_HIER_ARRAY
+    $dumpvars(1, t.arr[1].deep);
+`elsif TRACE_DUMPVARS_CASE_HIER_ARRAY_OOB
+    $dumpvars(1, t.arr[999].deep);
+`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_ARRAY
+    $dumpvars(1, cpptop.t.arr[1].deep);
+`elsif TRACE_DUMPVARS_CASE_CPPTOP_HIER_ARRAY_OOB
+    $dumpvars(1, cpptop.t.arr[999].deep);
+`else
+`error "Missing array trace_dumpvars case"
+`endif
+  end
+`elsif TRACE_DUMPVARS_CASE_GEN
+  initial begin
+    $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
+    $dumpvars(0, gen_sub[0]);
+  end
+`elsif TRACE_DUMPVARS_TASK_BRANCH
+`elsif TRACE_DUMPVARS_CASE_HIER_GLOBAL
+`elsif TRACE_DUMPVARS_CASE_HIER_GLOBAL_TASK
+`elsif TRACE_DUMPVARS_CASE_NONCONST_SCOPE
+  initial begin: dumpblock
+    int level;
+    if (!$value$plusargs("LEVEL=%d", level)) level = 0;
+    $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
+    $dumpvars(level, t.sub_a);
+  end
+`elsif TRACE_DUMPVARS_CASE_SUB
+  initial begin
+    $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
+  end
+`elsif TRACE_DUMPVARS_CASE_SUB0
+  initial begin
+    $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
+  end
+`else
+  initial begin
+    $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
+`ifdef TRACE_DUMPVARS_CASE_BASE
+    $dumpvars(0);
+`elsif TRACE_DUMPVARS_CASE_SCOPE
+    $dumpvars(0, sub_a);
+`elsif TRACE_DUMPVARS_CASE_MULTI_SCOPE
+    $dumpvars(0+1, t, t.sub_a.deep_i);
+`elsif TRACE_DUMPVARS_CASE_ABS_SCOPE
+    $dumpvars(0, t.sub_a);
+`elsif TRACE_DUMPVARS_CASE_OVERRIDE
+    $dumpvars(1, t.sub_a.deep_i);
+    $dumpvars(0);
+`elsif TRACE_DUMPVARS_CASE_CONTEXT
+    $dumpvars(1, t.sub_a.deep_i);
+    $dumpvars(0, top);
+`elsif TRACE_DUMPVARS_CASE_LEVEL
+    $dumpvars(1);
+`elsif TRACE_DUMPVARS_CASE_LEVEL_SCOPE
+    $dumpvars(1, sub_a);
+`elsif TRACE_DUMPVARS_CASE_HIER_SCOPE
+    $dumpvars(1, sub_a.deep_i);
+`elsif TRACE_DUMPVARS_CASE_WIRE
+    $dumpvars(0, cyc, counter);
+`elsif TRACE_DUMPVARS_CASE_T
+    $dumpvars(t);
+`elsif TRACE_DUMPVARS_CASE_MISSING_SCOPE
+    $dumpvars(0, missing_module);
+`elsif TRACE_DUMPVARS_CASE_MISSING2
+    $dumpvars(t.missingname);
+`elsif TRACE_DUMPVARS_CASE_MISSING3
+    $dumpvars(0, t.missing);
+`elsif TRACE_DUMPVARS_CASE_MISSING4
+    $dumpvars(0, t.sub_a.missing);
+`elsif TRACE_DUMPVARS_CASE_MISSING5
+    $dumpvars(0, missing.child);
+`elsif TRACE_DUMPVARS_CASE_CPPTOP
+    $dumpvars(0, cpptop, cpptop.t);
+`elsif TRACE_DUMPVARS_CASE_CPPTOP2
+    $dumpvars(0, cpptop, cpptop.notfound);
+`elsif TRACE_DUMPVARS_CASE_CPPTOP_MISSING
+    $dumpvars(0, missing_module);
+`elsif TRACE_DUMPVARS_CASE_CPPTOP_MISSING2
+    $dumpvars(t.missingname);
+`elsif TRACE_DUMPVARS_CASE_CPPTOP_MISSING3
+    $dumpvars(0, t.missing);
+`elsif TRACE_DUMPVARS_CASE_CPPTOP_MISSING4
+    $dumpvars(0, t.sub_a.missing);
+`else
+`error "Missing trace_dumpvars case define"
+`endif
+  end
+`endif
+endmodule
+
+module sub #(
+  parameter int ADD = 0
+)(
+    input int cyc
+);
+  int value;
+  always_comb value = cyc + ADD;
+
+`ifdef TRACE_DUMPVARS_CASE_HIER_GLOBAL_TASK
+  function void dump_from_func;
+    $dumpvars(1, t);
+  endfunction
+
+  task setup_trace;
+    $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
+    dump_from_func();
+  endtask
+`endif
+
+`ifdef TRACE_DUMPVARS_ARRAY_BRANCH
+  deep #(ADD + 1) deep(.*);
+`elsif TRACE_DUMPVARS_CASE_BASE
+`elsif TRACE_DUMPVARS_CASE_WIRE
+`elsif TRACE_DUMPVARS_CASE_CPPTOP
+`elsif TRACE_DUMPVARS_CASE_CPPTOP2
+`elsif TRACE_DUMPVARS_CASE_STRUCT
+`else
+  deep #(ADD + 1) deep_i(.*);
+`endif
+
+`ifdef TRACE_DUMPVARS_CASE_HIER_GLOBAL
+  initial begin
+    $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
+    $dumpvars(1, t);
+  end
+`elsif TRACE_DUMPVARS_CASE_HIER_GLOBAL_TASK
+  initial begin
+    setup_trace();
+  end
+`elsif TRACE_DUMPVARS_CASE_TASK2
+  initial begin
+    setup_trace_nested;
+  end
+`elsif TRACE_DUMPVARS_TASK_BRANCH
+  initial begin
+    setup_trace;
+  end
+`elsif TRACE_DUMPVARS_CASE_SUB
+  initial begin
+    $dumpvars(1);
+  end
+`elsif TRACE_DUMPVARS_CASE_SUB0
+  initial begin
+    $dumpvars(0);
+  end
+`endif
+endmodule
+
+module deep #(
+  parameter int ADD = 0
+)(
+    input int cyc
+);
+  int inner;
+`ifdef TRACE_DUMPVARS_CASE_HIER_GLOBAL
+  int t;
+`elsif TRACE_DUMPVARS_CASE_HIER_GLOBAL_TASK
+  int t;
+`endif
+  always_comb inner = cyc + ADD;
+
+`ifdef TRACE_DUMPVARS_CASE_HIER_GLOBAL_TASK
+  function void dump_from_func;
+    $dumpvars(1, t);
+  endfunction
+
+  task setup_trace;
+    $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
+    dump_from_func();
+  endtask
+
+  initial begin
+    setup_trace();
+  end
+`elsif TRACE_DUMPVARS_CASE_HIER_GLOBAL
+  initial begin
+    $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
+    $dumpvars(1, t);
+  end
+`elsif TRACE_DUMPVARS_CASE_CONTEXT
+  initial begin
+    $dumpvars(0);
+  end
+`endif
+endmodule
+
+/* verilator lint_on MULTITOP */
diff --git a/test_regress/t/t_trace_dumpvars_abs_scope.out b/test_regress/t/t_trace_dumpvars_abs_scope.out
new file mode 100644
index 000000000..0a31846b7
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_abs_scope.out
@@ -0,0 +1,29 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module $rootio $end
+ $upscope $end
+ $scope module t $end
+  $scope module sub_a $end
+   $var wire 32 ( ADD [31:0] $end
+   $var wire 32 " cyc [31:0] $end
+   $var wire 32 # value [31:0] $end
+   $scope module deep_i $end
+    $var wire 32 ) ADD [31:0] $end
+    $var wire 32 " cyc [31:0] $end
+    $var wire 32 $ inner [31:0] $end
+   $upscope $end
+  $upscope $end
+  $scope module sub_b $end
+   $scope module deep_i $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 "
+b00000000000000000000000000001010 #
+b00000000000000000000000000001011 $
+b00000000000000000000000000001010 (
+b00000000000000000000000000001011 )
diff --git a/test_regress/t/t_trace_dumpvars_abs_scope.py b/test_regress/t/t_trace_dumpvars_abs_scope.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_abs_scope.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_add_module.py b/test_regress/t/t_trace_dumpvars_add_module.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_add_module.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_add_module_0.out b/test_regress/t/t_trace_dumpvars_add_module_0.out
new file mode 100644
index 000000000..7a2a58e70
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_add_module_0.out
@@ -0,0 +1,26 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module t $end
+  $scope module sub_a $end
+    $var wire 32 ( ADD [31:0] $end
+   $var wire 32 " cyc [31:0] $end
+   $var wire 32 # value [31:0] $end
+    $scope module deep_i $end
+    $upscope $end
+  $upscope $end
+  $scope module sub_b $end
+    $scope module deep_i $end
+    $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 "
+b00000000000000000000000000001010 #
+b00000000000000000000000000001010 (
+#1
+b00000000000000000000000000000001 "
+b00000000000000000000000000001011 #
+#2
diff --git a/test_regress/t/t_trace_dumpvars_add_module_1.out b/test_regress/t/t_trace_dumpvars_add_module_1.out
new file mode 100644
index 000000000..023264f2f
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_add_module_1.out
@@ -0,0 +1,53 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module t $end
+  $scope module sub_a $end
+    $var wire 32 ( ADD [31:0] $end
+   $var wire 32 " cyc [31:0] $end
+   $var wire 32 # value [31:0] $end
+    $scope module deep_i $end
+    $upscope $end
+  $upscope $end
+  $scope module sub_b $end
+    $var wire 32 * ADD [31:0] $end
+   $var wire 32 " cyc [31:0] $end
+    $var wire 32 % value [31:0] $end
+    $scope module deep_i $end
+     $var wire 32 + ADD [31:0] $end
+     $var wire 32 " cyc [31:0] $end
+     $var wire 32 & inner [31:0] $end
+    $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#3
+b00000000000000000000000000000010 "
+b00000000000000000000000000001100 #
+b00000000000000000000000000010110 %
+b00000000000000000000000000010111 &
+b00000000000000000000000000001010 (
+b00000000000000000000000000010100 *
+b00000000000000000000000000010101 +
+#5
+b00000000000000000000000000000011 "
+b00000000000000000000000000001101 #
+b00000000000000000000000000010111 %
+b00000000000000000000000000011000 &
+#7
+b00000000000000000000000000000100 "
+b00000000000000000000000000001110 #
+b00000000000000000000000000011000 %
+b00000000000000000000000000011001 &
+#9
+b00000000000000000000000000000101 "
+b00000000000000000000000000001111 #
+b00000000000000000000000000011001 %
+b00000000000000000000000000011010 &
+#11
+b00000000000000000000000000000110 "
+b00000000000000000000000000010000 #
+b00000000000000000000000000011010 %
+b00000000000000000000000000011011 &
+
diff --git a/test_regress/t/t_trace_dumpvars_context.out b/test_regress/t/t_trace_dumpvars_context.out
new file mode 100644
index 000000000..ddf8ae798
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_context.out
@@ -0,0 +1,31 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module $rootio $end
+ $upscope $end
+ $scope module t $end
+    $var wire 32 ( top [31:0] $end
+  $scope module sub_a $end
+   $scope module deep_i $end
+        $var wire 32 * ADD [31:0] $end
+    $var wire 32 " cyc [31:0] $end
+    $var wire 32 $ inner [31:0] $end
+   $upscope $end
+  $upscope $end
+  $scope module sub_b $end
+   $scope module deep_i $end
+        $var wire 32 , ADD [31:0] $end
+    $var wire 32 " cyc [31:0] $end
+    $var wire 32 & inner [31:0] $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 "
+b00000000000000000000000000001011 $
+b00000000000000000000000000010101 &
+b00000000000000000000000000000000 (
+b00000000000000000000000000001011 *
+b00000000000000000000000000010101 ,
diff --git a/test_regress/t/t_trace_dumpvars_context.py b/test_regress/t/t_trace_dumpvars_context.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_context.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_cpptop.cpp b/test_regress/t/t_trace_dumpvars_cpptop.cpp
new file mode 100644
index 000000000..83ccacb87
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_cpptop.cpp
@@ -0,0 +1,36 @@
+// -*- mode: C++; c-file-style: "cc-mode" -*-
+//
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+#include <verilated.h>
+
+#include <memory>
+
+#include VM_PREFIX_INCLUDE
+
+unsigned long long main_time = 0;
+double sc_time_stamp() { return (double)main_time; }
+
+int main(int argc, char** argv) {
+    Verilated::debug(0);
+    Verilated::traceEverOn(true);
+    Verilated::commandArgs(argc, argv);
+
+    // Name the top module "cpptop" instead of default "TOP"
+    std::unique_ptr<VM_PREFIX> top{new VM_PREFIX{"cpptop"}};
+    top->clk = 0;
+
+    while (!Verilated::gotFinish()) {
+        top->eval();
+        ++main_time;
+        top->clk = !top->clk;
+    }
+    top->final();
+    top.reset();
+    printf("*-* All Finished *-*\n");
+    return 0;
+}
diff --git a/test_regress/t/t_trace_dumpvars_cpptop.out b/test_regress/t/t_trace_dumpvars_cpptop.out
new file mode 100644
index 000000000..e80569743
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_cpptop.out
@@ -0,0 +1,69 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module cpptop $end
+  $var wire 1 % clk $end
+  $scope module t $end
+   $var wire 1 % clk $end
+   $var wire 32 " cyc [31:0] $end
+   $scope module sub_a $end
+    $var wire 32 & ADD [31:0] $end
+    $var wire 32 " cyc [31:0] $end
+    $var wire 32 # value [31:0] $end
+   $upscope $end
+   $scope module sub_b $end
+    $var wire 32 ' ADD [31:0] $end
+    $var wire 32 " cyc [31:0] $end
+    $var wire 32 $ value [31:0] $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 "
+b00000000000000000000000000001010 #
+b00000000000000000000000000010100 $
+0%
+b00000000000000000000000000001010 &
+b00000000000000000000000000010100 '
+#1
+b00000000000000000000000000000001 "
+b00000000000000000000000000001011 #
+b00000000000000000000000000010101 $
+1%
+#2
+0%
+#3
+b00000000000000000000000000000010 "
+b00000000000000000000000000001100 #
+b00000000000000000000000000010110 $
+1%
+#4
+0%
+#5
+b00000000000000000000000000000011 "
+b00000000000000000000000000001101 #
+b00000000000000000000000000010111 $
+1%
+#6
+0%
+#7
+b00000000000000000000000000000100 "
+b00000000000000000000000000001110 #
+b00000000000000000000000000011000 $
+1%
+#8
+0%
+#9
+b00000000000000000000000000000101 "
+b00000000000000000000000000001111 #
+b00000000000000000000000000011001 $
+1%
+#10
+0%
+#11
+b00000000000000000000000000000110 "
+b00000000000000000000000000010000 #
+b00000000000000000000000000011010 $
+1%
diff --git a/test_regress/t/t_trace_dumpvars_cpptop.py b/test_regress/t/t_trace_dumpvars_cpptop.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_cpptop.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_cpptop2.out b/test_regress/t/t_trace_dumpvars_cpptop2.out
new file mode 100644
index 000000000..a585565b4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_cpptop2.out
@@ -0,0 +1,5 @@
+%Error: t/t_trace_dumpvars.v:272:5: $dumpvars target not found: cpptop.notfound
+  272 |     $dumpvars(0, cpptop, cpptop.notfound);
+      |     ^~~~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: Exiting due to
diff --git a/test_regress/t/t_trace_dumpvars_cpptop2.py b/test_regress/t/t_trace_dumpvars_cpptop2.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_cpptop2.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_array.out b/test_regress/t/t_trace_dumpvars_cpptop_hier_array.out
new file mode 100644
index 000000000..77cfcfdfa
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_array.out
@@ -0,0 +1,42 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module cpptop $end
+  $scope module t $end
+   $scope module arr[0] $end
+    $scope module deep $end
+    $upscope $end
+   $upscope $end
+   $scope module arr[1] $end
+    $scope module deep $end
+     $var wire 32 ' ADD [31:0] $end
+     $var wire 32 " cyc [31:0] $end
+     $var wire 32 $ inner [31:0] $end
+    $upscope $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 "
+b00000000000000000000000000001011 $
+b00000000000000000000000000001011 '
+#1
+b00000000000000000000000000000001 "
+b00000000000000000000000000001100 $
+#3
+b00000000000000000000000000000010 "
+b00000000000000000000000000001101 $
+#5
+b00000000000000000000000000000011 "
+b00000000000000000000000000001110 $
+#7
+b00000000000000000000000000000100 "
+b00000000000000000000000000001111 $
+#9
+b00000000000000000000000000000101 "
+b00000000000000000000000000010000 $
+#11
+b00000000000000000000000000000110 "
+b00000000000000000000000000010001 $
diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_array.py b/test_regress/t/t_trace_dumpvars_cpptop_hier_array.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_array.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.out b/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.out
new file mode 100644
index 000000000..d8b0895ae
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.out
@@ -0,0 +1,18 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module cpptop $end
+  $scope module t $end
+   $scope module arr[0] $end
+    $scope module deep $end
+    $upscope $end
+   $upscope $end
+   $scope module arr[1] $end
+    $scope module deep $end
+    $upscope $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#11
diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.py b/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_array_oob.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_global.py b/test_regress/t/t_trace_dumpvars_cpptop_hier_global.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_global.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.out b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.out
new file mode 100644
index 000000000..b65b71fa9
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.out
@@ -0,0 +1,38 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module cpptop $end
+  $scope module t $end
+   $scope module mystruct $end
+    $scope module deep $end
+     $var wire 32 ' add [31:0] $end
+     $var wire 32 # cyc [31:0] $end
+     $var wire 32 $ inner [31:0] $end
+    $upscope $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 #
+b00000000000000000000000000001011 $
+b00000000000000000000000000001011 '
+#1
+b00000000000000000000000000000001 #
+b00000000000000000000000000001100 $
+#3
+b00000000000000000000000000000010 #
+b00000000000000000000000000001101 $
+#5
+b00000000000000000000000000000011 #
+b00000000000000000000000000001110 $
+#7
+b00000000000000000000000000000100 #
+b00000000000000000000000000001111 $
+#9
+b00000000000000000000000000000101 #
+b00000000000000000000000000010000 $
+#11
+b00000000000000000000000000000110 #
+b00000000000000000000000000010001 $
diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.py b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.py b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_cpptop_hier_struct2.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing.out b/test_regress/t/t_trace_dumpvars_cpptop_missing.out
new file mode 100644
index 000000000..def8decb6
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_cpptop_missing.out
@@ -0,0 +1,2 @@
+%Error: t/t_trace_dumpvars.v:274: $dumpvars target not found: missing_module
+Aborting...
diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing.py b/test_regress/t/t_trace_dumpvars_cpptop_missing.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_cpptop_missing.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing2.out b/test_regress/t/t_trace_dumpvars_cpptop_missing2.out
new file mode 100644
index 000000000..a1a1a3e13
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_cpptop_missing2.out
@@ -0,0 +1,5 @@
+%Error: t/t_trace_dumpvars.v:276:17: Can't find definition of 'missingname' in dotted variable/method: 't.missingname'
+  276 |     $dumpvars(t.missingname);
+      |                 ^~~~~~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: Exiting due to
diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing2.py b/test_regress/t/t_trace_dumpvars_cpptop_missing2.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_cpptop_missing2.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing3.out b/test_regress/t/t_trace_dumpvars_cpptop_missing3.out
new file mode 100644
index 000000000..9f778c04b
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_cpptop_missing3.out
@@ -0,0 +1,2 @@
+%Error: t/t_trace_dumpvars.v:278: $dumpvars target not found: t.missing
+Aborting...
diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing3.py b/test_regress/t/t_trace_dumpvars_cpptop_missing3.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_cpptop_missing3.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing4.out b/test_regress/t/t_trace_dumpvars_cpptop_missing4.out
new file mode 100644
index 000000000..cf0802e31
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_cpptop_missing4.out
@@ -0,0 +1,2 @@
+%Error: t/t_trace_dumpvars.v:280: $dumpvars target not found: t.sub_a.missing
+Aborting...
diff --git a/test_regress/t/t_trace_dumpvars_cpptop_missing4.py b/test_regress/t/t_trace_dumpvars_cpptop_missing4.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_cpptop_missing4.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_func.out b/test_regress/t/t_trace_dumpvars_func.out
new file mode 100644
index 000000000..73b55a8a8
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_func.out
@@ -0,0 +1,29 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module $rootio $end
+ $upscope $end
+ $scope module t $end
+  $scope module sub_a $end
+   $var wire 32 ( ADD [31:0] $end
+   $var wire 32 " cyc [31:0] $end
+   $var wire 32 # value [31:0] $end
+   $scope module deep_i $end
+   $upscope $end
+  $upscope $end
+  $scope module sub_b $end
+   $var wire 32 * ADD [31:0] $end
+   $var wire 32 " cyc [31:0] $end
+   $var wire 32 % value [31:0] $end
+   $scope module deep_i $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 "
+b00000000000000000000000000001010 #
+b00000000000000000000000000010100 %
+b00000000000000000000000000001010 (
+b00000000000000000000000000010100 *
diff --git a/test_regress/t/t_trace_dumpvars_func.py b/test_regress/t/t_trace_dumpvars_func.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_func.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_gen.out b/test_regress/t/t_trace_dumpvars_gen.out
new file mode 100644
index 000000000..92d14f65f
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_gen.out
@@ -0,0 +1,33 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module $rootio $end
+ $upscope $end
+ $scope module t $end
+  $scope module gen_sub[0] $end
+   $scope module sub_i $end
+    $var wire 32 ( ADD [31:0] $end
+    $var wire 32 " cyc [31:0] $end
+    $var wire 32 # value [31:0] $end
+    $scope module deep_i $end
+     $var wire 32 ) ADD [31:0] $end
+     $var wire 32 " cyc [31:0] $end
+     $var wire 32 $ inner [31:0] $end
+    $upscope $end
+   $upscope $end
+  $upscope $end
+  $scope module gen_sub[1] $end
+   $scope module sub_i $end
+    $scope module deep_i $end
+    $upscope $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 "
+b00000000000000000000000000001010 #
+b00000000000000000000000000001011 $
+b00000000000000000000000000001010 (
+b00000000000000000000000000001011 )
diff --git a/test_regress/t/t_trace_dumpvars_gen.py b/test_regress/t/t_trace_dumpvars_gen.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_gen.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_hier_array.out b/test_regress/t/t_trace_dumpvars_hier_array.out
new file mode 100644
index 000000000..f05e7add6
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_hier_array.out
@@ -0,0 +1,24 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module $rootio $end
+ $upscope $end
+ $scope module t $end
+  $scope module arr[0] $end
+   $scope module deep $end
+   $upscope $end
+  $upscope $end
+  $scope module arr[1] $end
+   $scope module deep $end
+    $var wire 32 ' ADD [31:0] $end
+    $var wire 32 " cyc [31:0] $end
+    $var wire 32 $ inner [31:0] $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 "
+b00000000000000000000000000001011 $
+b00000000000000000000000000001011 '
diff --git a/test_regress/t/t_trace_dumpvars_hier_array.py b/test_regress/t/t_trace_dumpvars_hier_array.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_hier_array.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_hier_array_oob.py b/test_regress/t/t_trace_dumpvars_hier_array_oob.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_hier_array_oob.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_hier_global.out b/test_regress/t/t_trace_dumpvars_hier_global.out
new file mode 100644
index 000000000..546cc253e
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_hier_global.out
@@ -0,0 +1,26 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module $rootio $end
+ $upscope $end
+ $scope module t $end
+    $var wire 1 ' clk $end
+    $var wire 32 " cyc [31:0] $end
+  $scope module sub_a $end
+   $scope module deep_i $end
+        $var wire 32 * t [31:0] $end
+   $upscope $end
+  $upscope $end
+  $scope module sub_b $end
+   $scope module deep_i $end
+        $var wire 32 - t [31:0] $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 "
+0'
+b00000000000000000000000000000000 *
+b00000000000000000000000000000000 -
diff --git a/test_regress/t/t_trace_dumpvars_hier_global.py b/test_regress/t/t_trace_dumpvars_hier_global.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_hier_global.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_hier_global_task.out b/test_regress/t/t_trace_dumpvars_hier_global_task.out
new file mode 100644
index 000000000..934e212b9
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_hier_global_task.out
@@ -0,0 +1,26 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module $rootio $end
+ $upscope $end
+ $scope module t $end
+  $var wire 1 ' clk $end
+  $var wire 32 " cyc [31:0] $end
+  $scope module sub_a $end
+   $scope module deep_i $end
+    $var wire 32 * t [31:0] $end
+   $upscope $end
+  $upscope $end
+  $scope module sub_b $end
+   $scope module deep_i $end
+    $var wire 32 - t [31:0] $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 "
+0'
+b00000000000000000000000000000000 *
+b00000000000000000000000000000000 -
diff --git a/test_regress/t/t_trace_dumpvars_hier_global_task.py b/test_regress/t/t_trace_dumpvars_hier_global_task.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_hier_global_task.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_hier_scope.out b/test_regress/t/t_trace_dumpvars_hier_scope.out
new file mode 100644
index 000000000..033f569da
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_hier_scope.out
@@ -0,0 +1,24 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module $rootio $end
+ $upscope $end
+ $scope module t $end
+  $scope module sub_a $end
+   $scope module deep_i $end
+    $var wire 32 ) ADD [31:0] $end
+    $var wire 32 " cyc [31:0] $end
+    $var wire 32 $ inner [31:0] $end
+   $upscope $end
+  $upscope $end
+  $scope module sub_b $end
+   $scope module deep_i $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 "
+b00000000000000000000000000001011 $
+b00000000000000000000000000001011 )
diff --git a/test_regress/t/t_trace_dumpvars_hier_scope.py b/test_regress/t/t_trace_dumpvars_hier_scope.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_hier_scope.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_hier_struct.out b/test_regress/t/t_trace_dumpvars_hier_struct.out
new file mode 100644
index 000000000..40ed30d89
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_hier_struct.out
@@ -0,0 +1,20 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module $rootio $end
+ $upscope $end
+ $scope module t $end
+    $scope module mystruct $end
+   $scope module deep $end
+    $var wire 32 ' add [31:0] $end
+    $var wire 32 # cyc [31:0] $end
+    $var wire 32 $ inner [31:0] $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 #
+b00000000000000000000000000001011 $
+b00000000000000000000000000001011 '
diff --git a/test_regress/t/t_trace_dumpvars_hier_struct.py b/test_regress/t/t_trace_dumpvars_hier_struct.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_hier_struct.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_level.out b/test_regress/t/t_trace_dumpvars_level.out
new file mode 100644
index 000000000..b64676095
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_level.out
@@ -0,0 +1,22 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module $rootio $end
+ $upscope $end
+ $scope module t $end
+  $var wire 1 ' clk $end
+  $var wire 32 " cyc [31:0] $end
+  $scope module sub_a $end
+   $scope module deep_i $end
+   $upscope $end
+  $upscope $end
+  $scope module sub_b $end
+   $scope module deep_i $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 "
+0'
diff --git a/test_regress/t/t_trace_dumpvars_level.py b/test_regress/t/t_trace_dumpvars_level.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_level.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_level_scope.out b/test_regress/t/t_trace_dumpvars_level_scope.out
new file mode 100644
index 000000000..f2b9e53a4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_level_scope.out
@@ -0,0 +1,24 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module $rootio $end
+ $upscope $end
+ $scope module t $end
+  $scope module sub_a $end
+   $var wire 32 ( ADD [31:0] $end
+   $var wire 32 " cyc [31:0] $end
+   $var wire 32 # value [31:0] $end
+   $scope module deep_i $end
+   $upscope $end
+  $upscope $end
+  $scope module sub_b $end
+   $scope module deep_i $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 "
+b00000000000000000000000000001010 #
+b00000000000000000000000000001010 (
diff --git a/test_regress/t/t_trace_dumpvars_level_scope.py b/test_regress/t/t_trace_dumpvars_level_scope.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_level_scope.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_level_scope_fst.out b/test_regress/t/t_trace_dumpvars_level_scope_fst.out
new file mode 100644
index 000000000..f74d6bd3e
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_level_scope_fst.out
@@ -0,0 +1,31 @@
+$date
+Tue Mar 24 23:18:44 2026
+
+$end
+$version
+Generated by VerilatedFst
+$end
+$timescale
+1ps
+$end
+ $scope module $rootio $end
+ $upscope $end
+ $scope module t $end
+  $scope module sub_a $end
+   $var parameter 32 ! ADD [31:0] $end
+   $var wire 32 " cyc [31:0] $end
+   $var int 32 # value [31:0] $end
+   $scope module deep_i $end
+   $upscope $end
+  $upscope $end
+  $scope module sub_b $end
+   $scope module deep_i $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b00000000000000000000000000001010 #
+b00000000000000000000000000000000 "
+b00000000000000000000000000001010 !
diff --git a/test_regress/t/t_trace_dumpvars_level_scope_fst.py b/test_regress/t/t_trace_dumpvars_level_scope_fst.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_level_scope_fst.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_level_scope_saif.out b/test_regress/t/t_trace_dumpvars_level_scope_saif.out
new file mode 100644
index 000000000..c7d8c321b
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_level_scope_saif.out
@@ -0,0 +1,119 @@
+// Generated by verilated_saif
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(PROGRAM_NAME "Verilator")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 0)
+ (INSTANCE $rootio
+ )
+ (INSTANCE t
+  (INSTANCE sub_a
+   (NET
+    (ADD\[0\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ADD\[1\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (ADD\[2\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ADD\[3\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (ADD\[4\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ADD\[5\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ADD\[6\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ADD\[7\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ADD\[8\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ADD\[9\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ADD\[10\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ADD\[11\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ADD\[12\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ADD\[13\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ADD\[14\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ADD\[15\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ADD\[16\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ADD\[17\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ADD\[18\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ADD\[19\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ADD\[20\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ADD\[21\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ADD\[22\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ADD\[23\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ADD\[24\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ADD\[25\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ADD\[26\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ADD\[27\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ADD\[28\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ADD\[29\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ADD\[30\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (ADD\[31\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[0\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[1\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[2\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[3\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[4\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[5\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[6\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[7\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[8\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[9\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[10\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[11\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[12\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[13\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[14\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[15\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[16\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[17\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[18\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[19\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[20\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[21\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[22\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[23\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[24\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[25\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[26\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[27\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[28\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[29\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[30\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (cyc\[31\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (value\[0\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (value\[1\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (value\[2\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (value\[3\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1))
+    (value\[4\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (value\[5\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (value\[6\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (value\[7\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (value\[8\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (value\[9\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (value\[10\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (value\[11\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (value\[12\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (value\[13\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (value\[14\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (value\[15\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (value\[16\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (value\[17\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (value\[18\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (value\[19\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (value\[20\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (value\[21\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (value\[22\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (value\[23\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (value\[24\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (value\[25\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (value\[26\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (value\[27\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (value\[28\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (value\[29\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (value\[30\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+    (value\[31\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0))
+   )
+   (INSTANCE deep_i
+   )
+  )
+  (INSTANCE sub_b
+   (INSTANCE deep_i
+   )
+  )
+ )
+)
diff --git a/test_regress/t/t_trace_dumpvars_level_scope_saif.py b/test_regress/t/t_trace_dumpvars_level_scope_saif.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_level_scope_saif.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_missing2.out b/test_regress/t/t_trace_dumpvars_missing2.out
new file mode 100644
index 000000000..34d4cf6c8
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_missing2.out
@@ -0,0 +1,5 @@
+%Error: t/t_trace_dumpvars.v:262:17: Can't find definition of 'missingname' in dotted variable/method: 't.missingname'
+  262 |     $dumpvars(t.missingname);
+      |                 ^~~~~~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: Exiting due to
diff --git a/test_regress/t/t_trace_dumpvars_missing2.py b/test_regress/t/t_trace_dumpvars_missing2.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_missing2.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_missing3.out b/test_regress/t/t_trace_dumpvars_missing3.out
new file mode 100644
index 000000000..ff13ccdd2
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_missing3.out
@@ -0,0 +1,5 @@
+%Error: t/t_trace_dumpvars.v:264:5: $dumpvars target not found: t.missing
+  264 |     $dumpvars(0, t.missing);
+      |     ^~~~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: Exiting due to
diff --git a/test_regress/t/t_trace_dumpvars_missing3.py b/test_regress/t/t_trace_dumpvars_missing3.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_missing3.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_missing4.out b/test_regress/t/t_trace_dumpvars_missing4.out
new file mode 100644
index 000000000..692c591c2
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_missing4.out
@@ -0,0 +1,5 @@
+%Error: t/t_trace_dumpvars.v:266:5: $dumpvars target not found: t.sub_a.missing
+  266 |     $dumpvars(0, t.sub_a.missing);
+      |     ^~~~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: Exiting due to
diff --git a/test_regress/t/t_trace_dumpvars_missing4.py b/test_regress/t/t_trace_dumpvars_missing4.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_missing4.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_missing5.out b/test_regress/t/t_trace_dumpvars_missing5.out
new file mode 100644
index 000000000..1301b5faf
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_missing5.out
@@ -0,0 +1,5 @@
+%Error: t/t_trace_dumpvars.v:268:5: $dumpvars target not found: missing.child
+  268 |     $dumpvars(0, missing.child);
+      |     ^~~~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: Exiting due to
diff --git a/test_regress/t/t_trace_dumpvars_missing5.py b/test_regress/t/t_trace_dumpvars_missing5.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_missing5.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_missing_scope.out b/test_regress/t/t_trace_dumpvars_missing_scope.out
new file mode 100644
index 000000000..dfaa1f61a
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_missing_scope.out
@@ -0,0 +1,5 @@
+%Error: t/t_trace_dumpvars.v:260:5: $dumpvars target not found: missing_module
+  260 |     $dumpvars(0, missing_module);
+      |     ^~~~~~~~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: Exiting due to
diff --git a/test_regress/t/t_trace_dumpvars_missing_scope.py b/test_regress/t/t_trace_dumpvars_missing_scope.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_missing_scope.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_multi_scope.out b/test_regress/t/t_trace_dumpvars_multi_scope.out
new file mode 100644
index 000000000..1fc4774b1
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_multi_scope.out
@@ -0,0 +1,27 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module $rootio $end
+ $upscope $end
+ $scope module t $end
+  $var wire 1 ' clk $end
+  $var wire 32 " cyc [31:0] $end
+  $scope module sub_a $end
+   $scope module deep_i $end
+    $var wire 32 ) ADD [31:0] $end
+    $var wire 32 " cyc [31:0] $end
+    $var wire 32 $ inner [31:0] $end
+   $upscope $end
+  $upscope $end
+  $scope module sub_b $end
+   $scope module deep_i $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 "
+b00000000000000000000000000001011 $
+0'
+b00000000000000000000000000001011 )
diff --git a/test_regress/t/t_trace_dumpvars_multi_scope.py b/test_regress/t/t_trace_dumpvars_multi_scope.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_multi_scope.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_nonconst_scope.out b/test_regress/t/t_trace_dumpvars_nonconst_scope.out
new file mode 100644
index 000000000..b1f35509d
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_nonconst_scope.out
@@ -0,0 +1,31 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module $rootio $end
+ $upscope $end
+ $scope module t $end
+  $scope module dumpblock $end
+  $upscope $end
+  $scope module sub_a $end
+   $var wire 32 ) ADD [31:0] $end
+   $var wire 32 # cyc [31:0] $end
+   $var wire 32 $ value [31:0] $end
+   $scope module deep_i $end
+    $var wire 32 * ADD [31:0] $end
+    $var wire 32 # cyc [31:0] $end
+    $var wire 32 % inner [31:0] $end
+   $upscope $end
+  $upscope $end
+  $scope module sub_b $end
+   $scope module deep_i $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 #
+b00000000000000000000000000001010 $
+b00000000000000000000000000001011 %
+b00000000000000000000000000001010 )
+b00000000000000000000000000001011 *
diff --git a/test_regress/t/t_trace_dumpvars_nonconst_scope.py b/test_regress/t/t_trace_dumpvars_nonconst_scope.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_nonconst_scope.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_override.out b/test_regress/t/t_trace_dumpvars_override.out
new file mode 100644
index 000000000..cc85ab270
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_override.out
@@ -0,0 +1,43 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module $rootio $end
+    $var wire 1 ' clk $end
+ $upscope $end
+ $scope module t $end
+  $var wire 1 ' clk $end
+  $var wire 32 " cyc [31:0] $end
+  $scope module sub_a $end
+   $var wire 32 ( ADD [31:0] $end
+   $var wire 32 " cyc [31:0] $end
+   $var wire 32 # value [31:0] $end
+   $scope module deep_i $end
+    $var wire 32 ) ADD [31:0] $end
+    $var wire 32 " cyc [31:0] $end
+    $var wire 32 $ inner [31:0] $end
+   $upscope $end
+  $upscope $end
+  $scope module sub_b $end
+   $var wire 32 * ADD [31:0] $end
+   $var wire 32 " cyc [31:0] $end
+   $var wire 32 % value [31:0] $end
+   $scope module deep_i $end
+    $var wire 32 + ADD [31:0] $end
+    $var wire 32 " cyc [31:0] $end
+    $var wire 32 & inner [31:0] $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 "
+b00000000000000000000000000001010 #
+b00000000000000000000000000001011 $
+b00000000000000000000000000010100 %
+b00000000000000000000000000010101 &
+0'
+b00000000000000000000000000001010 (
+b00000000000000000000000000001011 )
+b00000000000000000000000000010100 *
+b00000000000000000000000000010101 +
diff --git a/test_regress/t/t_trace_dumpvars_override.py b/test_regress/t/t_trace_dumpvars_override.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_override.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_scope.out b/test_regress/t/t_trace_dumpvars_scope.out
new file mode 100644
index 000000000..0a31846b7
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_scope.out
@@ -0,0 +1,29 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module $rootio $end
+ $upscope $end
+ $scope module t $end
+  $scope module sub_a $end
+   $var wire 32 ( ADD [31:0] $end
+   $var wire 32 " cyc [31:0] $end
+   $var wire 32 # value [31:0] $end
+   $scope module deep_i $end
+    $var wire 32 ) ADD [31:0] $end
+    $var wire 32 " cyc [31:0] $end
+    $var wire 32 $ inner [31:0] $end
+   $upscope $end
+  $upscope $end
+  $scope module sub_b $end
+   $scope module deep_i $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 "
+b00000000000000000000000000001010 #
+b00000000000000000000000000001011 $
+b00000000000000000000000000001010 (
+b00000000000000000000000000001011 )
diff --git a/test_regress/t/t_trace_dumpvars_scope.py b/test_regress/t/t_trace_dumpvars_scope.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_scope.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_struct.out b/test_regress/t/t_trace_dumpvars_struct.out
new file mode 100644
index 000000000..0c114640d
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_struct.out
@@ -0,0 +1,24 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module $rootio $end
+ $upscope $end
+ $scope module t $end
+  $scope module rect $end
+   $scope module origin $end
+    $var wire 8 # x [7:0] $end
+   $upscope $end
+   $scope module size $end
+   $upscope $end
+  $upscope $end
+  $scope module pt $end
+        $var wire 8 ( y [7:0] $end
+  $upscope $end
+  $scope module sub_a $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000 #
+b00000000 (
diff --git a/test_regress/t/t_trace_dumpvars_struct.py b/test_regress/t/t_trace_dumpvars_struct.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_struct.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_sub.out b/test_regress/t/t_trace_dumpvars_sub.out
new file mode 100644
index 000000000..73b55a8a8
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_sub.out
@@ -0,0 +1,29 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module $rootio $end
+ $upscope $end
+ $scope module t $end
+  $scope module sub_a $end
+   $var wire 32 ( ADD [31:0] $end
+   $var wire 32 " cyc [31:0] $end
+   $var wire 32 # value [31:0] $end
+   $scope module deep_i $end
+   $upscope $end
+  $upscope $end
+  $scope module sub_b $end
+   $var wire 32 * ADD [31:0] $end
+   $var wire 32 " cyc [31:0] $end
+   $var wire 32 % value [31:0] $end
+   $scope module deep_i $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 "
+b00000000000000000000000000001010 #
+b00000000000000000000000000010100 %
+b00000000000000000000000000001010 (
+b00000000000000000000000000010100 *
diff --git a/test_regress/t/t_trace_dumpvars_sub.py b/test_regress/t/t_trace_dumpvars_sub.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_sub.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_sub0.out b/test_regress/t/t_trace_dumpvars_sub0.out
new file mode 100644
index 000000000..7418ac167
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_sub0.out
@@ -0,0 +1,39 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module $rootio $end
+ $upscope $end
+ $scope module t $end
+  $scope module sub_a $end
+   $var wire 32 ( ADD [31:0] $end
+   $var wire 32 " cyc [31:0] $end
+   $var wire 32 # value [31:0] $end
+   $scope module deep_i $end
+    $var wire 32 ) ADD [31:0] $end
+    $var wire 32 " cyc [31:0] $end
+    $var wire 32 $ inner [31:0] $end
+   $upscope $end
+  $upscope $end
+  $scope module sub_b $end
+   $var wire 32 * ADD [31:0] $end
+   $var wire 32 " cyc [31:0] $end
+   $var wire 32 % value [31:0] $end
+   $scope module deep_i $end
+    $var wire 32 + ADD [31:0] $end
+    $var wire 32 " cyc [31:0] $end
+    $var wire 32 & inner [31:0] $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 "
+b00000000000000000000000000001010 #
+b00000000000000000000000000001011 $
+b00000000000000000000000000010100 %
+b00000000000000000000000000010101 &
+b00000000000000000000000000001010 (
+b00000000000000000000000000001011 )
+b00000000000000000000000000010100 *
+b00000000000000000000000000010101 +
diff --git a/test_regress/t/t_trace_dumpvars_sub0.py b/test_regress/t/t_trace_dumpvars_sub0.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_sub0.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_t.out b/test_regress/t/t_trace_dumpvars_t.out
new file mode 100644
index 000000000..564660194
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_t.out
@@ -0,0 +1,5 @@
+%Error: t/t_trace_dumpvars.v:258:15: Can't find definition of variable: 't'
+  258 |     $dumpvars(t);
+      |               ^
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: Exiting due to
diff --git a/test_regress/t/t_trace_dumpvars_t.py b/test_regress/t/t_trace_dumpvars_t.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_t.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_task.out b/test_regress/t/t_trace_dumpvars_task.out
new file mode 100644
index 000000000..73b55a8a8
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_task.out
@@ -0,0 +1,29 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module $rootio $end
+ $upscope $end
+ $scope module t $end
+  $scope module sub_a $end
+   $var wire 32 ( ADD [31:0] $end
+   $var wire 32 " cyc [31:0] $end
+   $var wire 32 # value [31:0] $end
+   $scope module deep_i $end
+   $upscope $end
+  $upscope $end
+  $scope module sub_b $end
+   $var wire 32 * ADD [31:0] $end
+   $var wire 32 " cyc [31:0] $end
+   $var wire 32 % value [31:0] $end
+   $scope module deep_i $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 "
+b00000000000000000000000000001010 #
+b00000000000000000000000000010100 %
+b00000000000000000000000000001010 (
+b00000000000000000000000000010100 *
diff --git a/test_regress/t/t_trace_dumpvars_task.py b/test_regress/t/t_trace_dumpvars_task.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_task.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_task2.out b/test_regress/t/t_trace_dumpvars_task2.out
new file mode 100644
index 000000000..73b55a8a8
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_task2.out
@@ -0,0 +1,29 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module $rootio $end
+ $upscope $end
+ $scope module t $end
+  $scope module sub_a $end
+   $var wire 32 ( ADD [31:0] $end
+   $var wire 32 " cyc [31:0] $end
+   $var wire 32 # value [31:0] $end
+   $scope module deep_i $end
+   $upscope $end
+  $upscope $end
+  $scope module sub_b $end
+   $var wire 32 * ADD [31:0] $end
+   $var wire 32 " cyc [31:0] $end
+   $var wire 32 % value [31:0] $end
+   $scope module deep_i $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 "
+b00000000000000000000000000001010 #
+b00000000000000000000000000010100 %
+b00000000000000000000000000001010 (
+b00000000000000000000000000010100 *
diff --git a/test_regress/t/t_trace_dumpvars_task2.py b/test_regress/t/t_trace_dumpvars_task2.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_task2.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_task2_no_inl.out b/test_regress/t/t_trace_dumpvars_task2_no_inl.out
new file mode 100644
index 000000000..73b55a8a8
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_task2_no_inl.out
@@ -0,0 +1,29 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module $rootio $end
+ $upscope $end
+ $scope module t $end
+  $scope module sub_a $end
+   $var wire 32 ( ADD [31:0] $end
+   $var wire 32 " cyc [31:0] $end
+   $var wire 32 # value [31:0] $end
+   $scope module deep_i $end
+   $upscope $end
+  $upscope $end
+  $scope module sub_b $end
+   $var wire 32 * ADD [31:0] $end
+   $var wire 32 " cyc [31:0] $end
+   $var wire 32 % value [31:0] $end
+   $scope module deep_i $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 "
+b00000000000000000000000000001010 #
+b00000000000000000000000000010100 %
+b00000000000000000000000000001010 (
+b00000000000000000000000000010100 *
diff --git a/test_regress/t/t_trace_dumpvars_task2_no_inl.py b/test_regress/t/t_trace_dumpvars_task2_no_inl.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_task2_no_inl.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_task_no_inl.out b/test_regress/t/t_trace_dumpvars_task_no_inl.out
new file mode 100644
index 000000000..73b55a8a8
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_task_no_inl.out
@@ -0,0 +1,29 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module $rootio $end
+ $upscope $end
+ $scope module t $end
+  $scope module sub_a $end
+   $var wire 32 ( ADD [31:0] $end
+   $var wire 32 " cyc [31:0] $end
+   $var wire 32 # value [31:0] $end
+   $scope module deep_i $end
+   $upscope $end
+  $upscope $end
+  $scope module sub_b $end
+   $var wire 32 * ADD [31:0] $end
+   $var wire 32 " cyc [31:0] $end
+   $var wire 32 % value [31:0] $end
+   $scope module deep_i $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 "
+b00000000000000000000000000001010 #
+b00000000000000000000000000010100 %
+b00000000000000000000000000001010 (
+b00000000000000000000000000010100 *
diff --git a/test_regress/t/t_trace_dumpvars_task_no_inl.py b/test_regress/t/t_trace_dumpvars_task_no_inl.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_task_no_inl.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_top.out b/test_regress/t/t_trace_dumpvars_top.out
new file mode 100644
index 000000000..e69de29bb
diff --git a/test_regress/t/t_trace_dumpvars_top.py b/test_regress/t/t_trace_dumpvars_top.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_top.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_dumpvars_wire.out b/test_regress/t/t_trace_dumpvars_wire.out
new file mode 100644
index 000000000..d10cfb434
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_wire.out
@@ -0,0 +1,18 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module $rootio $end
+ $upscope $end
+ $scope module t $end
+  $var wire 32 " cyc [31:0] $end
+  $var wire 32 # counter [31:0] $end
+  $scope module sub_a $end
+  $upscope $end
+  $scope module sub_b $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 "
+b00000000000000000000000000000000 #
diff --git a/test_regress/t/t_trace_dumpvars_wire.py b/test_regress/t/t_trace_dumpvars_wire.py
new file mode 100644
index 000000000..96746adc4
--- /dev/null
+++ b/test_regress/t/t_trace_dumpvars_wire.py
@@ -0,0 +1,15 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+import trace_dumpvars_common
+
+test.scenarios('vlt')
+
+trace_dumpvars_common.run(test)
diff --git a/test_regress/t/t_trace_event.v b/test_regress/t/t_trace_event.v
index 4837399a8..925e68f7f 100644
--- a/test_regress/t/t_trace_event.v
+++ b/test_regress/t/t_trace_event.v
@@ -26,7 +26,7 @@ module t;
 
   initial begin
     $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
-    $dumpvars(0, top);
+    $dumpvars(0);
     for (i = 0; i < 10; i++) begin
       @(posedge clk);
 
diff --git a/test_regress/t/t_trace_two_a.v b/test_regress/t/t_trace_two_a.v
index f27143641..ad2ecd3a1 100644
--- a/test_regress/t/t_trace_two_a.v
+++ b/test_regress/t/t_trace_two_a.v
@@ -26,9 +26,9 @@ module t (
 
 `ifdef TEST_DUMP
     $dumpfile(filename);
-    $dumpvars(0);  // Intentionally no ", top" for parsing coverage with just (expr)
-    $dumpvars(1, top);  // Intentionally checking parsing coverage
-    $dumpvars(1, top, top);  // Intentionally checking parsing coverage
+    $dumpvars(0);  // Intentionally no ", topa" for parsing coverage with just (expr)
+    $dumpvars(1, topa);  // Intentionally checking parsing coverage
+    $dumpvars(1, topa, topa);  // Intentionally checking parsing coverage
     $dumplimit(10 * 1024 * 1024);
 `elsif TEST_DUMPPORTS
     $dumpports(top, filename);
diff --git a/test_regress/t/trace_dumpvars_common.py b/test_regress/t/trace_dumpvars_common.py
new file mode 100644
index 000000000..fe4bf2587
--- /dev/null
+++ b/test_regress/t/trace_dumpvars_common.py
@@ -0,0 +1,167 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 by Wilson Snyder.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import os
+import re
+
+
+_SHARED_TOP = "t/t_trace_dumpvars.v"
+_SHARED_CPPTOP = "t/t_trace_dumpvars_cpptop.cpp"
+
+_COMPILE_FAIL_CASES = {
+    "cpptop2",
+    "cpptop_missing2",
+    "missing_scope",
+    "missing2",
+    "missing3",
+    "missing4",
+    "missing5",
+    "t",
+}
+
+_EXECUTE_FAIL_CASES = {
+    "cpptop_missing",
+    "cpptop_missing3",
+    "cpptop_missing4",
+}
+
+_CPPTOP_CASES = {
+    "cpptop",
+    "cpptop2",
+    "cpptop_hier_array",
+    "cpptop_hier_array_oob",
+    "cpptop_hier_global",
+    "cpptop_hier_struct",
+    "cpptop_hier_struct2",
+    "cpptop_missing",
+    "cpptop_missing2",
+    "cpptop_missing3",
+    "cpptop_missing4",
+}
+
+_STRUCT_TRACE_CASES = {
+    "struct",
+    "hier_struct",
+    "cpptop_hier_struct",
+    "cpptop_hier_struct2",
+}
+
+_NO_INLINE_CASES = {
+    "hier_global_task",
+    "task_no_inl",
+    "task2_no_inl",
+}
+
+_FILE_COMPARE_CASES = {
+    "cpptop_hier_array_oob",
+}
+
+_DEFINE_ALIASES = {
+    "cpptop_hier_global": "hier_global",
+    "task_no_inl": "task",
+    "task2_no_inl": "task2",
+}
+
+_ALT_TRACE_FORMATS = {"fst", "saif"}
+
+
+def _split_format(case):
+    """Split case into (base_case, trace_format)."""
+    for fmt in _ALT_TRACE_FORMATS:
+        if case.endswith("_" + fmt):
+            return case[:-(len(fmt) + 1)], fmt
+    return case, "vcd"
+
+
+def _case_name(test):
+    name = os.path.splitext(os.path.basename(test.py_filename))[0]
+    prefix = "t_trace_dumpvars"
+    if name == prefix:
+        return "base"
+    if not name.startswith(prefix + "_"):
+        test.error(f"Invalid trace dumpvars test file '{name}'")
+    return name[len(prefix) + 1:]
+
+
+def _define_name(case):
+    define_case = _DEFINE_ALIASES.get(case, case)
+    token = re.sub(r"[^0-9A-Za-z]+", "_", define_case).upper()
+    return f"+define+TRACE_DUMPVARS_CASE_{token}"
+
+
+def _compile_flags(case, fmt="vcd"):
+    trace_flag = f"--trace-{fmt}"
+    flags = ["--top-module", "t", _define_name(case)]
+    if case == "add_module":
+        flags = ["--binary", "--timing", trace_flag, *flags]
+    elif case in _CPPTOP_CASES:
+        flags = ["--cc", "--exe", trace_flag, *flags, _SHARED_CPPTOP]
+    else:
+        flags = ["--binary", trace_flag, *flags]
+
+    if case in _STRUCT_TRACE_CASES:
+        flags.append("--trace-structs")
+    if case in _NO_INLINE_CASES:
+        flags.append("--fno-inline")
+    return flags
+
+
+def _has_golden_trace(test):
+    return os.path.exists(test.golden_filename) and os.path.getsize(test.golden_filename) > 0
+
+
+def run(test):
+    case = _case_name(test)
+    base_case, fmt = _split_format(case)
+
+    if base_case == "top":
+        test.passes()
+        return
+
+    test.top_filename = _SHARED_TOP
+    compile_kwargs = {"verilator_flags2": _compile_flags(base_case, fmt)}
+    if base_case in _CPPTOP_CASES:
+        compile_kwargs["make_main"] = False
+
+    if base_case in _COMPILE_FAIL_CASES:
+        test.compile(fails=True, expect_filename=test.golden_filename, **compile_kwargs)
+        test.passes()
+        return
+
+    test.compile(**compile_kwargs)
+
+    if base_case in _EXECUTE_FAIL_CASES:
+        test.execute(fails=True, expect_filename=test.golden_filename)
+        test.passes()
+        return
+
+    execute_kwargs = {}
+    if base_case == "nonconst_scope":
+        execute_kwargs["all_run_flags"] = ['+LEVEL=0']
+
+    test.execute(**execute_kwargs)
+
+    # For format variants, fall back to the base case's golden file
+    if fmt != "vcd" and not _has_golden_trace(test):
+        base_golden = os.path.join(test.t_dir, f"t_trace_dumpvars_{base_case}.out")
+        if os.path.exists(base_golden) and os.path.getsize(base_golden) > 0:
+            test.golden_filename = base_golden
+
+    if base_case == "add_module":
+        test.vcd_identical(test.obj_dir + "/simx0.vcd",
+                           test.t_dir + "/t_trace_dumpvars_add_module_0.out")
+        test.vcd_identical(test.obj_dir + "/simx1.vcd",
+                           test.t_dir + "/t_trace_dumpvars_add_module_1.out")
+    elif _has_golden_trace(test):
+        if base_case in _FILE_COMPARE_CASES:
+            test.files_identical(test.trace_filename, test.golden_filename)
+        else:
+            test.trace_identical(test.trace_filename, test.golden_filename)
+
+    test.passes()