diff --git a/src/V3Ast.h b/src/V3Ast.h
index 14b406ce4..c3bc540e8 100644
--- a/src/V3Ast.h
+++ b/src/V3Ast.h
@@ -574,7 +574,9 @@ class AstNode {
     static int	s_cloneCntGbl;	// Count of which userp is set
 
     // Attributes
-    bool	m_signed;	// Node is signed
+    bool	m_signed:1;	// Node is signed
+    //		// Space for more bools here
+
     int		m_width;	// Bit width of operation
     int		m_widthMin;	// If unsized, bitwidth of minimum implementation
     // This member ordering both allows 64 bit alignment and puts associated data together
diff --git a/src/V3Param.cpp b/src/V3Param.cpp
index 0ec851103..8ff43951e 100644
--- a/src/V3Param.cpp
+++ b/src/V3Param.cpp
@@ -164,6 +164,7 @@ private:
 		nodep->unlinkFrBack();
 	    }
 	    nodep->deleteTree(); nodep=NULL;
+	    // Normal edit rules will now recurse the replacement
 	} else {
 	    nodep->condp()->v3error("Generate If condition must evaluate to constant");
 	}
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index e896e2a20..9ad20c63d 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -865,8 +865,8 @@ public:
 // METHODs
 
 bool WidthVisitor::widthBad (AstNode* nodep, int expWidth, int expWidthMin) {
-    if (nodep->width()==0) nodep->v3fatalSrc("Under node has no expected width?? Missing Visitor func?");
-    if (expWidth==0) nodep->v3fatalSrc("Node has no expected width?? Missing Visitor func?");
+    if (nodep->width()==0) nodep->v3fatalSrc("Under node "<<nodep->prettyTypeName()<<" has no expected width?? Missing Visitor func?");
+    if (expWidth==0) nodep->v3fatalSrc("Node "<<nodep->prettyTypeName()<<" has no expected width?? Missing Visitor func?");
     if (expWidthMin==0) expWidthMin = expWidth;
     if (nodep->widthSized()  && nodep->width() != expWidthMin) return true;
     if (!nodep->widthSized() && nodep->widthMin() > expWidthMin) return true;
diff --git a/test_regress/t/t_gen_for_shuffle.pl b/test_regress/t/t_gen_for_shuffle.pl
new file mode 100644
index 000000000..7058e622f
--- /dev/null
+++ b/test_regress/t/t_gen_for_shuffle.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_gen_for_shuffle.v b/test_regress/t/t_gen_for_shuffle.v
new file mode 100644
index 000000000..92048f4d6
--- /dev/null
+++ b/test_regress/t/t_gen_for_shuffle.v
@@ -0,0 +1,79 @@
+// DESCRIPTION: Verilator: Verilog Test module
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2009 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer 	cyc=0;
+   reg [63:0] 	crc;
+   reg [63:0] 	sum;
+
+   // Take CRC data and apply to testblock inputs
+   wire [31:0]  in = crc[31:0];
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [31:0]		out;			// From test of Test.v
+   // End of automatics
+
+   Test test (/*AUTOINST*/
+	      // Outputs
+	      .out			(out[31:0]),
+	      // Inputs
+	      .in			(in[31:0]));
+
+   // Aggregate outputs into a single result vector
+   wire [63:0] result = {32'h0, out};
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc==0) begin
+	 // Setup
+	 crc <= 64'h5aef0c8d_d70a4497;
+	 sum <= 64'h0;
+      end
+      else if (cyc<10) begin
+	 sum <= 64'h0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+	 $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+	 if (crc !== 64'hc77bb9b3784ea091) $stop;
+	 // What checksum will we end up with (above print should match)
+`define EXPECTED_SUM 64'h3e3a62edb61f8c7f
+	 if (sum !== `EXPECTED_SUM) $stop;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+
+endmodule
+
+module Test (/*AUTOARG*/
+   // Outputs
+   out,
+   // Inputs
+   in
+   );
+
+   input [31:0] in;
+   output [31:0] out;
+
+   genvar 	 i;
+   generate
+      for (i=0; i<16; i=i+1) begin : gblk
+	 assign out[i*2+1:i*2] = in[(30-i*2)+1:(30-i*2)];
+      end
+   endgenerate
+endmodule
diff --git a/test_regress/t/t_inst_overwide.pl b/test_regress/t/t_inst_overwide.pl
index a92194ef4..d5af5378b 100755
--- a/test_regress/t/t_inst_overwide.pl
+++ b/test_regress/t/t_inst_overwide.pl
@@ -9,7 +9,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 compile (
 	 make_top_shell=>0,
-	 verilator_flags=> [qw(-sp -Wno-WIDTH)],
+	 verilator_flags2 => [qw(-sp -Wno-WIDTH)],
 	 verilator_make_gcc=>0,
 	 );
 
diff --git a/test_regress/t/t_param_sel.pl b/test_regress/t/t_param_sel.pl
new file mode 100644
index 000000000..7058e622f
--- /dev/null
+++ b/test_regress/t/t_param_sel.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_param_sel.v b/test_regress/t/t_param_sel.v
new file mode 100644
index 000000000..e12ff5266
--- /dev/null
+++ b/test_regress/t/t_param_sel.v
@@ -0,0 +1,93 @@
+// DESCRIPTION: Verilator: Verilog Test module
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2009 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer 	cyc=0;
+   reg [63:0] 	crc;
+   reg [63:0] 	sum;
+
+   // Take CRC data and apply to testblock inputs
+   wire [31:0]  in = crc[31:0];
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [31:0]		out;			// From test of Test.v
+   // End of automatics
+
+   Test #(16,2) test (/*AUTOINST*/
+		      // Outputs
+		      .out		(out[31:0]),
+		      // Inputs
+		      .clk		(clk),
+		      .in		(in[31:0]));
+
+   // Aggregate outputs into a single result vector
+   wire [63:0] result = {32'h0, out};
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc==0) begin
+	 // Setup
+	 crc <= 64'h5aef0c8d_d70a4497;
+	 sum <= 64'h0;
+      end
+      else if (cyc<10) begin
+	 sum <= 64'h0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+	 $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+	 if (crc !== 64'hc77bb9b3784ea091) $stop;
+	 // What checksum will we end up with (above print should match)
+`define EXPECTED_SUM 64'hf9b3a5000165ed38
+	 if (sum !== `EXPECTED_SUM) $stop;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+
+endmodule
+
+module Test (/*AUTOARG*/
+   // Outputs
+   out,
+   // Inputs
+   clk, in
+   );
+
+   input clk;
+   input [31:0] in;
+   output [31:0] out;
+
+   parameter  N = 0;
+   parameter  PASSDOWN = 1;
+
+   add #(PASSDOWN) add (.in  (in[(2*N)-1:(0*N)]),
+			.out (out));
+
+endmodule
+
+module add (/*AUTOARG*/
+   // Outputs
+   out,
+   // Inputs
+   in
+   );
+   parameter PASSDOWN = 9999;
+   input [31:0] in;
+   output [31:0] out;
+   wire 	 out = in + PASSDOWN;
+endmodule
diff --git a/test_regress/t/t_select_param.pl b/test_regress/t/t_select_param.pl
new file mode 100644
index 000000000..98dc46682
--- /dev/null
+++ b/test_regress/t/t_select_param.pl
@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;
+
diff --git a/test_regress/t/t_select_param.v b/test_regress/t/t_select_param.v
new file mode 100644
index 000000000..12b835729
--- /dev/null
+++ b/test_regress/t/t_select_param.v
@@ -0,0 +1,17 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2009 by Wilson Snyder.
+
+module t;
+   parameter [ BMSB : BLSB ] B = A[23:20]; // 3
+   parameter A = 32'h12345678;
+   parameter BLSB = A[16+:4];  // 4
+   parameter BMSB = A[7:4]; // 7
+
+   initial begin
+      if (B !== 4'h3) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule