diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index ab9541888..59532b758 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -3946,7 +3946,7 @@ class WidthVisitor final : public VNVisitor {
                 nodep->varp(varp);
                 if (nodep->access().isWriteOrRW()) V3LinkLValue::linkLValueSet(nodep);
                 if (AstIfaceRefDType* const adtypep
-                    = VN_CAST(nodep->fromp()->dtypep(), IfaceRefDType)) {
+                    = VN_CAST(nodep->fromp()->dtypep()->skipRefp(), IfaceRefDType)) {
                     nodep->varp()->sensIfacep(adtypep->ifacep());
                 }
                 UINFO(9, "     done clocking msel " << nodep);
diff --git a/test_regress/t/t_clocking_virtual.v b/test_regress/t/t_clocking_virtual.v
index 55e65ad1f..064fe9fde 100644
--- a/test_regress/t/t_clocking_virtual.v
+++ b/test_regress/t/t_clocking_virtual.v
@@ -16,6 +16,16 @@ interface Iface;
   assign out2 = out;
 endinterface
 
+interface IfaceT (
+    input bit clk
+);
+  logic data = 1'b1;
+
+  clocking cb @(posedge clk);
+    input data;
+  endclocking
+endinterface
+
 module main;
   initial begin
     #6;
@@ -47,8 +57,20 @@ module main;
   end
 endmodule
 
+module main_typedef;
+  initial begin
+    #1 t.clk = 1'b1;
+    #1 if (t.vift.cb.data != 1'b1) $stop;
+  end
+endmodule
+
 module t;
+  bit clk = 1'b0;
+  typedef virtual IfaceT VifT;
+  IfaceT ift (clk);
+  VifT vift = ift;
   main main1 ();
+  main_typedef main2 ();
   Iface mod0 ();
   virtual Iface mod1 = mod0;
 endmodule