From 6339df577031c247dcb92aae38409a588c8e7b8d Mon Sep 17 00:00:00 2001 From: Mateusz Gancarz Date: Thu, 6 Mar 2025 10:32:49 +0100 Subject: [PATCH] [#74021] drop reduntant saif tests verilog files --- test_regress/t/t_trace_saif_cmake.v | 99 ----------------------------- test_regress/t/t_trace_saif_sc.py | 2 + test_regress/t/t_trace_saif_sc.v | 98 ---------------------------- 3 files changed, 2 insertions(+), 197 deletions(-) delete mode 100644 test_regress/t/t_trace_saif_cmake.v delete mode 100644 test_regress/t/t_trace_saif_sc.v diff --git a/test_regress/t/t_trace_saif_cmake.v b/test_regress/t/t_trace_saif_cmake.v deleted file mode 100644 index 288ddadfc..000000000 --- a/test_regress/t/t_trace_saif_cmake.v +++ /dev/null @@ -1,99 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed into the Public Domain, for any use, -// Author: Yu-Sheng Lin johnjohnlys@media.ee.ntu.edu.tw -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Outputs - state, - // Inputs - clk - ); - - input clk; - - int cyc; - reg rstn; - output [4:0] state; - - parameter real fst_gparam_real = 1.23; - localparam real fst_lparam_real = 4.56; - real fst_real = 1.23; - integer fst_integer; - bit fst_bit; - logic fst_logic; - int fst_int; - shortint fst_shortint; - longint fst_longint; - byte fst_byte; - - parameter fst_parameter = 123; - localparam fst_lparam = 456; - supply0 fst_supply0; - supply1 fst_supply1; - tri0 fst_tri0; - tri1 fst_tri1; - tri fst_tri; - wire fst_wire; - - Test test (/*AUTOINST*/ - // Outputs - .state (state[4:0]), - // Inputs - .clk (clk), - .rstn (rstn)); - - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==0) begin - // Setup - rstn <= ~'1; - end - else if (cyc<10) begin - rstn <= ~'1; - end - else if (cyc<90) begin - rstn <= ~'0; - end - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - -endmodule - - -module Test ( - input clk, - input rstn, - output logic [4:0] state - ); - - logic [4:0] state_w; - logic [4:0] state_array [3]; - assign state = state_array[0]; - - always_comb begin - state_w[4] = state_array[2][0]; - state_w[3] = state_array[2][4]; - state_w[2] = state_array[2][3] ^ state_array[2][0]; - state_w[1] = state_array[2][2]; - state_w[0] = state_array[2][1]; - end - - always_ff @(posedge clk or negedge rstn) begin - if (!rstn) begin - for (int i = 0; i < 3; i++) - state_array[i] <= 'b1; - end - else begin - for (int i = 0; i < 2; i++) - state_array[i] <= state_array[i+1]; - state_array[2] <= state_w; - end - end - -endmodule diff --git a/test_regress/t/t_trace_saif_sc.py b/test_regress/t/t_trace_saif_sc.py index d8ff6413a..aae4356a6 100755 --- a/test_regress/t/t_trace_saif_sc.py +++ b/test_regress/t/t_trace_saif_sc.py @@ -11,6 +11,8 @@ import vltest_bootstrap test.scenarios('vlt_all') +test.top_filename = "t/t_trace_fst_sc.v" + if not test.have_sc: test.skip("No SystemC installed") diff --git a/test_regress/t/t_trace_saif_sc.v b/test_regress/t/t_trace_saif_sc.v deleted file mode 100644 index 52c148bd5..000000000 --- a/test_regress/t/t_trace_saif_sc.v +++ /dev/null @@ -1,98 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed into the Public Domain, for any use, -// Author: Yu-Sheng Lin johnjohnlys@media.ee.ntu.edu.tw -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; - - int cyc; - reg rstn; - - parameter real fst_gparam_real = 1.23; - localparam real fst_lparam_real = 4.56; - real fst_real = 1.23; - integer fst_integer; - bit fst_bit; - logic fst_logic; - int fst_int; - shortint fst_shortint; - longint fst_longint; - byte fst_byte; - - parameter fst_parameter = 123; - localparam fst_lparam = 456; - supply0 fst_supply0; - supply1 fst_supply1; - tri0 fst_tri0; - tri1 fst_tri1; - tri fst_tri; - wire fst_wire; - - logic [4:0] state; - - Test test (/*AUTOINST*/ - // Outputs - .state (state[4:0]), - // Inputs - .clk (clk), - .rstn (rstn)); - - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc==0) begin - // Setup - rstn <= ~'1; - end - else if (cyc<10) begin - rstn <= ~'1; - end - else if (cyc<90) begin - rstn <= ~'0; - end - else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - -endmodule - - -module Test ( - input clk, - input rstn, - output logic [4:0] state - ); - - logic [4:0] state_w; - logic [4:0] state_array [3]; - assign state = state_array[0]; - - always_comb begin - state_w[4] = state_array[2][0]; - state_w[3] = state_array[2][4]; - state_w[2] = state_array[2][3] ^ state_array[2][0]; - state_w[1] = state_array[2][2]; - state_w[0] = state_array[2][1]; - end - - always_ff @(posedge clk or negedge rstn) begin - if (!rstn) begin - for (int i = 0; i < 3; i++) - state_array[i] <= 'b1; - end - else begin - for (int i = 0; i < 2; i++) - state_array[i] <= state_array[i+1]; - state_array[2] <= state_w; - end - end - -endmodule