diff --git a/test_regress/t/t_c_this.pl b/test_regress/t/t_c_this.pl index b8edcffb4..93c3b5200 100755 --- a/test_regress/t/t_c_this.pl +++ b/test_regress/t/t_c_this.pl @@ -8,19 +8,28 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -scenarios(vlt => 1); +scenarios(simulator => 1); compile(); if ($Self->{vlt_all}) { # The word 'this' (but only the whole word 'this' should have been replaced # in the contents. - my $file = glob_one("$Self->{obj_dir}/$Self->{VM_PREFIX}___024root__DepSet_*__0.cpp"); - my $text = file_contents($file); - error("$file has 'this->clk'") if ($text =~ m/\bthis->clk\b/); - error("$file does not have 'xthis'") if ($text !~ m/\bxthis\b/); - error("$file does not have 'thisx'") if ($text !~ m/\bthisx\b/); - error("$file does not have 'xthisx'") if ($text !~ m/\bxthisx\b/); + my $has_this = 0; + my $has_xthis = 0; + my $has_thisx = 0; + my $has_xthisx = 0; + for my $file (glob_all("$Self->{obj_dir}/$Self->{VM_PREFIX}___024root__DepSet_*__0.cpp")) { + my $text = file_contents($file); + $has_this = 1 if ($text =~ m/\bthis->clk\b/); + $has_xthis = 1 if ($text =~ m/\bxthis\b/); + $has_thisx = 1 if ($text =~ m/\bthisx\b/); + $has_xthisx = 1 if ($text =~ m/\bxthisx\b/); + } + error("Some file has 'this->clk'") if $has_this; + error("No file has 'xthis'") if !$has_xthis; + error("No file has 'thisx'") if !$has_thisx; + error("No file has 'xthisx'") if !$has_xthisx; } ok(1); diff --git a/test_regress/t/t_event.v b/test_regress/t/t_event.v index 0f5384c14..9bf376779 100644 --- a/test_regress/t/t_event.v +++ b/test_regress/t/t_event.v @@ -22,9 +22,9 @@ module t(/*AUTOARG*/ event ev [3:0]; `endif - int cyc; + int cyc = 0; - int last_event; + int last_event = 0; always @(e1) begin `WRITE_VERBOSE(("[%0t] e1\n", $time)); if (!e1.triggered) $stop; diff --git a/test_regress/t/t_order_multialways.v b/test_regress/t/t_order_multialways.v index 63f75c5eb..65d500455 100644 --- a/test_regress/t/t_order_multialways.v +++ b/test_regress/t/t_order_multialways.v @@ -25,11 +25,11 @@ module t (/*AUTOARG*/ // verilator lint_off UNOPTFLAT reg [31:0] e2,f2,g2,h2; - always @ (/*AS*/f2) begin + always @ (/*AS*/f2, g2) begin h2 = {g2[15:0], g2[31:16]}; g2 = {f2[15:0], f2[31:16]}; end - always @ (/*AS*/in_a) begin + always @ (/*AS*/in_a, e2) begin f2 = {e2[15:0], e2[31:16]}; e2 = in_a; end