From 6061744c4d1d39fd76b072348e2c85ab3553a6f7 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 12 Dec 2020 20:56:35 -0500
Subject: [PATCH] Tests: Add t_dynarray_unpacked (#2314)

---
 ..._queue_array.pl => t_dynarray_unpacked.pl} |  0
 test_regress/t/t_dynarray_unpacked.v          | 34 +++++++++++++++++++
 test_regress/t/t_queue_unpacked.pl            | 21 ++++++++++++
 .../t/{t_queue_array.v => t_queue_unpacked.v} | 10 +-----
 4 files changed, 56 insertions(+), 9 deletions(-)
 rename test_regress/t/{t_queue_array.pl => t_dynarray_unpacked.pl} (100%)
 create mode 100644 test_regress/t/t_dynarray_unpacked.v
 create mode 100755 test_regress/t/t_queue_unpacked.pl
 rename test_regress/t/{t_queue_array.v => t_queue_unpacked.v} (94%)

diff --git a/test_regress/t/t_queue_array.pl b/test_regress/t/t_dynarray_unpacked.pl
similarity index 100%
rename from test_regress/t/t_queue_array.pl
rename to test_regress/t/t_dynarray_unpacked.pl
diff --git a/test_regress/t/t_dynarray_unpacked.v b/test_regress/t/t_dynarray_unpacked.v
new file mode 100644
index 000000000..530a6cbc3
--- /dev/null
+++ b/test_regress/t/t_dynarray_unpacked.v
@@ -0,0 +1,34 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2020 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define stop $stop
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
+
+module t (/*AUTOARG*/);
+
+   byte dyn [][1:0];
+
+   initial begin
+      begin
+         dyn = new [3];
+         dyn[0] = '{101, 100};
+         dyn[1] = '{111, 110};
+         dyn[2] = '{121, 120};
+`ifndef verilator // bug2314
+         `checkh(dyn[0][0], 100);
+         `checkh(dyn[0][1], 101);
+         `checkh(dyn[1][0], 110);
+         `checkh(dyn[1][1], 111);
+         `checkh(dyn[2][0], 120);
+         `checkh(dyn[2][1], 121);
+`endif
+      end
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule
diff --git a/test_regress/t/t_queue_unpacked.pl b/test_regress/t/t_queue_unpacked.pl
new file mode 100755
index 000000000..9a15dd2cc
--- /dev/null
+++ b/test_regress/t/t_queue_unpacked.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_queue_array.v b/test_regress/t/t_queue_unpacked.v
similarity index 94%
rename from test_regress/t/t_queue_array.v
rename to test_regress/t/t_queue_unpacked.v
index f6a1b57ea..566de16b6 100644
--- a/test_regress/t/t_queue_array.v
+++ b/test_regress/t/t_queue_unpacked.v
@@ -7,15 +7,7 @@
 `define stop $stop
 `define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
 
-module t (/*AUTOARG*/
-   // Inputs
-   clk
-   );
-   input clk;
-
-   integer cyc=0;
-
-   integer i;
+module t (/*AUTOARG*/);
 
    typedef string sarray_t[2];
    typedef sarray_t q_sarray_t[$];