diff --git a/test_regress/t/t_gen_local.pl b/test_regress/t/t_gen_local.pl
new file mode 100755
index 000000000..793ad4f0d
--- /dev/null
+++ b/test_regress/t/t_gen_local.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} and $Self->skip("Verilator unsupported, bug461");
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_gen_local.v b/test_regress/t/t_gen_local.v
new file mode 100644
index 000000000..dcb7354e8
--- /dev/null
+++ b/test_regress/t/t_gen_local.v
@@ -0,0 +1,35 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+   integer 	cyc=0;
+
+   localparam N = 31;
+
+   wire [31:0] 	vec;
+
+   generate
+      genvar  g;  // bug461
+      begin : topgen
+	 for (g=0; g<N; ++g) begin : gfor
+	    assign vec[g] = (g<2);
+	 end
+      end
+   endgenerate
+
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      if (cyc == 3) begin
+	 if (vec != 32'b0011) $stop;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+
+endmodule