diff --git a/test_regress/t/t_lint_width_bad.pl b/test_regress/t/t_lint_width_bad.pl
index 27b1529ad..c3abd847a 100755
--- a/test_regress/t/t_lint_width_bad.pl
+++ b/test_regress/t/t_lint_width_bad.pl
@@ -13,8 +13,13 @@ compile (
 	 v_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
-q{.*%Warning-WIDTH: t/t_lint_width_bad.v:\d+: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'in' generates 4 bits.
+q{.*%Warning-WIDTH: t/t_lint_width_bad.v:\d+: Operator VAR 'XS' expects 4 bits on the Initial value, but Initial value's CONST '\?32\?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.
 %Warning-WIDTH: Use .*
+%Warning-WIDTH: t/t_lint_width_bad.v:\d+: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'in' generates 4 bits.
+%Warning-WIDTH: t/t_lint_width_bad.v:\d+: Operator SHIFTL expects 5 bits on the LHS, but LHS's CONST '1'h1' generates 1 bits.
+%Warning-WIDTH: t/t_lint_width_bad.v:\d+: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS's SHIFTL generates 7 bits.
+%Warning-WIDTH: t/t_lint_width_bad.v:\d+: Operator ADD expects 3 bits on the LHS, but LHS's VARREF 'one' generates 1 bits.
+%Warning-WIDTH: t/t_lint_width_bad.v:\d+: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits.
 %Error: Exiting due to.*},
     );
 
diff --git a/test_regress/t/t_lint_width_bad.v b/test_regress/t/t_lint_width_bad.v
index 7fb3f06ff..8327029e0 100644
--- a/test_regress/t/t_lint_width_bad.v
+++ b/test_regress/t/t_lint_width_bad.v
@@ -5,11 +5,31 @@
 
 module t ();
 
+   // See also t_math_width
+
    // This shows the uglyness in width warnings across param modules
    // TODO: Would be nice to also show relevant parameter settings
    p #(.WIDTH(4)) p4 (.in(4'd0));
    p #(.WIDTH(5)) p5 (.in(5'd0));
 
+   //====
+   localparam [3:0]	XS = 'hx;  // User presumably intended to use 'x
+
+   //====
+   wire [4:0] c = 1'b1 << 2;  // No width warning, as is common syntax
+   wire [4:0] d = (1'b1 << 2) + 5'b1;  // Has warning as not obvious what expression width is
+
+   //====
+   localparam		WIDTH = 6;
+   wire 		one_bit;
+   wire	[2:0]		shifter = 1;
+   wire [WIDTH-1:0] 	masked = (({{(WIDTH){1'b0}}, one_bit}) << shifter);
+
+   //====
+   // We presently warn here, in theory we could detect if the number of one bit additions could overflow the LHS
+   wire 		one = 1;
+   wire [2:0] 		cnt  = (one + one + one + one);
+
 endmodule
 
 module p
diff --git a/test_regress/t/t_math_width.v b/test_regress/t/t_math_width.v
index 693f034f7..114996abe 100644
--- a/test_regress/t/t_math_width.v
+++ b/test_regress/t/t_math_width.v
@@ -7,6 +7,16 @@ module t ();
 
    // See also t_lint_width
 
+   parameter A_ONE = '1;
+   // verilator lint_off WIDTH
+   parameter [3:0] A_W4 = A_ONE;
+   // verilator lint_on WIDTH
+   initial begin
+      if ($bits(A_ONE) != 1 || A_ONE !== 1'b1) $stop;
+      if ($bits(A_W4) != 4) $stop;
+      if (A_W4 != 4'b0001) $stop;
+   end
+
    b #(.B_WIDTH(48)) b ();
 
    reg [4:0] c;
@@ -17,6 +27,15 @@ module t ();
       if (c != 5'b1000) $stop;
    end
 
+   localparam D_TT = 32'd23;
+   localparam D_SIX = 6;
+   // verilator lint_off WIDTH
+   localparam [5:0] D_SUB = D_TT - D_SIX;
+   // verilator lint_on WIDTH
+   initial begin
+      if (D_SUB != 17) $stop;
+   end
+
    initial begin
       $write("*-* All Finished *-*\n");
       $finish;